1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PPCInstrBuilder.h"
17 #include "PPCRegisterInfo.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineDebugInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineLocation.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/ADT/STLExtras.h"
39 /// getRegisterNumbering - Given the enum value for some register, e.g.
40 /// PPC::F14, return the number that it corresponds to (e.g. 14).
41 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
43 case PPC::R0 : case PPC::F0 : case PPC::V0 : case PPC::CR0: return 0;
44 case PPC::R1 : case PPC::F1 : case PPC::V1 : case PPC::CR1: return 1;
45 case PPC::R2 : case PPC::F2 : case PPC::V2 : case PPC::CR2: return 2;
46 case PPC::R3 : case PPC::F3 : case PPC::V3 : case PPC::CR3: return 3;
47 case PPC::R4 : case PPC::F4 : case PPC::V4 : case PPC::CR4: return 4;
48 case PPC::R5 : case PPC::F5 : case PPC::V5 : case PPC::CR5: return 5;
49 case PPC::R6 : case PPC::F6 : case PPC::V6 : case PPC::CR6: return 6;
50 case PPC::R7 : case PPC::F7 : case PPC::V7 : case PPC::CR7: return 7;
51 case PPC::R8 : case PPC::F8 : case PPC::V8 : return 8;
52 case PPC::R9 : case PPC::F9 : case PPC::V9 : return 9;
53 case PPC::R10: case PPC::F10: case PPC::V10: return 10;
54 case PPC::R11: case PPC::F11: case PPC::V11: return 11;
55 case PPC::R12: case PPC::F12: case PPC::V12: return 12;
56 case PPC::R13: case PPC::F13: case PPC::V13: return 13;
57 case PPC::R14: case PPC::F14: case PPC::V14: return 14;
58 case PPC::R15: case PPC::F15: case PPC::V15: return 15;
59 case PPC::R16: case PPC::F16: case PPC::V16: return 16;
60 case PPC::R17: case PPC::F17: case PPC::V17: return 17;
61 case PPC::R18: case PPC::F18: case PPC::V18: return 18;
62 case PPC::R19: case PPC::F19: case PPC::V19: return 19;
63 case PPC::R20: case PPC::F20: case PPC::V20: return 20;
64 case PPC::R21: case PPC::F21: case PPC::V21: return 21;
65 case PPC::R22: case PPC::F22: case PPC::V22: return 22;
66 case PPC::R23: case PPC::F23: case PPC::V23: return 23;
67 case PPC::R24: case PPC::F24: case PPC::V24: return 24;
68 case PPC::R25: case PPC::F25: case PPC::V25: return 25;
69 case PPC::R26: case PPC::F26: case PPC::V26: return 26;
70 case PPC::R27: case PPC::F27: case PPC::V27: return 27;
71 case PPC::R28: case PPC::F28: case PPC::V28: return 28;
72 case PPC::R29: case PPC::F29: case PPC::V29: return 29;
73 case PPC::R30: case PPC::F30: case PPC::V30: return 30;
74 case PPC::R31: case PPC::F31: case PPC::V31: return 31;
76 std::cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
81 PPCRegisterInfo::PPCRegisterInfo()
82 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
83 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
84 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
85 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
86 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
87 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
88 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
89 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
90 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
94 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
95 MachineBasicBlock::iterator MI,
96 unsigned SrcReg, int FrameIdx,
97 const TargetRegisterClass *RC) const {
98 if (SrcReg == PPC::LR) {
99 // FIXME: this spills LR immediately to memory in one step. To do this, we
100 // use R11, which we know cannot be used in the prolog/epilog. This is a
102 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
103 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
104 } else if (RC == PPC::CRRCRegisterClass) {
105 // We need to store the CR in the low 4-bits of the saved value. First,
106 // issue a MFCR to save all of the CRBits.
107 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
109 // If the saved register wasn't CR0, shift the bits left so that they are in
111 if (SrcReg != PPC::CR0) {
112 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
113 // rlwinm r11, r11, ShiftBits, 0, 31.
114 BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R11)
115 .addReg(PPC::R11).addImm(ShiftBits).addImm(0).addImm(31);
118 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
119 } else if (RC == PPC::GPRCRegisterClass) {
120 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
121 } else if (RC == PPC::G8RCRegisterClass) {
122 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx);
123 } else if (RC == PPC::F8RCRegisterClass) {
124 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
125 } else if (RC == PPC::F4RCRegisterClass) {
126 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
127 } else if (RC == PPC::VRRCRegisterClass) {
128 // We don't have indexed addressing for vector loads. Emit:
130 // Dest = LVX R0, R11
132 // FIXME: We use R0 here, because it isn't available for RA.
133 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
134 BuildMI(MBB, MI, PPC::STVX, 3)
135 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
137 assert(0 && "Unknown regclass!");
143 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
144 MachineBasicBlock::iterator MI,
145 unsigned DestReg, int FrameIdx,
146 const TargetRegisterClass *RC) const {
147 if (DestReg == PPC::LR) {
148 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
149 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
150 } else if (RC == PPC::CRRCRegisterClass) {
151 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
153 // If the reloaded register isn't CR0, shift the bits right so that they are
154 // in the right CR's slot.
155 if (DestReg != PPC::CR0) {
156 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
157 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
158 BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R11)
159 .addReg(PPC::R11).addImm(32-ShiftBits).addImm(0).addImm(31);
162 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
163 } else if (RC == PPC::GPRCRegisterClass) {
164 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
165 } else if (RC == PPC::G8RCRegisterClass) {
166 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
167 } else if (RC == PPC::F8RCRegisterClass) {
168 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
169 } else if (RC == PPC::F4RCRegisterClass) {
170 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
171 } else if (RC == PPC::VRRCRegisterClass) {
172 // We don't have indexed addressing for vector loads. Emit:
174 // Dest = LVX R0, R11
176 // FIXME: We use R0 here, because it isn't available for RA.
177 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
178 BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
180 assert(0 && "Unknown regclass!");
185 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
186 MachineBasicBlock::iterator MI,
187 unsigned DestReg, unsigned SrcReg,
188 const TargetRegisterClass *RC) const {
189 if (RC == PPC::GPRCRegisterClass) {
190 BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
191 } else if (RC == PPC::G8RCRegisterClass) {
192 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
193 } else if (RC == PPC::F4RCRegisterClass) {
194 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
195 } else if (RC == PPC::F8RCRegisterClass) {
196 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
197 } else if (RC == PPC::CRRCRegisterClass) {
198 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
199 } else if (RC == PPC::VRRCRegisterClass) {
200 BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
202 std::cerr << "Attempt to copy register that is not GPR or FPR";
207 const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
208 static const unsigned CalleeSaveRegs[] = {
237 return CalleeSaveRegs;
240 const TargetRegisterClass* const*
241 PPCRegisterInfo::getCalleeSaveRegClasses() const {
242 static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
243 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
244 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
245 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
246 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
247 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
248 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
249 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
250 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
251 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
252 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
253 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
254 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
255 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
256 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
257 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
258 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
259 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
260 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
261 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
262 &PPC::CRRCRegClass, &PPC::CRRCRegClass,
263 &PPC::CRRCRegClass, &PPC::VRRCRegClass,
264 &PPC::VRRCRegClass, &PPC::VRRCRegClass,
265 &PPC::VRRCRegClass, &PPC::VRRCRegClass,
266 &PPC::VRRCRegClass, &PPC::VRRCRegClass,
267 &PPC::VRRCRegClass, &PPC::VRRCRegClass,
268 &PPC::VRRCRegClass, &PPC::VRRCRegClass,
269 &PPC::VRRCRegClass, &PPC::GPRCRegClass, 0
271 return CalleeSaveRegClasses;
274 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
275 /// copy instructions, turning them into load/store instructions.
276 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
278 int FrameIndex) const {
279 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
280 // it takes more than one instruction to store it.
281 unsigned Opc = MI->getOpcode();
283 if ((Opc == PPC::OR4 &&
284 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
285 if (OpNum == 0) { // move -> store
286 unsigned InReg = MI->getOperand(1).getReg();
287 return addFrameReference(BuildMI(PPC::STW,
288 3).addReg(InReg), FrameIndex);
289 } else { // move -> load
290 unsigned OutReg = MI->getOperand(0).getReg();
291 return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
293 } else if ((Opc == PPC::OR8 &&
294 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
295 if (OpNum == 0) { // move -> store
296 unsigned InReg = MI->getOperand(1).getReg();
297 return addFrameReference(BuildMI(PPC::STD,
298 3).addReg(InReg), FrameIndex);
299 } else { // move -> load
300 unsigned OutReg = MI->getOperand(0).getReg();
301 return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex);
303 } else if (Opc == PPC::FMRD) {
304 if (OpNum == 0) { // move -> store
305 unsigned InReg = MI->getOperand(1).getReg();
306 return addFrameReference(BuildMI(PPC::STFD,
307 3).addReg(InReg), FrameIndex);
308 } else { // move -> load
309 unsigned OutReg = MI->getOperand(0).getReg();
310 return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex);
312 } else if (Opc == PPC::FMRS) {
313 if (OpNum == 0) { // move -> store
314 unsigned InReg = MI->getOperand(1).getReg();
315 return addFrameReference(BuildMI(PPC::STFS,
316 3).addReg(InReg), FrameIndex);
317 } else { // move -> load
318 unsigned OutReg = MI->getOperand(0).getReg();
319 return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex);
325 //===----------------------------------------------------------------------===//
326 // Stack Frame Processing methods
327 //===----------------------------------------------------------------------===//
329 // hasFP - Return true if the specified function should have a dedicated frame
330 // pointer register. This is true if the function has variable sized allocas or
331 // if frame pointer elimination is disabled.
333 static bool hasFP(const MachineFunction &MF) {
334 const MachineFrameInfo *MFI = MF.getFrameInfo();
335 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
337 // If frame pointers are forced, or if there are variable sized stack objects,
338 // use a frame pointer.
340 return NoFramePointerElim || MFI->hasVarSizedObjects();
343 void PPCRegisterInfo::
344 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
345 MachineBasicBlock::iterator I) const {
347 // If we have a frame pointer, convert as follows:
348 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
349 // ADJCALLSTACKUP -> addi, r1, r1, amount
350 MachineInstr *Old = I;
351 unsigned Amount = Old->getOperand(0).getImmedValue();
353 // We need to keep the stack aligned properly. To do this, we round the
354 // amount of space needed for the outgoing arguments up to the next
355 // alignment boundary.
356 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
357 Amount = (Amount+Align-1)/Align*Align;
359 // Replace the pseudo instruction with a new instruction...
360 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
361 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(-Amount);
363 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
364 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(Amount);
372 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
374 MachineInstr &MI = *II;
375 MachineBasicBlock &MBB = *MI.getParent();
376 MachineFunction &MF = *MBB.getParent();
378 while (!MI.getOperand(i).isFrameIndex()) {
380 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
383 int FrameIndex = MI.getOperand(i).getFrameIndex();
385 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
386 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1);
388 // Take into account whether it's an add or mem instruction
389 unsigned OffIdx = (i == 2) ? 1 : 2;
391 // Now add the frame object offset to the offset from r1.
392 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
393 MI.getOperand(OffIdx).getImmedValue();
395 // If we're not using a Frame Pointer that has been set to the value of the
396 // SP before having the stack size subtracted from it, then add the stack size
397 // to Offset to get the correct offset.
398 Offset += MF.getFrameInfo()->getStackSize();
400 if (Offset > 32767 || Offset < -32768) {
401 // Insert a set of r0 with the full offset value before the ld, st, or add
402 MachineBasicBlock *MBB = MI.getParent();
403 BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addImm(Offset >> 16);
404 BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset);
406 // convert into indexed form of the instruction
407 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
408 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
409 assert(ImmToIdxMap.count(MI.getOpcode()) &&
410 "No indexed form of load or store available!");
411 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
412 MI.setOpcode(NewOpcode);
413 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg());
414 MI.getOperand(2).ChangeToRegister(PPC::R0);
416 switch (MI.getOpcode()) {
421 assert((Offset & 3) == 0 && "Invalid frame offset!");
422 Offset >>= 2; // The actual encoded value has the low two bits zero.
425 MI.getOperand(OffIdx).ChangeToImmediate(Offset);
429 /// VRRegNo - Map from a numbered VR register to its enum value.
431 static const unsigned short VRRegNo[] = {
432 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
433 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
434 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
435 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
438 /// RemoveVRSaveCode - We have found that this function does not need any code
439 /// to manipulate the VRSAVE register, even though it uses vector registers.
440 /// This can happen when the only registers used are known to be live in or out
441 /// of the function. Remove all of the VRSAVE related code from the function.
442 static void RemoveVRSaveCode(MachineInstr *MI) {
443 MachineBasicBlock *Entry = MI->getParent();
444 MachineFunction *MF = Entry->getParent();
446 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
447 MachineBasicBlock::iterator MBBI = MI;
449 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
450 MBBI->eraseFromParent();
452 bool RemovedAllMTVRSAVEs = true;
453 // See if we can find and remove the MTVRSAVE instruction from all of the
455 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
456 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
457 // If last instruction is a return instruction, add an epilogue
458 if (!I->empty() && TII.isReturn(I->back().getOpcode())) {
459 bool FoundIt = false;
460 for (MBBI = I->end(); MBBI != I->begin(); ) {
462 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
463 MBBI->eraseFromParent(); // remove it.
468 RemovedAllMTVRSAVEs &= FoundIt;
472 // If we found and removed all MTVRSAVE instructions, remove the read of
474 if (RemovedAllMTVRSAVEs) {
476 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
478 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
479 MBBI->eraseFromParent();
482 // Finally, nuke the UPDATE_VRSAVE.
483 MI->eraseFromParent();
486 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
487 // instruction selector. Based on the vector registers that have been used,
488 // transform this into the appropriate ORI instruction.
489 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) {
490 unsigned UsedRegMask = 0;
491 for (unsigned i = 0; i != 32; ++i)
492 if (UsedRegs[VRRegNo[i]])
493 UsedRegMask |= 1 << (31-i);
495 // Live in and live out values already must be in the mask, so don't bother
497 MachineFunction *MF = MI->getParent()->getParent();
498 for (MachineFunction::livein_iterator I =
499 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) {
500 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
501 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
502 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
504 for (MachineFunction::liveout_iterator I =
505 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) {
506 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
507 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
508 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
511 unsigned SrcReg = MI->getOperand(1).getReg();
512 unsigned DstReg = MI->getOperand(0).getReg();
513 // If no registers are used, turn this into a copy.
514 if (UsedRegMask == 0) {
515 // Remove all VRSAVE code.
516 RemoveVRSaveCode(MI);
518 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
519 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
520 .addReg(SrcReg).addImm(UsedRegMask);
521 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
522 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
523 .addReg(SrcReg).addImm(UsedRegMask >> 16);
525 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
526 .addReg(SrcReg).addImm(UsedRegMask >> 16);
527 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
528 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
531 // Remove the old UPDATE_VRSAVE instruction.
532 MI->eraseFromParent();
536 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
537 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
538 MachineBasicBlock::iterator MBBI = MBB.begin();
539 MachineFrameInfo *MFI = MF.getFrameInfo();
540 MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo();
542 // Do we have a frame pointer for this function?
543 bool HasFP = hasFP(MF);
545 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
547 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
548 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
549 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
554 // Move MBBI back to the beginning of the function.
557 // Get the number of bytes to allocate from the FrameInfo
558 unsigned NumBytes = MFI->getStackSize();
560 // Get the alignments provided by the target, and the maximum alignment
561 // (if any) of the fixed frame objects.
562 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
563 unsigned MaxAlign = MFI->getMaxAlignment();
565 // If we have calls, we cannot use the red zone to store callee save registers
566 // and we must set up a stack frame, so calculate the necessary size here.
567 if (MFI->hasCalls()) {
568 // We reserve argument space for call sites in the function immediately on
569 // entry to the current function. This eliminates the need for add/sub
570 // brackets around call sites.
571 NumBytes += MFI->getMaxCallFrameSize();
574 // If we are a leaf function, and use up to 224 bytes of stack space,
575 // and don't have a frame pointer, then we do not need to adjust the stack
576 // pointer (we fit in the Red Zone).
577 if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() &&
578 MaxAlign <= TargetAlign)) {
579 MFI->setStackSize(0);
583 // Add the size of R1 to NumBytes size for the store of R1 to the bottom
584 // of the stack and round the size to a multiple of the alignment.
585 unsigned Align = std::max(TargetAlign, MaxAlign);
586 unsigned GPRSize = 4;
587 unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize;
588 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
590 // Update frame info to pretend that this is part of the stack...
591 MFI->setStackSize(NumBytes);
592 int NegNumbytes = -NumBytes;
594 // Adjust stack pointer: r1 -= numbytes.
595 // If there is a preferred stack alignment, align R1 now
596 if (MaxAlign > TargetAlign) {
597 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!");
598 assert(isInt16(0-NumBytes) && "Unhandled stack size and alignment!");
599 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
600 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
601 BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
603 BuildMI(MBB, MBBI, PPC::STWUX, 3)
604 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
605 } else if (NumBytes <= 32768) {
606 BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addImm(NegNumbytes)
609 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegNumbytes >> 16);
610 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
611 .addImm(NegNumbytes & 0xFFFF);
612 BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
616 if (DebugInfo && DebugInfo->hasInfo()) {
617 std::vector<MachineMove *> &Moves = DebugInfo->getFrameMoves();
618 unsigned LabelID = DebugInfo->NextLabelID();
620 // Show update of SP.
621 MachineLocation Dst(MachineLocation::VirtualFP);
622 MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes);
623 Moves.push_back(new MachineMove(LabelID, Dst, Src));
625 BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addImm(LabelID);
628 // If there is a frame pointer, copy R1 (SP) into R31 (FP)
630 BuildMI(MBB, MBBI, PPC::STW, 3)
631 .addReg(PPC::R31).addImm(GPRSize).addReg(PPC::R1);
632 BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
636 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
637 MachineBasicBlock &MBB) const {
638 MachineBasicBlock::iterator MBBI = prior(MBB.end());
639 assert(MBBI->getOpcode() == PPC::BLR &&
640 "Can only insert epilog into returning blocks");
642 // Get alignment info so we know how to restore r1
643 const MachineFrameInfo *MFI = MF.getFrameInfo();
644 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
646 // Get the number of bytes allocated from the FrameInfo.
647 unsigned NumBytes = MFI->getStackSize();
648 unsigned GPRSize = 4;
651 // If this function has a frame pointer, load the saved stack pointer from
654 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
655 .addImm(GPRSize).addReg(PPC::R31);
658 // The loaded (or persistent) stack pointer value is offseted by the 'stwu'
659 // on entry to the function. Add this offset back now.
660 if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) {
661 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
662 .addReg(PPC::R1).addImm(NumBytes);
664 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addImm(0).addReg(PPC::R1);
669 unsigned PPCRegisterInfo::getRARegister() const {
673 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
674 return hasFP(MF) ? PPC::R31 : PPC::R1;
677 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves)
679 // Initial state is the frame pointer is R1.
680 MachineLocation Dst(MachineLocation::VirtualFP);
681 MachineLocation Src(PPC::R1, 0);
682 Moves.push_back(new MachineMove(0, Dst, Src));
685 #include "PPCGenRegisterInfo.inc"