1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PPCInstrBuilder.h"
17 #include "PPCRegisterInfo.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/ADT/STLExtras.h"
35 PPCRegisterInfo::PPCRegisterInfo()
36 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
37 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
38 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
39 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
40 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
41 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
42 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
43 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
44 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
48 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator MI,
50 unsigned SrcReg, int FrameIdx,
51 const TargetRegisterClass *RC) const {
52 if (SrcReg == PPC::LR) {
53 // FIXME: this spills LR immediately to memory in one step. To do this, we
54 // use R11, which we know cannot be used in the prolog/epilog. This is a
56 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
57 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
58 } else if (RC == PPC::CRRCRegisterClass) {
59 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
60 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
61 } else if (RC == PPC::GPRCRegisterClass) {
62 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
63 } else if (RC == PPC::G8RCRegisterClass) {
64 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx);
65 } else if (RC == PPC::F8RCRegisterClass) {
66 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
67 } else if (RC == PPC::F4RCRegisterClass) {
68 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
69 } else if (RC == PPC::VRRCRegisterClass) {
70 // We don't have indexed addressing for vector loads. Emit:
74 // FIXME: We use R0 here, because it isn't available for RA.
75 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
76 BuildMI(MBB, MI, PPC::STVX, 3)
77 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
79 assert(0 && "Unknown regclass!");
85 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
86 MachineBasicBlock::iterator MI,
87 unsigned DestReg, int FrameIdx,
88 const TargetRegisterClass *RC) const {
89 if (DestReg == PPC::LR) {
90 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
91 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
92 } else if (RC == PPC::CRRCRegisterClass) {
93 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
94 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
95 } else if (RC == PPC::GPRCRegisterClass) {
96 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
97 } else if (RC == PPC::G8RCRegisterClass) {
98 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
99 } else if (RC == PPC::F8RCRegisterClass) {
100 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
101 } else if (RC == PPC::F4RCRegisterClass) {
102 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
103 } else if (RC == PPC::VRRCRegisterClass) {
104 // We don't have indexed addressing for vector loads. Emit:
106 // Dest = LVX R0, R11
108 // FIXME: We use R0 here, because it isn't available for RA.
109 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
110 BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
112 assert(0 && "Unknown regclass!");
117 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
118 MachineBasicBlock::iterator MI,
119 unsigned DestReg, unsigned SrcReg,
120 const TargetRegisterClass *RC) const {
123 if (RC == PPC::GPRCRegisterClass) {
124 BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
125 } else if (RC == PPC::G8RCRegisterClass) {
126 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
127 } else if (RC == PPC::F4RCRegisterClass) {
128 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
129 } else if (RC == PPC::F8RCRegisterClass) {
130 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
131 } else if (RC == PPC::CRRCRegisterClass) {
132 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
133 } else if (RC == PPC::VRRCRegisterClass) {
134 BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
136 std::cerr << "Attempt to copy register that is not GPR or FPR";
141 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
142 /// copy instructions, turning them into load/store instructions.
143 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
145 int FrameIndex) const {
146 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
147 // it takes more than one instruction to store it.
148 unsigned Opc = MI->getOpcode();
150 if ((Opc == PPC::OR4 &&
151 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
152 if (OpNum == 0) { // move -> store
153 unsigned InReg = MI->getOperand(1).getReg();
154 return addFrameReference(BuildMI(PPC::STW,
155 3).addReg(InReg), FrameIndex);
156 } else { // move -> load
157 unsigned OutReg = MI->getOperand(0).getReg();
158 return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
160 } else if ((Opc == PPC::OR8 &&
161 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
162 if (OpNum == 0) { // move -> store
163 unsigned InReg = MI->getOperand(1).getReg();
164 return addFrameReference(BuildMI(PPC::STD,
165 3).addReg(InReg), FrameIndex);
166 } else { // move -> load
167 unsigned OutReg = MI->getOperand(0).getReg();
168 return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex);
170 } else if (Opc == PPC::FMRD) {
171 if (OpNum == 0) { // move -> store
172 unsigned InReg = MI->getOperand(1).getReg();
173 return addFrameReference(BuildMI(PPC::STFD,
174 3).addReg(InReg), FrameIndex);
175 } else { // move -> load
176 unsigned OutReg = MI->getOperand(0).getReg();
177 return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex);
179 } else if (Opc == PPC::FMRS) {
180 if (OpNum == 0) { // move -> store
181 unsigned InReg = MI->getOperand(1).getReg();
182 return addFrameReference(BuildMI(PPC::STFS,
183 3).addReg(InReg), FrameIndex);
184 } else { // move -> load
185 unsigned OutReg = MI->getOperand(0).getReg();
186 return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex);
192 //===----------------------------------------------------------------------===//
193 // Stack Frame Processing methods
194 //===----------------------------------------------------------------------===//
196 // hasFP - Return true if the specified function should have a dedicated frame
197 // pointer register. This is true if the function has variable sized allocas or
198 // if frame pointer elimination is disabled.
200 static bool hasFP(MachineFunction &MF) {
201 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
204 void PPCRegisterInfo::
205 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
206 MachineBasicBlock::iterator I) const {
208 // If we have a frame pointer, convert as follows:
209 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
210 // ADJCALLSTACKUP -> addi, r1, r1, amount
211 MachineInstr *Old = I;
212 unsigned Amount = Old->getOperand(0).getImmedValue();
214 // We need to keep the stack aligned properly. To do this, we round the
215 // amount of space needed for the outgoing arguments up to the next
216 // alignment boundary.
217 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
218 Amount = (Amount+Align-1)/Align*Align;
220 // Replace the pseudo instruction with a new instruction...
221 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
222 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(-Amount);
224 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
225 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(Amount);
233 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
235 MachineInstr &MI = *II;
236 MachineBasicBlock &MBB = *MI.getParent();
237 MachineFunction &MF = *MBB.getParent();
239 while (!MI.getOperand(i).isFrameIndex()) {
241 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
244 int FrameIndex = MI.getOperand(i).getFrameIndex();
246 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
247 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
249 // Take into account whether it's an add or mem instruction
250 unsigned OffIdx = (i == 2) ? 1 : 2;
252 // Now add the frame object offset to the offset from r1.
253 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
254 MI.getOperand(OffIdx).getImmedValue();
256 // If we're not using a Frame Pointer that has been set to the value of the
257 // SP before having the stack size subtracted from it, then add the stack size
258 // to Offset to get the correct offset.
259 Offset += MF.getFrameInfo()->getStackSize();
261 if (Offset > 32767 || Offset < -32768) {
262 // Insert a set of r0 with the full offset value before the ld, st, or add
263 MachineBasicBlock *MBB = MI.getParent();
264 BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16);
265 BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset);
267 // convert into indexed form of the instruction
268 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
269 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
270 assert(ImmToIdxMap.count(MI.getOpcode()) &&
271 "No indexed form of load or store available!");
272 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
273 MI.setOpcode(NewOpcode);
274 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
275 MI.SetMachineOperandReg(2, PPC::R0);
277 switch (MI.getOpcode()) {
282 assert((Offset & 3) == 0 && "Invalid frame offset!");
283 Offset >>= 2; // The actual encoded value has the low two bits zero.
286 MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
291 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
292 // instruction selector. Based on the vector registers that have been used,
293 // transform this into the appropriate ORI instruction.
294 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) {
295 unsigned UsedRegMask = 0;
296 #define HANDLEREG(N) if (UsedRegs[PPC::V##N]) UsedRegMask |= 1 << (31-N)
297 HANDLEREG( 0); HANDLEREG( 1); HANDLEREG( 2); HANDLEREG( 3);
298 HANDLEREG( 4); HANDLEREG( 5); HANDLEREG( 6); HANDLEREG( 7);
299 HANDLEREG( 8); HANDLEREG( 9); HANDLEREG(10); HANDLEREG(11);
300 HANDLEREG(12); HANDLEREG(13); HANDLEREG(14); HANDLEREG(15);
301 HANDLEREG(16); HANDLEREG(17); HANDLEREG(18); HANDLEREG(19);
302 HANDLEREG(20); HANDLEREG(21); HANDLEREG(22); HANDLEREG(23);
303 HANDLEREG(24); HANDLEREG(25); HANDLEREG(26); HANDLEREG(27);
304 HANDLEREG(28); HANDLEREG(29); HANDLEREG(30); HANDLEREG(31);
306 unsigned SrcReg = MI->getOperand(1).getReg();
307 unsigned DstReg = MI->getOperand(0).getReg();
308 // If no registers are used, turn this into a copy.
309 if (UsedRegMask == 0) {
310 if (SrcReg != DstReg)
311 BuildMI(*MI->getParent(), MI, PPC::OR4, 2, DstReg)
312 .addReg(SrcReg).addReg(SrcReg);
313 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
314 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
315 .addReg(SrcReg).addImm(UsedRegMask);
316 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
317 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
318 .addReg(SrcReg).addImm(UsedRegMask >> 16);
320 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
321 .addReg(SrcReg).addImm(UsedRegMask >> 16);
322 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
323 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
326 // Remove the old UPDATE_VRSAVE instruction.
327 MI->getParent()->erase(MI);
331 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
332 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
333 MachineBasicBlock::iterator MBBI = MBB.begin();
334 MachineFrameInfo *MFI = MF.getFrameInfo();
336 // Scan the first few instructions of the prolog, looking for an UPDATE_VRSAVE
337 // instruction. If we find it, process it.
338 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
339 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
340 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
345 // Move MBBI back to the beginning of the function.
348 // Get the number of bytes to allocate from the FrameInfo
349 unsigned NumBytes = MFI->getStackSize();
351 // Get the alignments provided by the target, and the maximum alignment
352 // (if any) of the fixed frame objects.
353 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
354 unsigned MaxAlign = MFI->getMaxAlignment();
356 // If we have calls, we cannot use the red zone to store callee save registers
357 // and we must set up a stack frame, so calculate the necessary size here.
358 if (MFI->hasCalls()) {
359 // We reserve argument space for call sites in the function immediately on
360 // entry to the current function. This eliminates the need for add/sub
361 // brackets around call sites.
362 NumBytes += MFI->getMaxCallFrameSize();
365 // If we are a leaf function, and use up to 224 bytes of stack space,
366 // and don't have a frame pointer, then we do not need to adjust the stack
367 // pointer (we fit in the Red Zone).
368 if ((NumBytes == 0) || (NumBytes <= 224 && !hasFP(MF) && !MFI->hasCalls() &&
369 MaxAlign <= TargetAlign)) {
370 MFI->setStackSize(0);
374 // Add the size of R1 to NumBytes size for the store of R1 to the bottom
375 // of the stack and round the size to a multiple of the alignment.
376 unsigned Align = std::max(TargetAlign, MaxAlign);
377 unsigned GPRSize = 4;
378 unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize;
379 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
381 // Update frame info to pretend that this is part of the stack...
382 MFI->setStackSize(NumBytes);
384 // Adjust stack pointer: r1 -= numbytes.
385 if (NumBytes <= 32768) {
386 BuildMI(MBB, MBBI, PPC::STWU, 3)
387 .addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
389 int NegNumbytes = -NumBytes;
390 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
391 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0)
392 .addReg(PPC::R0).addImm(NegNumbytes & 0xFFFF);
393 BuildMI(MBB, MBBI, PPC::STWUX, 3)
394 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
397 // If there is a preferred stack alignment, align R1 now
398 // FIXME: If this ever matters, this could be made more efficient by folding
399 // this into the code above, so that we don't issue two store+update
401 if (MaxAlign > TargetAlign) {
402 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!");
403 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
404 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
405 BuildMI(MBB, MBBI, PPC::SUBFIC, 2,PPC::R0).addReg(PPC::R0).addImm(MaxAlign);
406 BuildMI(MBB, MBBI, PPC::STWUX, 3)
407 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
410 // If there is a frame pointer, copy R1 (SP) into R31 (FP)
412 BuildMI(MBB, MBBI, PPC::STW, 3)
413 .addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
414 BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
418 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
419 MachineBasicBlock &MBB) const {
420 MachineBasicBlock::iterator MBBI = prior(MBB.end());
421 assert(MBBI->getOpcode() == PPC::BLR &&
422 "Can only insert epilog into returning blocks");
424 // Get the number of bytes allocated from the FrameInfo.
425 unsigned NumBytes = MF.getFrameInfo()->getStackSize();
426 unsigned GPRSize = 4;
429 // If this function has a frame pointer, load the saved stack pointer from
432 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
433 .addSImm(GPRSize).addReg(PPC::R31);
436 // The loaded (or persistent) stack pointer value is offseted by the 'stwu'
437 // on entry to the function. Add this offset back now.
438 if (NumBytes < 32768) {
439 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
440 .addReg(PPC::R1).addSImm(NumBytes);
442 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NumBytes >> 16);
443 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0)
444 .addReg(PPC::R0).addImm(NumBytes & 0xFFFF);
445 BuildMI(MBB, MBBI, PPC::ADD4, 2, PPC::R1)
446 .addReg(PPC::R0).addReg(PPC::R1);
451 #include "PPCGenRegisterInfo.inc"