1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PPCInstrBuilder.h"
17 #include "PPCRegisterInfo.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/ADT/STLExtras.h"
35 PPCRegisterInfo::PPCRegisterInfo()
36 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
37 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
38 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
39 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
40 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
41 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
42 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
43 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
44 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
48 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator MI,
50 unsigned SrcReg, int FrameIdx,
51 const TargetRegisterClass *RC) const {
52 if (SrcReg == PPC::LR) {
53 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
54 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
55 } else if (RC == PPC::CRRCRegisterClass) {
56 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
57 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
58 } else if (RC == PPC::GPRCRegisterClass) {
59 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
60 } else if (RC == PPC::G8RCRegisterClass) {
61 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx);
62 } else if (RC == PPC::F8RCRegisterClass) {
63 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
64 } else if (RC == PPC::F4RCRegisterClass) {
65 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
67 assert(0 && "Unknown regclass!");
73 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
74 MachineBasicBlock::iterator MI,
75 unsigned DestReg, int FrameIdx,
76 const TargetRegisterClass *RC) const {
77 if (DestReg == PPC::LR) {
78 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
79 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
80 } else if (RC == PPC::CRRCRegisterClass) {
81 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
82 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
83 } else if (RC == PPC::GPRCRegisterClass) {
84 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
85 } else if (RC == PPC::G8RCRegisterClass) {
86 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
87 } else if (RC == PPC::F8RCRegisterClass) {
88 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
89 } else if (RC == PPC::F4RCRegisterClass) {
90 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
92 assert(0 && "Unknown regclass!");
97 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
98 MachineBasicBlock::iterator MI,
99 unsigned DestReg, unsigned SrcReg,
100 const TargetRegisterClass *RC) const {
103 if (RC == PPC::GPRCRegisterClass) {
104 BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
105 } else if (RC == PPC::G8RCRegisterClass) {
106 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
107 } else if (RC == PPC::F4RCRegisterClass) {
108 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
109 } else if (RC == PPC::F8RCRegisterClass) {
110 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
111 } else if (RC == PPC::CRRCRegisterClass) {
112 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
113 } else if (RC == PPC::VRRCRegisterClass) {
114 BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
116 std::cerr << "Attempt to copy register that is not GPR or FPR";
121 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
122 /// copy instructions, turning them into load/store instructions.
123 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
125 int FrameIndex) const {
126 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
127 // it takes more than one instruction to store it.
128 unsigned Opc = MI->getOpcode();
130 if ((Opc == PPC::OR4 &&
131 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
132 if (OpNum == 0) { // move -> store
133 unsigned InReg = MI->getOperand(1).getReg();
134 return addFrameReference(BuildMI(PPC::STW,
135 3).addReg(InReg), FrameIndex);
136 } else { // move -> load
137 unsigned OutReg = MI->getOperand(0).getReg();
138 return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
140 } else if ((Opc == PPC::OR8 &&
141 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
142 if (OpNum == 0) { // move -> store
143 unsigned InReg = MI->getOperand(1).getReg();
144 return addFrameReference(BuildMI(PPC::STD,
145 3).addReg(InReg), FrameIndex);
146 } else { // move -> load
147 unsigned OutReg = MI->getOperand(0).getReg();
148 return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex);
150 } else if (Opc == PPC::FMRD) {
151 if (OpNum == 0) { // move -> store
152 unsigned InReg = MI->getOperand(1).getReg();
153 return addFrameReference(BuildMI(PPC::STFD,
154 3).addReg(InReg), FrameIndex);
155 } else { // move -> load
156 unsigned OutReg = MI->getOperand(0).getReg();
157 return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex);
159 } else if (Opc == PPC::FMRS) {
160 if (OpNum == 0) { // move -> store
161 unsigned InReg = MI->getOperand(1).getReg();
162 return addFrameReference(BuildMI(PPC::STFS,
163 3).addReg(InReg), FrameIndex);
164 } else { // move -> load
165 unsigned OutReg = MI->getOperand(0).getReg();
166 return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex);
172 //===----------------------------------------------------------------------===//
173 // Stack Frame Processing methods
174 //===----------------------------------------------------------------------===//
176 // hasFP - Return true if the specified function should have a dedicated frame
177 // pointer register. This is true if the function has variable sized allocas or
178 // if frame pointer elimination is disabled.
180 static bool hasFP(MachineFunction &MF) {
181 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
184 void PPCRegisterInfo::
185 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
186 MachineBasicBlock::iterator I) const {
188 // If we have a frame pointer, convert as follows:
189 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
190 // ADJCALLSTACKUP -> addi, r1, r1, amount
191 MachineInstr *Old = I;
192 unsigned Amount = Old->getOperand(0).getImmedValue();
194 // We need to keep the stack aligned properly. To do this, we round the
195 // amount of space needed for the outgoing arguments up to the next
196 // alignment boundary.
197 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
198 Amount = (Amount+Align-1)/Align*Align;
200 // Replace the pseudo instruction with a new instruction...
201 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
202 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(-Amount);
204 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
205 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(Amount);
213 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
215 MachineInstr &MI = *II;
216 MachineBasicBlock &MBB = *MI.getParent();
217 MachineFunction &MF = *MBB.getParent();
219 while (!MI.getOperand(i).isFrameIndex()) {
221 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
224 int FrameIndex = MI.getOperand(i).getFrameIndex();
226 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
227 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
229 // Take into account whether it's an add or mem instruction
230 unsigned OffIdx = (i == 2) ? 1 : 2;
232 // Now add the frame object offset to the offset from r1.
233 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
234 MI.getOperand(OffIdx).getImmedValue();
236 // If we're not using a Frame Pointer that has been set to the value of the
237 // SP before having the stack size subtracted from it, then add the stack size
238 // to Offset to get the correct offset.
239 Offset += MF.getFrameInfo()->getStackSize();
241 if (Offset > 32767 || Offset < -32768) {
242 // Insert a set of r0 with the full offset value before the ld, st, or add
243 MachineBasicBlock *MBB = MI.getParent();
244 BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16);
245 BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset);
247 // convert into indexed form of the instruction
248 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
249 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
250 assert(ImmToIdxMap.count(MI.getOpcode()) &&
251 "No indexed form of load or store available!");
252 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
253 MI.setOpcode(NewOpcode);
254 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
255 MI.SetMachineOperandReg(2, PPC::R0);
257 switch (MI.getOpcode()) {
262 assert((Offset & 3) == 0 && "Invalid frame offset!");
263 Offset >>= 2; // The actual encoded value has the low two bits zero.
266 MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
271 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
272 // instruction selector. Based on the vector registers that have been used,
273 // transform this into the appropriate ORI instruction.
274 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) {
275 unsigned UsedRegMask = 0;
276 #define HANDLEREG(N) if (UsedRegs[PPC::V##N]) UsedRegMask |= 1 << (31-N)
277 HANDLEREG( 0); HANDLEREG( 1); HANDLEREG( 2); HANDLEREG( 3);
278 HANDLEREG( 4); HANDLEREG( 5); HANDLEREG( 6); HANDLEREG( 7);
279 HANDLEREG( 8); HANDLEREG( 9); HANDLEREG(10); HANDLEREG(11);
280 HANDLEREG(12); HANDLEREG(13); HANDLEREG(14); HANDLEREG(15);
281 HANDLEREG(16); HANDLEREG(17); HANDLEREG(18); HANDLEREG(19);
282 HANDLEREG(20); HANDLEREG(21); HANDLEREG(22); HANDLEREG(23);
283 HANDLEREG(24); HANDLEREG(25); HANDLEREG(26); HANDLEREG(27);
284 HANDLEREG(28); HANDLEREG(29); HANDLEREG(30); HANDLEREG(31);
286 unsigned SrcReg = MI->getOperand(1).getReg();
287 unsigned DstReg = MI->getOperand(0).getReg();
288 // If no registers are used, turn this into a copy.
289 if (UsedRegMask == 0) {
290 if (SrcReg != DstReg)
291 BuildMI(*MI->getParent(), MI, PPC::OR4, 2, DstReg)
292 .addReg(SrcReg).addReg(SrcReg);
293 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
294 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
295 .addReg(SrcReg).addImm(UsedRegMask);
296 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
297 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
298 .addReg(SrcReg).addImm(UsedRegMask >> 16);
300 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
301 .addReg(SrcReg).addImm(UsedRegMask >> 16);
302 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
303 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
306 // Remove the old UPDATE_VRSAVE instruction.
307 MI->getParent()->erase(MI);
311 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
312 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
313 MachineBasicBlock::iterator MBBI = MBB.begin();
314 MachineFrameInfo *MFI = MF.getFrameInfo();
316 // Scan the first few instructions of the prolog, looking for an UPDATE_VRSAVE
317 // instruction. If we find it, process it.
318 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
319 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
320 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
325 // Move MBBI back to the beginning of the function.
328 // Get the number of bytes to allocate from the FrameInfo
329 unsigned NumBytes = MFI->getStackSize();
331 // Get the alignments provided by the target, and the maximum alignment
332 // (if any) of the fixed frame objects.
333 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
334 unsigned MaxAlign = MFI->getMaxAlignment();
336 // If we have calls, we cannot use the red zone to store callee save registers
337 // and we must set up a stack frame, so calculate the necessary size here.
338 if (MFI->hasCalls()) {
339 // We reserve argument space for call sites in the function immediately on
340 // entry to the current function. This eliminates the need for add/sub
341 // brackets around call sites.
342 NumBytes += MFI->getMaxCallFrameSize();
345 // If we are a leaf function, and use up to 224 bytes of stack space,
346 // and don't have a frame pointer, then we do not need to adjust the stack
347 // pointer (we fit in the Red Zone).
348 if ((NumBytes == 0) || (NumBytes <= 224 && !hasFP(MF) && !MFI->hasCalls() &&
349 MaxAlign <= TargetAlign)) {
350 MFI->setStackSize(0);
354 // Add the size of R1 to NumBytes size for the store of R1 to the bottom
355 // of the stack and round the size to a multiple of the alignment.
356 unsigned Align = std::max(TargetAlign, MaxAlign);
357 unsigned GPRSize = 4;
358 unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize;
359 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
361 // Update frame info to pretend that this is part of the stack...
362 MFI->setStackSize(NumBytes);
364 // Adjust stack pointer: r1 -= numbytes.
365 if (NumBytes <= 32768) {
366 BuildMI(MBB, MBBI, PPC::STWU, 3)
367 .addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
369 int NegNumbytes = -NumBytes;
370 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
371 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0)
372 .addReg(PPC::R0).addImm(NegNumbytes & 0xFFFF);
373 BuildMI(MBB, MBBI, PPC::STWUX, 3)
374 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
377 // If there is a preferred stack alignment, align R1 now
378 // FIXME: If this ever matters, this could be made more efficient by folding
379 // this into the code above, so that we don't issue two store+update
381 if (MaxAlign > TargetAlign) {
382 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!");
383 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
384 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
385 BuildMI(MBB, MBBI, PPC::SUBFIC, 2,PPC::R0).addReg(PPC::R0).addImm(MaxAlign);
386 BuildMI(MBB, MBBI, PPC::STWUX, 3)
387 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
390 // If there is a frame pointer, copy R1 (SP) into R31 (FP)
392 BuildMI(MBB, MBBI, PPC::STW, 3)
393 .addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
394 BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
398 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
399 MachineBasicBlock &MBB) const {
400 MachineBasicBlock::iterator MBBI = prior(MBB.end());
401 assert(MBBI->getOpcode() == PPC::BLR &&
402 "Can only insert epilog into returning blocks");
404 // Get the number of bytes allocated from the FrameInfo.
405 unsigned NumBytes = MF.getFrameInfo()->getStackSize();
406 unsigned GPRSize = 4;
409 // If this function has a frame pointer, load the saved stack pointer from
412 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
413 .addSImm(GPRSize).addReg(PPC::R31);
416 // The loaded (or persistent) stack pointer value is offseted by the 'stwu'
417 // on entry to the function. Add this offset back now.
418 if (NumBytes < 32768) {
419 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
420 .addReg(PPC::R1).addSImm(NumBytes);
422 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NumBytes >> 16);
423 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0)
424 .addReg(PPC::R0).addImm(NumBytes & 0xFFFF);
425 BuildMI(MBB, MBBI, PPC::ADD4, 2, PPC::R1)
426 .addReg(PPC::R0).addReg(PPC::R1);
431 #include "PPCGenRegisterInfo.inc"