1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PPCInstrBuilder.h"
17 #include "PPCRegisterInfo.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/ADT/STLExtras.h"
35 PPCRegisterInfo::PPCRegisterInfo()
36 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
37 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
38 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
39 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
40 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
41 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
42 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
43 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
44 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
48 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator MI,
50 unsigned SrcReg, int FrameIdx,
51 const TargetRegisterClass *RC) const {
52 if (SrcReg == PPC::LR) {
53 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
54 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
55 } else if (RC == PPC::CRRCRegisterClass) {
56 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
57 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
58 } else if (RC == PPC::GPRCRegisterClass) {
59 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
60 } else if (RC == PPC::G8RCRegisterClass) {
61 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx);
62 } else if (RC == PPC::F8RCRegisterClass) {
63 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
64 } else if (RC == PPC::F4RCRegisterClass) {
65 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
67 assert(0 && "Unknown regclass!");
73 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
74 MachineBasicBlock::iterator MI,
75 unsigned DestReg, int FrameIdx,
76 const TargetRegisterClass *RC) const {
77 if (DestReg == PPC::LR) {
78 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
79 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
80 } else if (RC == PPC::CRRCRegisterClass) {
81 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
82 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
83 } else if (RC == PPC::GPRCRegisterClass) {
84 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
85 } else if (RC == PPC::G8RCRegisterClass) {
86 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
87 } else if (RC == PPC::F8RCRegisterClass) {
88 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
89 } else if (RC == PPC::F4RCRegisterClass) {
90 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
92 assert(0 && "Unknown regclass!");
97 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
98 MachineBasicBlock::iterator MI,
99 unsigned DestReg, unsigned SrcReg,
100 const TargetRegisterClass *RC) const {
103 if (RC == PPC::GPRCRegisterClass) {
104 BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
105 } else if (RC == PPC::G8RCRegisterClass) {
106 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
107 } else if (RC == PPC::F4RCRegisterClass) {
108 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
109 } else if (RC == PPC::F8RCRegisterClass) {
110 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
111 } else if (RC == PPC::CRRCRegisterClass) {
112 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
114 std::cerr << "Attempt to copy register that is not GPR or FPR";
119 unsigned PPCRegisterInfo::isLoadFromStackSlot(MachineInstr *MI,
120 int &FrameIndex) const {
121 switch (MI->getOpcode()) {
127 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
128 MI->getOperand(2).isFrameIndex()) {
129 FrameIndex = MI->getOperand(2).getFrameIndex();
130 return MI->getOperand(0).getReg();
137 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
138 /// copy instructions, turning them into load/store instructions.
139 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
141 int FrameIndex) const {
142 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
143 // it takes more than one instruction to store it.
144 unsigned Opc = MI->getOpcode();
146 if ((Opc == PPC::OR4 &&
147 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
148 if (OpNum == 0) { // move -> store
149 unsigned InReg = MI->getOperand(1).getReg();
150 return addFrameReference(BuildMI(PPC::STW,
151 3).addReg(InReg), FrameIndex);
152 } else { // move -> load
153 unsigned OutReg = MI->getOperand(0).getReg();
154 return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
156 } else if ((Opc == PPC::OR8 &&
157 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
158 if (OpNum == 0) { // move -> store
159 unsigned InReg = MI->getOperand(1).getReg();
160 return addFrameReference(BuildMI(PPC::STD,
161 3).addReg(InReg), FrameIndex);
162 } else { // move -> load
163 unsigned OutReg = MI->getOperand(0).getReg();
164 return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex);
166 } else if (Opc == PPC::FMRD) {
167 if (OpNum == 0) { // move -> store
168 unsigned InReg = MI->getOperand(1).getReg();
169 return addFrameReference(BuildMI(PPC::STFD,
170 3).addReg(InReg), FrameIndex);
171 } else { // move -> load
172 unsigned OutReg = MI->getOperand(0).getReg();
173 return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex);
175 } else if (Opc == PPC::FMRS) {
176 if (OpNum == 0) { // move -> store
177 unsigned InReg = MI->getOperand(1).getReg();
178 return addFrameReference(BuildMI(PPC::STFS,
179 3).addReg(InReg), FrameIndex);
180 } else { // move -> load
181 unsigned OutReg = MI->getOperand(0).getReg();
182 return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex);
188 //===----------------------------------------------------------------------===//
189 // Stack Frame Processing methods
190 //===----------------------------------------------------------------------===//
192 // hasFP - Return true if the specified function should have a dedicated frame
193 // pointer register. This is true if the function has variable sized allocas or
194 // if frame pointer elimination is disabled.
196 static bool hasFP(MachineFunction &MF) {
197 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
200 void PPCRegisterInfo::
201 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
202 MachineBasicBlock::iterator I) const {
204 // If we have a frame pointer, convert as follows:
205 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
206 // ADJCALLSTACKUP -> addi, r1, r1, amount
207 MachineInstr *Old = I;
208 unsigned Amount = Old->getOperand(0).getImmedValue();
210 // We need to keep the stack aligned properly. To do this, we round the
211 // amount of space needed for the outgoing arguments up to the next
212 // alignment boundary.
213 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
214 Amount = (Amount+Align-1)/Align*Align;
216 // Replace the pseudo instruction with a new instruction...
217 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
218 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
221 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
222 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
231 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
233 MachineInstr &MI = *II;
234 MachineBasicBlock &MBB = *MI.getParent();
235 MachineFunction &MF = *MBB.getParent();
237 while (!MI.getOperand(i).isFrameIndex()) {
239 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
242 int FrameIndex = MI.getOperand(i).getFrameIndex();
244 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
245 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
247 // Take into account whether it's an add or mem instruction
248 unsigned OffIdx = (i == 2) ? 1 : 2;
250 // Now add the frame object offset to the offset from r1.
251 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
252 MI.getOperand(OffIdx).getImmedValue();
254 // If we're not using a Frame Pointer that has been set to the value of the
255 // SP before having the stack size subtracted from it, then add the stack size
256 // to Offset to get the correct offset.
257 Offset += MF.getFrameInfo()->getStackSize();
259 if (Offset > 32767 || Offset < -32768) {
260 // Insert a set of r0 with the full offset value before the ld, st, or add
261 MachineBasicBlock *MBB = MI.getParent();
262 MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16));
263 MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
265 // convert into indexed form of the instruction
266 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
267 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
268 assert(ImmToIdxMap.count(MI.getOpcode()) &&
269 "No indexed form of load or store available!");
270 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
271 MI.setOpcode(NewOpcode);
272 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
273 MI.SetMachineOperandReg(2, PPC::R0);
275 switch (MI.getOpcode()) {
280 assert((Offset & 3) == 0 && "Invalid frame offset!");
281 Offset >>= 2; // The actual encoded value has the low two bits zero.
284 MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
290 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
291 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
292 MachineBasicBlock::iterator MBBI = MBB.begin();
293 MachineFrameInfo *MFI = MF.getFrameInfo();
296 // Get the number of bytes to allocate from the FrameInfo
297 unsigned NumBytes = MFI->getStackSize();
299 // Get the alignments provided by the target, and the maximum alignment
300 // (if any) of the fixed frame objects.
301 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
302 unsigned MaxAlign = MFI->getMaxAlignment();
304 // If we have calls, we cannot use the red zone to store callee save registers
305 // and we must set up a stack frame, so calculate the necessary size here.
306 if (MFI->hasCalls()) {
307 // We reserve argument space for call sites in the function immediately on
308 // entry to the current function. This eliminates the need for add/sub
309 // brackets around call sites.
310 NumBytes += MFI->getMaxCallFrameSize();
313 // If we are a leaf function, and use up to 224 bytes of stack space,
314 // and don't have a frame pointer, then we do not need to adjust the stack
315 // pointer (we fit in the Red Zone).
316 if ((NumBytes == 0) || (NumBytes <= 224 && !hasFP(MF) && !MFI->hasCalls() &&
317 MaxAlign <= TargetAlign)) {
318 MFI->setStackSize(0);
322 // Add the size of R1 to NumBytes size for the store of R1 to the bottom
323 // of the stack and round the size to a multiple of the alignment.
324 unsigned Align = std::max(TargetAlign, MaxAlign);
325 unsigned GPRSize = 4;
326 unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize;
327 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
329 // Update frame info to pretend that this is part of the stack...
330 MFI->setStackSize(NumBytes);
332 // Adjust stack pointer: r1 -= numbytes.
333 if (NumBytes <= 32768) {
334 MI=BuildMI(PPC::STWU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
335 MBB.insert(MBBI, MI);
337 int NegNumbytes = -NumBytes;
338 MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
339 MBB.insert(MBBI, MI);
340 MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
341 .addImm(NegNumbytes & 0xFFFF);
342 MBB.insert(MBBI, MI);
343 MI = BuildMI(PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
344 MBB.insert(MBBI, MI);
347 // If there is a preferred stack alignment, align R1 now
348 // FIXME: If this ever matters, this could be made more efficient by folding
349 // this into the code above, so that we don't issue two store+update
351 if (MaxAlign > TargetAlign) {
352 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!");
353 MI = BuildMI(PPC::RLWINM, 4, PPC::R0).addReg(PPC::R1).addImm(0)
354 .addImm(32-Log2_32(MaxAlign)).addImm(31);
355 MBB.insert(MBBI, MI);
356 MI = BuildMI(PPC::SUBFIC, 2, PPC::R0).addReg(PPC::R0).addImm(MaxAlign);
357 MBB.insert(MBBI, MI);
358 MI = BuildMI(PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
359 MBB.insert(MBBI, MI);
362 // If there is a frame pointer, copy R1 (SP) into R31 (FP)
364 MI = BuildMI(PPC::STW, 3).addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
365 MBB.insert(MBBI, MI);
366 MI = BuildMI(PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
367 MBB.insert(MBBI, MI);
371 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
372 MachineBasicBlock &MBB) const {
373 const MachineFrameInfo *MFI = MF.getFrameInfo();
374 MachineBasicBlock::iterator MBBI = prior(MBB.end());
376 assert(MBBI->getOpcode() == PPC::BLR &&
377 "Can only insert epilog into returning blocks");
379 // Get the number of bytes allocated from the FrameInfo...
380 unsigned NumBytes = MFI->getStackSize();
381 unsigned GPRSize = 4;
385 MI = BuildMI(PPC::LWZ, 2, PPC::R31).addSImm(GPRSize).addReg(PPC::R31);
386 MBB.insert(MBBI, MI);
388 MI = BuildMI(PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
389 MBB.insert(MBBI, MI);
393 #include "PPCGenRegisterInfo.inc"