1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PPCInstrBuilder.h"
17 #include "PPCRegisterInfo.h"
18 #include "PPCSubtarget.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Type.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineDebugInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineLocation.h"
27 #include "llvm/CodeGen/SelectionDAGNodes.h"
28 #include "llvm/Target/TargetFrameInfo.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/ADT/STLExtras.h"
40 /// getRegisterNumbering - Given the enum value for some register, e.g.
41 /// PPC::F14, return the number that it corresponds to (e.g. 14).
42 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
45 case R0 : case X0 : case F0 : case V0 : case CR0: return 0;
46 case R1 : case X1 : case F1 : case V1 : case CR1: return 1;
47 case R2 : case X2 : case F2 : case V2 : case CR2: return 2;
48 case R3 : case X3 : case F3 : case V3 : case CR3: return 3;
49 case R4 : case X4 : case F4 : case V4 : case CR4: return 4;
50 case R5 : case X5 : case F5 : case V5 : case CR5: return 5;
51 case R6 : case X6 : case F6 : case V6 : case CR6: return 6;
52 case R7 : case X7 : case F7 : case V7 : case CR7: return 7;
53 case R8 : case X8 : case F8 : case V8 : return 8;
54 case R9 : case X9 : case F9 : case V9 : return 9;
55 case R10: case X10: case F10: case V10: return 10;
56 case R11: case X11: case F11: case V11: return 11;
57 case R12: case X12: case F12: case V12: return 12;
58 case R13: case X13: case F13: case V13: return 13;
59 case R14: case X14: case F14: case V14: return 14;
60 case R15: case X15: case F15: case V15: return 15;
61 case R16: case X16: case F16: case V16: return 16;
62 case R17: case X17: case F17: case V17: return 17;
63 case R18: case X18: case F18: case V18: return 18;
64 case R19: case X19: case F19: case V19: return 19;
65 case R20: case X20: case F20: case V20: return 20;
66 case R21: case X21: case F21: case V21: return 21;
67 case R22: case X22: case F22: case V22: return 22;
68 case R23: case X23: case F23: case V23: return 23;
69 case R24: case X24: case F24: case V24: return 24;
70 case R25: case X25: case F25: case V25: return 25;
71 case R26: case X26: case F26: case V26: return 26;
72 case R27: case X27: case F27: case V27: return 27;
73 case R28: case X28: case F28: case V28: return 28;
74 case R29: case X29: case F29: case V29: return 29;
75 case R30: case X30: case F30: case V30: return 30;
76 case R31: case X31: case F31: case V31: return 31;
78 std::cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
83 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
84 const TargetInstrInfo &tii)
85 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
86 Subtarget(ST), TII(tii) {
87 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
88 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
89 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
90 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
91 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
92 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
93 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
94 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
98 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
99 MachineBasicBlock::iterator MI,
100 unsigned SrcReg, int FrameIdx,
101 const TargetRegisterClass *RC) const {
102 if (RC == PPC::GPRCRegisterClass) {
103 if (SrcReg != PPC::LR) {
104 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
106 // FIXME: this spills LR immediately to memory in one step. To do this,
107 // we use R11, which we know cannot be used in the prolog/epilog. This is
109 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
110 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11),
113 } else if (RC == PPC::G8RCRegisterClass) {
114 if (SrcReg != PPC::LR8) {
115 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg), FrameIdx);
117 // FIXME: this spills LR immediately to memory in one step. To do this,
118 // we use R11, which we know cannot be used in the prolog/epilog. This is
120 BuildMI(MBB, MI, PPC::MFLR8, 1, PPC::X11);
121 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(PPC::X11),
124 } else if (RC == PPC::F8RCRegisterClass) {
125 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
126 } else if (RC == PPC::F4RCRegisterClass) {
127 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
128 } else if (RC == PPC::CRRCRegisterClass) {
129 // FIXME: We use R0 here, because it isn't available for RA.
130 // We need to store the CR in the low 4-bits of the saved value. First,
131 // issue a MFCR to save all of the CRBits.
132 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0);
134 // If the saved register wasn't CR0, shift the bits left so that they are in
136 if (SrcReg != PPC::CR0) {
137 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
138 // rlwinm r0, r0, ShiftBits, 0, 31.
139 BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0)
140 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31);
143 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx);
144 } else if (RC == PPC::VRRCRegisterClass) {
145 // We don't have indexed addressing for vector loads. Emit:
147 // Dest = LVX R0, R11
149 // FIXME: We use R0 here, because it isn't available for RA.
150 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
151 BuildMI(MBB, MI, PPC::STVX, 3)
152 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
154 assert(0 && "Unknown regclass!");
160 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
161 MachineBasicBlock::iterator MI,
162 unsigned DestReg, int FrameIdx,
163 const TargetRegisterClass *RC) const {
164 if (RC == PPC::GPRCRegisterClass) {
165 if (DestReg != PPC::LR) {
166 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
168 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
169 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
171 } else if (RC == PPC::G8RCRegisterClass) {
172 if (DestReg != PPC::LR8) {
173 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
175 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, PPC::R11), FrameIdx);
176 BuildMI(MBB, MI, PPC::MTLR8, 1).addReg(PPC::R11);
178 } else if (RC == PPC::F8RCRegisterClass) {
179 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
180 } else if (RC == PPC::F4RCRegisterClass) {
181 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
182 } else if (RC == PPC::CRRCRegisterClass) {
183 // FIXME: We use R0 here, because it isn't available for RA.
184 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx);
186 // If the reloaded register isn't CR0, shift the bits right so that they are
187 // in the right CR's slot.
188 if (DestReg != PPC::CR0) {
189 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
190 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
191 BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0)
192 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31);
195 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0);
196 } else if (RC == PPC::VRRCRegisterClass) {
197 // We don't have indexed addressing for vector loads. Emit:
199 // Dest = LVX R0, R11
201 // FIXME: We use R0 here, because it isn't available for RA.
202 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
203 BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
205 assert(0 && "Unknown regclass!");
210 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
211 MachineBasicBlock::iterator MI,
212 unsigned DestReg, unsigned SrcReg,
213 const TargetRegisterClass *RC) const {
214 if (RC == PPC::GPRCRegisterClass) {
215 BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
216 } else if (RC == PPC::G8RCRegisterClass) {
217 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
218 } else if (RC == PPC::F4RCRegisterClass) {
219 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
220 } else if (RC == PPC::F8RCRegisterClass) {
221 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
222 } else if (RC == PPC::CRRCRegisterClass) {
223 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
224 } else if (RC == PPC::VRRCRegisterClass) {
225 BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
227 std::cerr << "Attempt to copy register that is not GPR or FPR";
232 const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
233 // 32-bit Darwin calling convention.
234 static const unsigned Darwin32_CalleeSaveRegs[] = {
235 PPC::R1 , PPC::R13, PPC::R14, PPC::R15,
236 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
237 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
238 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
239 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
241 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
242 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
243 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
244 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
247 PPC::CR2, PPC::CR3, PPC::CR4,
248 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
249 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
250 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
254 // 64-bit Darwin calling convention.
255 static const unsigned Darwin64_CalleeSaveRegs[] = {
256 PPC::X1 , PPC::X13, PPC::X14, PPC::X15,
257 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
258 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
259 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
260 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
262 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
263 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
264 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
265 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
268 PPC::CR2, PPC::CR3, PPC::CR4,
269 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
270 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
271 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
276 return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegs :
277 Darwin32_CalleeSaveRegs;
280 const TargetRegisterClass* const*
281 PPCRegisterInfo::getCalleeSaveRegClasses() const {
282 // 32-bit Darwin calling convention.
283 static const TargetRegisterClass * const Darwin32_CalleeSaveRegClasses[] = {
284 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
285 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
286 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
287 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
288 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
290 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
291 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
292 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
293 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
294 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
296 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
298 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
299 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
300 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
302 &PPC::GPRCRegClass, 0
305 // 64-bit Darwin calling convention.
306 static const TargetRegisterClass * const Darwin64_CalleeSaveRegClasses[] = {
307 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
308 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
309 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
310 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
311 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
313 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
314 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
315 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
316 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
317 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
319 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
321 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
322 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
323 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
325 &PPC::G8RCRegClass, 0
328 return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegClasses :
329 Darwin32_CalleeSaveRegClasses;
332 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
333 /// copy instructions, turning them into load/store instructions.
334 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
336 int FrameIndex) const {
337 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
338 // it takes more than one instruction to store it.
339 unsigned Opc = MI->getOpcode();
341 if ((Opc == PPC::OR &&
342 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
343 if (OpNum == 0) { // move -> store
344 unsigned InReg = MI->getOperand(1).getReg();
345 return addFrameReference(BuildMI(TII, PPC::STW,
346 3).addReg(InReg), FrameIndex);
347 } else { // move -> load
348 unsigned OutReg = MI->getOperand(0).getReg();
349 return addFrameReference(BuildMI(TII, PPC::LWZ, 2, OutReg), FrameIndex);
351 } else if ((Opc == PPC::OR8 &&
352 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
353 if (OpNum == 0) { // move -> store
354 unsigned InReg = MI->getOperand(1).getReg();
355 return addFrameReference(BuildMI(TII, PPC::STD,
356 3).addReg(InReg), FrameIndex);
357 } else { // move -> load
358 unsigned OutReg = MI->getOperand(0).getReg();
359 return addFrameReference(BuildMI(TII, PPC::LD, 2, OutReg), FrameIndex);
361 } else if (Opc == PPC::FMRD) {
362 if (OpNum == 0) { // move -> store
363 unsigned InReg = MI->getOperand(1).getReg();
364 return addFrameReference(BuildMI(TII, PPC::STFD,
365 3).addReg(InReg), FrameIndex);
366 } else { // move -> load
367 unsigned OutReg = MI->getOperand(0).getReg();
368 return addFrameReference(BuildMI(TII, PPC::LFD, 2, OutReg), FrameIndex);
370 } else if (Opc == PPC::FMRS) {
371 if (OpNum == 0) { // move -> store
372 unsigned InReg = MI->getOperand(1).getReg();
373 return addFrameReference(BuildMI(TII, PPC::STFS,
374 3).addReg(InReg), FrameIndex);
375 } else { // move -> load
376 unsigned OutReg = MI->getOperand(0).getReg();
377 return addFrameReference(BuildMI(TII, PPC::LFS, 2, OutReg), FrameIndex);
383 //===----------------------------------------------------------------------===//
384 // Stack Frame Processing methods
385 //===----------------------------------------------------------------------===//
387 // hasFP - Return true if the specified function should have a dedicated frame
388 // pointer register. This is true if the function has variable sized allocas or
389 // if frame pointer elimination is disabled.
391 static bool hasFP(const MachineFunction &MF) {
392 const MachineFrameInfo *MFI = MF.getFrameInfo();
394 // If frame pointers are forced, or if there are variable sized stack objects,
395 // use a frame pointer.
397 return NoFramePointerElim || MFI->hasVarSizedObjects();
400 void PPCRegisterInfo::
401 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
402 MachineBasicBlock::iterator I) const {
404 // If we have a frame pointer, convert as follows:
405 // ADJCALLSTACKDOWN -> lwz r0, 0(r31)
406 // stwu, r0, -amount(r1)
407 // ADJCALLSTACKUP -> addi, r1, r1, amount
408 MachineInstr *Old = I;
409 unsigned Amount = Old->getOperand(0).getImmedValue();
411 // We need to keep the stack aligned properly. To do this, we round the
412 // amount of space needed for the outgoing arguments up to the next
413 // alignment boundary.
414 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
415 Amount = (Amount+Align-1)/Align*Align;
417 // Replace the pseudo instruction with a new instruction...
418 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
419 if (!Subtarget.isPPC64()) {
420 BuildMI(MBB, I, PPC::LWZ, 2, PPC::R0).addImm(0).addReg(PPC::R31);
421 BuildMI(MBB, I, PPC::STWU, 3)
422 .addReg(PPC::R0).addImm(-Amount).addReg(PPC::R1);
424 BuildMI(MBB, I, PPC::LD, 2, PPC::X0).addImm(0).addReg(PPC::X31);
425 BuildMI(MBB, I, PPC::STDU, 3)
426 .addReg(PPC::X0).addImm(-Amount/4).addReg(PPC::X1);
429 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
430 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(Amount);
438 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
440 MachineInstr &MI = *II;
441 MachineBasicBlock &MBB = *MI.getParent();
442 MachineFunction &MF = *MBB.getParent();
444 while (!MI.getOperand(i).isFrameIndex()) {
446 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
449 int FrameIndex = MI.getOperand(i).getFrameIndex();
451 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
452 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false);
454 // Take into account whether it's an add or mem instruction
455 unsigned OffIdx = (i == 2) ? 1 : 2;
457 // Figure out if the offset in the instruction is shifted right two bits. This
458 // is true for instructions like "STD", which the machine implicitly adds two
460 bool isIXAddr = false;
461 switch (MI.getOpcode()) {
471 // Now add the frame object offset to the offset from r1.
472 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
475 Offset += MI.getOperand(OffIdx).getImmedValue();
477 Offset += MI.getOperand(OffIdx).getImmedValue() << 2;
479 // If we're not using a Frame Pointer that has been set to the value of the
480 // SP before having the stack size subtracted from it, then add the stack size
481 // to Offset to get the correct offset.
482 Offset += MF.getFrameInfo()->getStackSize();
484 if (Offset > 32767 || Offset < -32768) {
485 // Insert a set of r0 with the full offset value before the ld, st, or add
486 MachineBasicBlock *MBB = MI.getParent();
487 BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addImm(Offset >> 16);
488 BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset);
490 // convert into indexed form of the instruction
491 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
492 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
493 assert(ImmToIdxMap.count(MI.getOpcode()) &&
494 "No indexed form of load or store available!");
495 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
496 MI.setOpcode(NewOpcode);
497 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false);
498 MI.getOperand(2).ChangeToRegister(PPC::R0, false);
501 assert((Offset & 3) == 0 && "Invalid frame offset!");
502 Offset >>= 2; // The actual encoded value has the low two bits zero.
504 MI.getOperand(OffIdx).ChangeToImmediate(Offset);
508 /// VRRegNo - Map from a numbered VR register to its enum value.
510 static const unsigned short VRRegNo[] = {
511 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
512 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
513 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
514 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
517 /// RemoveVRSaveCode - We have found that this function does not need any code
518 /// to manipulate the VRSAVE register, even though it uses vector registers.
519 /// This can happen when the only registers used are known to be live in or out
520 /// of the function. Remove all of the VRSAVE related code from the function.
521 static void RemoveVRSaveCode(MachineInstr *MI) {
522 MachineBasicBlock *Entry = MI->getParent();
523 MachineFunction *MF = Entry->getParent();
525 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
526 MachineBasicBlock::iterator MBBI = MI;
528 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
529 MBBI->eraseFromParent();
531 bool RemovedAllMTVRSAVEs = true;
532 // See if we can find and remove the MTVRSAVE instruction from all of the
534 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
535 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
536 // If last instruction is a return instruction, add an epilogue
537 if (!I->empty() && TII.isReturn(I->back().getOpcode())) {
538 bool FoundIt = false;
539 for (MBBI = I->end(); MBBI != I->begin(); ) {
541 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
542 MBBI->eraseFromParent(); // remove it.
547 RemovedAllMTVRSAVEs &= FoundIt;
551 // If we found and removed all MTVRSAVE instructions, remove the read of
553 if (RemovedAllMTVRSAVEs) {
555 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
557 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
558 MBBI->eraseFromParent();
561 // Finally, nuke the UPDATE_VRSAVE.
562 MI->eraseFromParent();
565 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
566 // instruction selector. Based on the vector registers that have been used,
567 // transform this into the appropriate ORI instruction.
568 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) {
569 unsigned UsedRegMask = 0;
570 for (unsigned i = 0; i != 32; ++i)
571 if (UsedRegs[VRRegNo[i]])
572 UsedRegMask |= 1 << (31-i);
574 // Live in and live out values already must be in the mask, so don't bother
576 MachineFunction *MF = MI->getParent()->getParent();
577 for (MachineFunction::livein_iterator I =
578 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) {
579 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
580 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
581 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
583 for (MachineFunction::liveout_iterator I =
584 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) {
585 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
586 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
587 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
590 unsigned SrcReg = MI->getOperand(1).getReg();
591 unsigned DstReg = MI->getOperand(0).getReg();
592 // If no registers are used, turn this into a copy.
593 if (UsedRegMask == 0) {
594 // Remove all VRSAVE code.
595 RemoveVRSaveCode(MI);
597 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
598 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
599 .addReg(SrcReg).addImm(UsedRegMask);
600 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
601 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
602 .addReg(SrcReg).addImm(UsedRegMask >> 16);
604 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
605 .addReg(SrcReg).addImm(UsedRegMask >> 16);
606 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
607 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
610 // Remove the old UPDATE_VRSAVE instruction.
611 MI->eraseFromParent();
615 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
616 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
617 MachineBasicBlock::iterator MBBI = MBB.begin();
618 MachineFrameInfo *MFI = MF.getFrameInfo();
619 MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo();
621 // Do we have a frame pointer for this function?
622 bool HasFP = hasFP(MF);
624 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
626 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
627 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
628 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
633 // Move MBBI back to the beginning of the function.
636 // Get the number of bytes to allocate from the FrameInfo
637 unsigned NumBytes = MFI->getStackSize();
639 // Get the alignments provided by the target, and the maximum alignment
640 // (if any) of the fixed frame objects.
641 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
642 unsigned MaxAlign = MFI->getMaxAlignment();
644 // If we have calls, we cannot use the red zone to store callee save registers
645 // and we must set up a stack frame, so calculate the necessary size here.
646 if (MFI->hasCalls()) {
647 // We reserve argument space for call sites in the function immediately on
648 // entry to the current function. This eliminates the need for add/sub
649 // brackets around call sites.
650 NumBytes += MFI->getMaxCallFrameSize();
653 // If we are a leaf function, and use up to 224 bytes of stack space,
654 // and don't have a frame pointer, then we do not need to adjust the stack
655 // pointer (we fit in the Red Zone).
656 if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() &&
657 MaxAlign <= TargetAlign)) {
658 MFI->setStackSize(0);
662 // Add the size of R1 to NumBytes size for the store of R1 to the bottom
663 // of the stack and round the size to a multiple of the alignment.
664 unsigned Align = std::max(TargetAlign, MaxAlign);
665 unsigned GPRSize = Subtarget.isPPC64() ? 8 : 4;
666 unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize;
667 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
669 // Update frame info to pretend that this is part of the stack...
670 MFI->setStackSize(NumBytes);
671 int NegNumbytes = -NumBytes;
673 // Adjust stack pointer: r1 -= numbytes.
674 // If there is a preferred stack alignment, align R1 now
675 if (!Subtarget.isPPC64()) {
677 if (MaxAlign > TargetAlign) {
678 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767&&"Invalid alignment!");
679 assert(isInt16(0-NumBytes) && "Unhandled stack size and alignment!");
680 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
681 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
682 BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
684 BuildMI(MBB, MBBI, PPC::STWUX, 3)
685 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
686 } else if (NumBytes <= 32768) {
687 BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addImm(NegNumbytes)
690 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegNumbytes >> 16);
691 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
692 .addImm(NegNumbytes & 0xFFFF);
693 BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
697 if (MaxAlign > TargetAlign) {
698 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767&&"Invalid alignment!");
699 assert(isInt16(0-NumBytes) && "Unhandled stack size and alignment!");
700 BuildMI(MBB, MBBI, PPC::RLDICL, 3, PPC::X0)
701 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign));
702 BuildMI(MBB, MBBI, PPC::SUBFIC8, 2, PPC::X0).addReg(PPC::X0)
704 BuildMI(MBB, MBBI, PPC::STDUX, 3)
705 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0);
706 } else if (NumBytes <= 32768*4) {
707 BuildMI(MBB, MBBI, PPC::STDU, 3).addReg(PPC::X1).addImm(NegNumbytes/4)
710 BuildMI(MBB, MBBI, PPC::LIS8, 1, PPC::X0).addImm(NegNumbytes >> 16);
711 BuildMI(MBB, MBBI, PPC::ORI8, 2, PPC::X0).addReg(PPC::X0)
712 .addImm(NegNumbytes & 0xFFFF);
713 BuildMI(MBB, MBBI, PPC::STDUX, 3).addReg(PPC::X1).addReg(PPC::X1)
718 if (DebugInfo && DebugInfo->hasInfo()) {
719 std::vector<MachineMove *> &Moves = DebugInfo->getFrameMoves();
720 unsigned LabelID = DebugInfo->NextLabelID();
722 // Mark effective beginning of when frame pointer becomes valid.
723 BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addImm(LabelID);
725 // Show update of SP.
726 MachineLocation SPDst(MachineLocation::VirtualFP);
727 MachineLocation SPSrc(MachineLocation::VirtualFP, NegNumbytes);
728 Moves.push_back(new MachineMove(LabelID, SPDst, SPSrc));
730 // Add callee saved registers to move list.
731 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
732 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
733 MachineLocation CSDst(MachineLocation::VirtualFP,
734 MFI->getObjectOffset(CSI[I].getFrameIdx()));
735 MachineLocation CSSrc(CSI[I].getReg());
736 Moves.push_back(new MachineMove(LabelID, CSDst, CSSrc));
740 // If there is a frame pointer, copy R1 (SP) into R31 (FP)
742 if (!Subtarget.isPPC64()) {
743 BuildMI(MBB, MBBI, PPC::STW, 3)
744 .addReg(PPC::R31).addImm(GPRSize).addReg(PPC::R1);
745 BuildMI(MBB, MBBI, PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
747 BuildMI(MBB, MBBI, PPC::STD, 3)
748 .addReg(PPC::X31).addImm(GPRSize/4).addReg(PPC::X1);
749 BuildMI(MBB, MBBI, PPC::OR8, 2, PPC::X31).addReg(PPC::X1).addReg(PPC::X1);
754 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
755 MachineBasicBlock &MBB) const {
756 MachineBasicBlock::iterator MBBI = prior(MBB.end());
757 assert(MBBI->getOpcode() == PPC::BLR &&
758 "Can only insert epilog into returning blocks");
760 // Get alignment info so we know how to restore r1
761 const MachineFrameInfo *MFI = MF.getFrameInfo();
762 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
764 // Get the number of bytes allocated from the FrameInfo.
765 unsigned NumBytes = MFI->getStackSize();
766 unsigned GPRSize = 4;
769 // If this function has a frame pointer, load the saved stack pointer from
772 if (!Subtarget.isPPC64()) {
773 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
774 .addImm(GPRSize).addReg(PPC::R31);
776 BuildMI(MBB, MBBI, PPC::LD, 2, PPC::X31)
777 .addImm(GPRSize/4).addReg(PPC::X31);
781 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
782 // on entry to the function. Add this offset back now.
783 if (!Subtarget.isPPC64()) {
784 if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) {
785 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
786 .addReg(PPC::R1).addImm(NumBytes);
788 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addImm(0).addReg(PPC::R1);
791 if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) {
792 BuildMI(MBB, MBBI, PPC::ADDI8, 2, PPC::X1)
793 .addReg(PPC::X1).addImm(NumBytes);
795 BuildMI(MBB, MBBI, PPC::LD, 2, PPC::X1).addImm(0).addReg(PPC::X1);
801 unsigned PPCRegisterInfo::getRARegister() const {
802 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
806 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
807 if (!Subtarget.isPPC64())
808 return hasFP(MF) ? PPC::R31 : PPC::R1;
810 return hasFP(MF) ? PPC::X31 : PPC::X1;
813 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves)
815 // Initial state of the frame pointer is R1.
816 MachineLocation Dst(MachineLocation::VirtualFP);
817 MachineLocation Src(PPC::R1, 0);
818 Moves.push_back(new MachineMove(0, Dst, Src));
821 #include "PPCGenRegisterInfo.inc"