1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "reginfo"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCRegisterInfo.h"
20 #include "PPCFrameInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/Function.h"
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/ValueTypes.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineLocation.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/RegisterScavenging.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/MathExtras.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/STLExtras.h"
47 // FIXME This disables some code that aligns the stack to a boundary
48 // bigger than the default (16 bytes on Darwin) when there is a stack local
49 // of greater alignment. This does not currently work, because the delta
50 // between old and new stack pointers is added to offsets that reference
51 // incoming parameters after the prolog is generated, and the code that
52 // does that doesn't handle a variable delta. You don't want to do that
53 // anyway; a better approach is to reserve another register that retains
54 // to the incoming stack pointer, and reference parameters relative to that.
57 // FIXME (64-bit): Eventually enable by default.
59 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger",
61 cl::desc("Enable PPC32 register scavenger"),
63 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger",
65 cl::desc("Enable PPC64 register scavenger"),
71 #define EnableRegisterScavenging \
72 ((EnablePPC32RS && !Subtarget.isPPC64()) || \
73 (EnablePPC64RS && Subtarget.isPPC64()))
75 // FIXME (64-bit): Should be inlined.
77 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
78 return EnableRegisterScavenging;
81 /// getRegisterNumbering - Given the enum value for some register, e.g.
82 /// PPC::F14, return the number that it corresponds to (e.g. 14).
83 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
87 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0;
88 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1;
89 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2;
90 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3;
91 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4;
92 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5;
93 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6;
94 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7;
95 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8;
96 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9;
97 case R10: case X10: case F10: case V10: case CR2EQ: return 10;
98 case R11: case X11: case F11: case V11: case CR2UN: return 11;
99 case R12: case X12: case F12: case V12: case CR3LT: return 12;
100 case R13: case X13: case F13: case V13: case CR3GT: return 13;
101 case R14: case X14: case F14: case V14: case CR3EQ: return 14;
102 case R15: case X15: case F15: case V15: case CR3UN: return 15;
103 case R16: case X16: case F16: case V16: case CR4LT: return 16;
104 case R17: case X17: case F17: case V17: case CR4GT: return 17;
105 case R18: case X18: case F18: case V18: case CR4EQ: return 18;
106 case R19: case X19: case F19: case V19: case CR4UN: return 19;
107 case R20: case X20: case F20: case V20: case CR5LT: return 20;
108 case R21: case X21: case F21: case V21: case CR5GT: return 21;
109 case R22: case X22: case F22: case V22: case CR5EQ: return 22;
110 case R23: case X23: case F23: case V23: case CR5UN: return 23;
111 case R24: case X24: case F24: case V24: case CR6LT: return 24;
112 case R25: case X25: case F25: case V25: case CR6GT: return 25;
113 case R26: case X26: case F26: case V26: case CR6EQ: return 26;
114 case R27: case X27: case F27: case V27: case CR6UN: return 27;
115 case R28: case X28: case F28: case V28: case CR7LT: return 28;
116 case R29: case X29: case F29: case V29: case CR7GT: return 29;
117 case R30: case X30: case F30: case V30: case CR7EQ: return 30;
118 case R31: case X31: case F31: case V31: case CR7UN: return 31;
120 llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!");
124 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
125 const TargetInstrInfo &tii)
126 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
127 Subtarget(ST), TII(tii) {
128 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
129 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
130 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
131 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
132 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
133 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
134 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
135 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
138 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
139 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
140 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
141 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
142 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
145 /// getPointerRegClass - Return the register class to use to hold pointers.
146 /// This is used for addressing modes.
147 const TargetRegisterClass *
148 PPCRegisterInfo::getPointerRegClass(unsigned Kind) const {
149 if (Subtarget.isPPC64())
150 return &PPC::G8RCRegClass;
151 return &PPC::GPRCRegClass;
155 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
156 // 32-bit Darwin calling convention.
157 static const unsigned Darwin32_CalleeSavedRegs[] = {
158 PPC::R13, PPC::R14, PPC::R15,
159 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
160 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
161 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
162 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
164 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
165 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
166 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
167 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
170 PPC::CR2, PPC::CR3, PPC::CR4,
171 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
172 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
173 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
175 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
176 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
177 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
182 // 32-bit SVR4 calling convention.
183 static const unsigned SVR4_CalleeSavedRegs[] = {
185 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
186 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
187 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
188 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
190 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
191 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
192 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
193 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
196 PPC::CR2, PPC::CR3, PPC::CR4,
200 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
201 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
202 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
204 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
205 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
206 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
210 // 64-bit Darwin calling convention.
211 static const unsigned Darwin64_CalleeSavedRegs[] = {
213 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
214 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
215 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
216 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
218 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
219 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
220 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
221 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
224 PPC::CR2, PPC::CR3, PPC::CR4,
225 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
226 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
227 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
229 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
230 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
231 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
236 // 64-bit SVR4 calling convention.
237 static const unsigned SVR4_64_CalleeSavedRegs[] = {
239 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
240 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
241 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
242 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
244 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
245 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
246 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
247 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
250 PPC::CR2, PPC::CR3, PPC::CR4,
254 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
255 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
256 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
258 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
259 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
260 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
265 if (Subtarget.isDarwinABI())
266 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
267 Darwin32_CalleeSavedRegs;
269 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs;
272 // needsFP - Return true if the specified function should have a dedicated frame
273 // pointer register. This is true if the function has variable sized allocas or
274 // if frame pointer elimination is disabled.
276 static bool needsFP(const MachineFunction &MF) {
277 const MachineFrameInfo *MFI = MF.getFrameInfo();
278 // Naked functions have no stack frame pushed, so we don't have a frame pointer.
279 if (MF.getFunction()->hasFnAttr(Attribute::Naked))
281 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects() ||
282 (GuaranteedTailCallOpt && MF.getInfo<PPCFunctionInfo>()->hasFastCall());
285 static bool spillsCR(const MachineFunction &MF) {
286 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
287 return FuncInfo->isCRSpilled();
290 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
291 BitVector Reserved(getNumRegs());
292 Reserved.set(PPC::R0);
293 Reserved.set(PPC::R1);
294 Reserved.set(PPC::LR);
295 Reserved.set(PPC::LR8);
296 Reserved.set(PPC::RM);
298 // The SVR4 ABI reserves r2 and r13
299 if (Subtarget.isSVR4ABI()) {
300 Reserved.set(PPC::R2); // System-reserved register
301 Reserved.set(PPC::R13); // Small Data Area pointer register
303 // Reserve R2 on Darwin to hack around the problem of save/restore of CR
304 // when the stack frame is too big to address directly; we need two regs.
306 if (Subtarget.isDarwinABI()) {
307 Reserved.set(PPC::R2);
310 // On PPC64, r13 is the thread pointer. Never allocate this register.
311 // Note that this is over conservative, as it also prevents allocation of R31
312 // when the FP is not needed.
313 if (Subtarget.isPPC64()) {
314 Reserved.set(PPC::R13);
315 Reserved.set(PPC::R31);
317 if (!EnableRegisterScavenging)
318 Reserved.set(PPC::R0); // FIXME (64-bit): Remove
320 Reserved.set(PPC::X0);
321 Reserved.set(PPC::X1);
322 Reserved.set(PPC::X13);
323 Reserved.set(PPC::X31);
325 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
326 if (Subtarget.isSVR4ABI()) {
327 Reserved.set(PPC::X2);
329 // Reserve R2 on Darwin to hack around the problem of save/restore of CR
330 // when the stack frame is too big to address directly; we need two regs.
332 if (Subtarget.isDarwinABI()) {
333 Reserved.set(PPC::X2);
338 Reserved.set(PPC::R31);
343 //===----------------------------------------------------------------------===//
344 // Stack Frame Processing methods
345 //===----------------------------------------------------------------------===//
347 // hasFP - Return true if the specified function actually has a dedicated frame
348 // pointer register. This is true if the function needs a frame pointer and has
349 // a non-zero stack size.
350 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
351 const MachineFrameInfo *MFI = MF.getFrameInfo();
352 return MFI->getStackSize() && needsFP(MF);
355 /// MustSaveLR - Return true if this function requires that we save the LR
356 /// register onto the stack in the prolog and restore it in the epilog of the
358 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
359 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
361 // We need a save/restore of LR if there is any def of LR (which is
362 // defined by calls, including the PIC setup sequence), or if there is
363 // some use of the LR stack slot (e.g. for builtin_return_address).
364 // (LR comes in 32 and 64 bit versions.)
365 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
366 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
371 void PPCRegisterInfo::
372 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
373 MachineBasicBlock::iterator I) const {
374 if (GuaranteedTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) {
375 // Add (actually subtract) back the amount the callee popped on return.
376 if (int CalleeAmt = I->getOperand(1).getImm()) {
377 bool is64Bit = Subtarget.isPPC64();
379 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
380 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
381 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
382 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
383 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
384 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
385 MachineInstr *MI = I;
386 DebugLoc dl = MI->getDebugLoc();
388 if (isInt<16>(CalleeAmt)) {
389 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg).
392 MachineBasicBlock::iterator MBBI = I;
393 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
394 .addImm(CalleeAmt >> 16);
395 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
396 .addReg(TmpReg, RegState::Kill)
397 .addImm(CalleeAmt & 0xFFFF);
398 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
405 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
409 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered
410 /// register first and then a spilled callee-saved register if that fails.
412 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS,
413 const TargetRegisterClass *RC, int SPAdj) {
414 assert(RS && "Register scavenging must be on");
415 unsigned Reg = RS->FindUnusedReg(RC);
416 // FIXME: move ARM callee-saved reg scan to target independent code, then
417 // search for already spilled CS register here.
419 Reg = RS->scavengeRegister(RC, II, SPAdj);
423 /// lowerDynamicAlloc - Generate the code for allocating an object in the
424 /// current frame. The sequence of code with be in the general form
426 /// addi R0, SP, \#frameSize ; get the address of the previous frame
427 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
428 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
430 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
431 int SPAdj, RegScavenger *RS) const {
432 // Get the instruction.
433 MachineInstr &MI = *II;
434 // Get the instruction's basic block.
435 MachineBasicBlock &MBB = *MI.getParent();
436 // Get the basic block's function.
437 MachineFunction &MF = *MBB.getParent();
438 // Get the frame info.
439 MachineFrameInfo *MFI = MF.getFrameInfo();
440 // Determine whether 64-bit pointers are used.
441 bool LP64 = Subtarget.isPPC64();
442 DebugLoc dl = MI.getDebugLoc();
444 // Get the maximum call stack size.
445 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
446 // Get the total frame size.
447 unsigned FrameSize = MFI->getStackSize();
449 // Get stack alignments.
450 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
451 unsigned MaxAlign = MFI->getMaxAlignment();
452 assert(MaxAlign <= TargetAlign &&
453 "Dynamic alloca with large aligns not supported");
455 // Determine the previous frame's address. If FrameSize can't be
456 // represented as 16 bits or we need special alignment, then we load the
457 // previous frame's address from 0(SP). Why not do an addis of the hi?
458 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
459 // Constructing the constant and adding would take 3 instructions.
460 // Fortunately, a frame greater than 32K is rare.
461 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
462 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
463 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
465 // FIXME (64-bit): Use "findScratchRegister"
467 if (EnableRegisterScavenging)
468 Reg = findScratchRegister(II, RS, RC, SPAdj);
472 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
473 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
477 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
478 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
482 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0)
486 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
491 // Grow the stack and update the stack pointer link, then determine the
492 // address of new allocated space.
494 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
495 BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
496 .addReg(Reg, RegState::Kill)
498 .addReg(MI.getOperand(1).getReg());
500 BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
501 .addReg(PPC::X0, RegState::Kill)
503 .addReg(MI.getOperand(1).getReg());
505 if (!MI.getOperand(1).isKill())
506 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
508 .addImm(maxCallFrameSize);
510 // Implicitly kill the register.
511 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
513 .addImm(maxCallFrameSize)
514 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
516 BuildMI(MBB, II, dl, TII.get(PPC::STWUX))
517 .addReg(Reg, RegState::Kill)
519 .addReg(MI.getOperand(1).getReg());
521 if (!MI.getOperand(1).isKill())
522 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
524 .addImm(maxCallFrameSize);
526 // Implicitly kill the register.
527 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
529 .addImm(maxCallFrameSize)
530 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
533 // Discard the DYNALLOC instruction.
537 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
538 /// reserving a whole register (R0), we scrounge for one here. This generates
541 /// mfcr rA ; Move the conditional register into GPR rA.
542 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
543 /// stw rA, FI ; Store rA to the frame.
545 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
546 unsigned FrameIndex, int SPAdj,
547 RegScavenger *RS) const {
548 // Get the instruction.
549 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI>
550 // Get the instruction's basic block.
551 MachineBasicBlock &MBB = *MI.getParent();
552 DebugLoc dl = MI.getDebugLoc();
554 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
555 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
556 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
557 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
558 unsigned SrcReg = MI.getOperand(0).getReg();
560 // We need to store the CR in the low 4-bits of the saved value. First, issue
561 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
562 BuildMI(MBB, II, dl, TII.get(PPC::MFCRpseud), Reg)
563 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
565 // If the saved register wasn't CR0, shift the bits left so that they are in
567 if (SrcReg != PPC::CR0)
568 // rlwinm rA, rA, ShiftBits, 0, 31.
569 BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg)
570 .addReg(Reg, RegState::Kill)
571 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4)
575 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
576 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
579 // Discard the pseudo instruction.
584 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
585 int SPAdj, FrameIndexValue *Value,
586 RegScavenger *RS) const {
587 assert(SPAdj == 0 && "Unexpected");
589 // Get the instruction.
590 MachineInstr &MI = *II;
591 // Get the instruction's basic block.
592 MachineBasicBlock &MBB = *MI.getParent();
593 // Get the basic block's function.
594 MachineFunction &MF = *MBB.getParent();
595 // Get the frame info.
596 MachineFrameInfo *MFI = MF.getFrameInfo();
597 DebugLoc dl = MI.getDebugLoc();
599 // Find out which operand is the frame index.
600 unsigned FIOperandNo = 0;
601 while (!MI.getOperand(FIOperandNo).isFI()) {
603 assert(FIOperandNo != MI.getNumOperands() &&
604 "Instr doesn't have FrameIndex operand!");
606 // Take into account whether it's an add or mem instruction
607 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
608 if (MI.isInlineAsm())
609 OffsetOperandNo = FIOperandNo-1;
611 // Get the frame index.
612 int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
614 // Get the frame pointer save index. Users of this index are primarily
615 // DYNALLOC instructions.
616 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
617 int FPSI = FI->getFramePointerSaveIndex();
618 // Get the instruction opcode.
619 unsigned OpC = MI.getOpcode();
621 // Special case for dynamic alloca.
622 if (FPSI && FrameIndex == FPSI &&
623 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
624 lowerDynamicAlloc(II, SPAdj, RS);
628 // Special case for pseudo-op SPILL_CR.
629 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default.
630 if (OpC == PPC::SPILL_CR) {
631 lowerCRSpilling(II, FrameIndex, SPAdj, RS);
635 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
636 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1,
639 // Figure out if the offset in the instruction is shifted right two bits. This
640 // is true for instructions like "STD", which the machine implicitly adds two
642 bool isIXAddr = false;
652 // Now add the frame object offset to the offset from r1.
653 int Offset = MFI->getObjectOffset(FrameIndex);
655 Offset += MI.getOperand(OffsetOperandNo).getImm();
657 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
659 // If we're not using a Frame Pointer that has been set to the value of the
660 // SP before having the stack size subtracted from it, then add the stack size
661 // to Offset to get the correct offset.
662 // Naked functions have stack size 0, although getStackSize may not reflect that
663 // because we didn't call all the pieces that compute it for naked functions.
664 if (!MF.getFunction()->hasFnAttr(Attribute::Naked))
665 Offset += MFI->getStackSize();
667 // If we can, encode the offset directly into the instruction. If this is a
668 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
669 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
670 // clear can be encoded. This is extremely uncommon, because normally you
671 // only "std" to a stack slot that is at least 4-byte aligned, but it can
672 // happen in invalid code.
673 if (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
675 Offset >>= 2; // The actual encoded value has the low two bits zero.
676 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
680 // The offset doesn't fit into a single register, scavenge one to build the
682 // FIXME: figure out what SPAdj is doing here.
684 // FIXME (64-bit): Use "findScratchRegister".
686 if (EnableRegisterScavenging)
687 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
691 // Insert a set of rA with the full offset value before the ld, st, or add
692 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg)
693 .addImm(Offset >> 16);
694 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg)
695 .addReg(SReg, RegState::Kill)
698 // Convert into indexed form of the instruction:
700 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
701 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
702 unsigned OperandBase;
704 if (OpC != TargetOpcode::INLINEASM) {
705 assert(ImmToIdxMap.count(OpC) &&
706 "No indexed form of load or store available!");
707 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
708 MI.setDesc(TII.get(NewOpcode));
711 OperandBase = OffsetOperandNo;
714 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
715 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
716 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
720 /// VRRegNo - Map from a numbered VR register to its enum value.
722 static const unsigned short VRRegNo[] = {
723 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
724 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
725 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
726 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
729 /// RemoveVRSaveCode - We have found that this function does not need any code
730 /// to manipulate the VRSAVE register, even though it uses vector registers.
731 /// This can happen when the only registers used are known to be live in or out
732 /// of the function. Remove all of the VRSAVE related code from the function.
733 static void RemoveVRSaveCode(MachineInstr *MI) {
734 MachineBasicBlock *Entry = MI->getParent();
735 MachineFunction *MF = Entry->getParent();
737 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
738 MachineBasicBlock::iterator MBBI = MI;
740 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
741 MBBI->eraseFromParent();
743 bool RemovedAllMTVRSAVEs = true;
744 // See if we can find and remove the MTVRSAVE instruction from all of the
746 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
747 // If last instruction is a return instruction, add an epilogue
748 if (!I->empty() && I->back().getDesc().isReturn()) {
749 bool FoundIt = false;
750 for (MBBI = I->end(); MBBI != I->begin(); ) {
752 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
753 MBBI->eraseFromParent(); // remove it.
758 RemovedAllMTVRSAVEs &= FoundIt;
762 // If we found and removed all MTVRSAVE instructions, remove the read of
764 if (RemovedAllMTVRSAVEs) {
766 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
768 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
769 MBBI->eraseFromParent();
772 // Finally, nuke the UPDATE_VRSAVE.
773 MI->eraseFromParent();
776 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
777 // instruction selector. Based on the vector registers that have been used,
778 // transform this into the appropriate ORI instruction.
779 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
780 MachineFunction *MF = MI->getParent()->getParent();
781 DebugLoc dl = MI->getDebugLoc();
783 unsigned UsedRegMask = 0;
784 for (unsigned i = 0; i != 32; ++i)
785 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
786 UsedRegMask |= 1 << (31-i);
788 // Live in and live out values already must be in the mask, so don't bother
790 for (MachineRegisterInfo::livein_iterator
791 I = MF->getRegInfo().livein_begin(),
792 E = MF->getRegInfo().livein_end(); I != E; ++I) {
793 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
794 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
795 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
797 for (MachineRegisterInfo::liveout_iterator
798 I = MF->getRegInfo().liveout_begin(),
799 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
800 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
801 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
802 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
805 // If no registers are used, turn this into a copy.
806 if (UsedRegMask == 0) {
807 // Remove all VRSAVE code.
808 RemoveVRSaveCode(MI);
812 unsigned SrcReg = MI->getOperand(1).getReg();
813 unsigned DstReg = MI->getOperand(0).getReg();
815 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
816 if (DstReg != SrcReg)
817 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
819 .addImm(UsedRegMask);
821 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
822 .addReg(SrcReg, RegState::Kill)
823 .addImm(UsedRegMask);
824 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
825 if (DstReg != SrcReg)
826 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
828 .addImm(UsedRegMask >> 16);
830 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
831 .addReg(SrcReg, RegState::Kill)
832 .addImm(UsedRegMask >> 16);
834 if (DstReg != SrcReg)
835 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
837 .addImm(UsedRegMask >> 16);
839 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
840 .addReg(SrcReg, RegState::Kill)
841 .addImm(UsedRegMask >> 16);
843 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
844 .addReg(DstReg, RegState::Kill)
845 .addImm(UsedRegMask & 0xFFFF);
848 // Remove the old UPDATE_VRSAVE instruction.
849 MI->eraseFromParent();
852 /// determineFrameLayout - Determine the size of the frame and maximum call
854 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
855 MachineFrameInfo *MFI = MF.getFrameInfo();
857 // Get the number of bytes to allocate from the FrameInfo
858 unsigned FrameSize = MFI->getStackSize();
860 // Get the alignments provided by the target, and the maximum alignment
861 // (if any) of the fixed frame objects.
862 unsigned MaxAlign = MFI->getMaxAlignment();
863 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
864 unsigned AlignMask = TargetAlign - 1; //
866 // If we are a leaf function, and use up to 224 bytes of stack space,
867 // don't have a frame pointer, calls, or dynamic alloca then we do not need
868 // to adjust the stack pointer (we fit in the Red Zone).
869 bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone);
870 // FIXME SVR4 The 32-bit SVR4 ABI has no red zone.
871 if (!DisableRedZone &&
872 FrameSize <= 224 && // Fits in red zone.
873 !MFI->hasVarSizedObjects() && // No dynamic alloca.
874 !MFI->adjustsStack() && // No calls.
875 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
877 MFI->setStackSize(0);
881 // Get the maximum call frame size of all the calls.
882 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
884 // Maximum call frame needs to be at least big enough for linkage and 8 args.
885 unsigned minCallFrameSize =
886 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
887 Subtarget.isDarwinABI());
888 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
890 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
891 // that allocations will be aligned.
892 if (MFI->hasVarSizedObjects())
893 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
895 // Update maximum call frame size.
896 MFI->setMaxCallFrameSize(maxCallFrameSize);
898 // Include call frame size in total.
899 FrameSize += maxCallFrameSize;
901 // Make sure the frame is aligned.
902 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
904 // Update frame info.
905 MFI->setStackSize(FrameSize);
909 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
910 RegScavenger *RS) const {
911 // Save and clear the LR state.
912 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
913 unsigned LR = getRARegister();
914 FI->setMustSaveLR(MustSaveLR(MF, LR));
915 MF.getRegInfo().setPhysRegUnused(LR);
917 // Save R31 if necessary
918 int FPSI = FI->getFramePointerSaveIndex();
919 bool isPPC64 = Subtarget.isPPC64();
920 bool isDarwinABI = Subtarget.isDarwinABI();
921 MachineFrameInfo *MFI = MF.getFrameInfo();
923 // If the frame pointer save index hasn't been defined yet.
924 if (!FPSI && needsFP(MF)) {
925 // Find out what the fix offset of the frame pointer save area.
926 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64,
928 // Allocate the frame index for frame pointer save area.
929 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset,
932 FI->setFramePointerSaveIndex(FPSI);
935 // Reserve stack space to move the linkage area to in case of a tail call.
937 if (GuaranteedTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
938 MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta,
942 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
943 // a large stack, which will require scavenging a register to materialize a
945 // FIXME: this doesn't actually check stack size, so is a bit pessimistic
946 // FIXME: doesn't detect whether or not we need to spill vXX, which requires
949 if (EnableRegisterScavenging) // FIXME (64-bit): Enable.
950 if (needsFP(MF) || spillsCR(MF)) {
951 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
952 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
953 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC;
954 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
961 PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
963 // Early exit if not using the SVR4 ABI.
964 if (!Subtarget.isSVR4ABI()) {
968 // Get callee saved register information.
969 MachineFrameInfo *FFI = MF.getFrameInfo();
970 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
972 // Early exit if no callee saved registers are modified!
973 if (CSI.empty() && !needsFP(MF)) {
977 unsigned MinGPR = PPC::R31;
978 unsigned MinG8R = PPC::X31;
979 unsigned MinFPR = PPC::F31;
980 unsigned MinVR = PPC::V31;
982 bool HasGPSaveArea = false;
983 bool HasG8SaveArea = false;
984 bool HasFPSaveArea = false;
985 bool HasCRSaveArea = false;
986 bool HasVRSAVESaveArea = false;
987 bool HasVRSaveArea = false;
989 SmallVector<CalleeSavedInfo, 18> GPRegs;
990 SmallVector<CalleeSavedInfo, 18> G8Regs;
991 SmallVector<CalleeSavedInfo, 18> FPRegs;
992 SmallVector<CalleeSavedInfo, 18> VRegs;
994 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
995 unsigned Reg = CSI[i].getReg();
996 if (PPC::GPRCRegisterClass->contains(Reg)) {
997 HasGPSaveArea = true;
999 GPRegs.push_back(CSI[i]);
1004 } else if (PPC::G8RCRegisterClass->contains(Reg)) {
1005 HasG8SaveArea = true;
1007 G8Regs.push_back(CSI[i]);
1012 } else if (PPC::F8RCRegisterClass->contains(Reg)) {
1013 HasFPSaveArea = true;
1015 FPRegs.push_back(CSI[i]);
1020 // FIXME SVR4: Disable CR save area for now.
1021 } else if (PPC::CRBITRCRegisterClass->contains(Reg)
1022 || PPC::CRRCRegisterClass->contains(Reg)) {
1023 // HasCRSaveArea = true;
1024 } else if (PPC::VRSAVERCRegisterClass->contains(Reg)) {
1025 HasVRSAVESaveArea = true;
1026 } else if (PPC::VRRCRegisterClass->contains(Reg)) {
1027 HasVRSaveArea = true;
1029 VRegs.push_back(CSI[i]);
1035 llvm_unreachable("Unknown RegisterClass!");
1039 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
1041 int64_t LowerBound = 0;
1043 // Take into account stack space reserved for tail calls.
1045 if (GuaranteedTailCallOpt && (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1046 LowerBound = TCSPDelta;
1049 // The Floating-point register save area is right below the back chain word
1050 // of the previous stack frame.
1051 if (HasFPSaveArea) {
1052 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1053 int FI = FPRegs[i].getFrameIdx();
1055 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1058 LowerBound -= (31 - getRegisterNumbering(MinFPR) + 1) * 8;
1061 // Check whether the frame pointer register is allocated. If so, make sure it
1062 // is spilled to the correct offset.
1064 HasGPSaveArea = true;
1066 int FI = PFI->getFramePointerSaveIndex();
1067 assert(FI && "No Frame Pointer Save Slot!");
1069 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1072 // General register save area starts right below the Floating-point
1073 // register save area.
1074 if (HasGPSaveArea || HasG8SaveArea) {
1075 // Move general register save area spill slots down, taking into account
1076 // the size of the Floating-point register save area.
1077 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1078 int FI = GPRegs[i].getFrameIdx();
1080 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1083 // Move general register save area spill slots down, taking into account
1084 // the size of the Floating-point register save area.
1085 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1086 int FI = G8Regs[i].getFrameIdx();
1088 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1091 unsigned MinReg = std::min<unsigned>(getRegisterNumbering(MinGPR),
1092 getRegisterNumbering(MinG8R));
1094 if (Subtarget.isPPC64()) {
1095 LowerBound -= (31 - MinReg + 1) * 8;
1097 LowerBound -= (31 - MinReg + 1) * 4;
1101 // The CR save area is below the general register save area.
1102 if (HasCRSaveArea) {
1103 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1104 // which have the CR/CRBIT register class?
1105 // Adjust the frame index of the CR spill slot.
1106 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1107 unsigned Reg = CSI[i].getReg();
1109 if (PPC::CRBITRCRegisterClass->contains(Reg) ||
1110 PPC::CRRCRegisterClass->contains(Reg)) {
1111 int FI = CSI[i].getFrameIdx();
1113 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1117 LowerBound -= 4; // The CR save area is always 4 bytes long.
1120 if (HasVRSAVESaveArea) {
1121 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1122 // which have the VRSAVE register class?
1123 // Adjust the frame index of the VRSAVE spill slot.
1124 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1125 unsigned Reg = CSI[i].getReg();
1127 if (PPC::VRSAVERCRegisterClass->contains(Reg)) {
1128 int FI = CSI[i].getFrameIdx();
1130 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1134 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1137 if (HasVRSaveArea) {
1138 // Insert alignment padding, we need 16-byte alignment.
1139 LowerBound = (LowerBound - 15) & ~(15);
1141 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1142 int FI = VRegs[i].getFrameIdx();
1144 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1150 PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
1151 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
1152 MachineBasicBlock::iterator MBBI = MBB.begin();
1153 MachineFrameInfo *MFI = MF.getFrameInfo();
1154 MachineModuleInfo &MMI = MF.getMMI();
1156 bool needsFrameMoves = MMI.hasDebugInfo() ||
1157 !MF.getFunction()->doesNotThrow() ||
1158 UnwindTablesMandatory;
1160 // Prepare for frame info.
1161 MCSymbol *FrameLabel = 0;
1163 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
1165 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
1166 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
1167 HandleVRSaveUpdate(MBBI, TII);
1172 // Move MBBI back to the beginning of the function.
1175 // Work out frame sizes.
1176 determineFrameLayout(MF);
1177 unsigned FrameSize = MFI->getStackSize();
1179 int NegFrameSize = -FrameSize;
1181 // Get processor type.
1182 bool isPPC64 = Subtarget.isPPC64();
1183 // Get operating system
1184 bool isDarwinABI = Subtarget.isDarwinABI();
1185 // Check if the link register (LR) must be saved.
1186 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1187 bool MustSaveLR = FI->mustSaveLR();
1188 // Do we have a frame pointer for this function?
1189 bool HasFP = hasFP(MF) && FrameSize;
1191 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI);
1195 if (Subtarget.isSVR4ABI()) {
1196 MachineFrameInfo *FFI = MF.getFrameInfo();
1197 int FPIndex = FI->getFramePointerSaveIndex();
1198 assert(FPIndex && "No Frame Pointer Save Slot!");
1199 FPOffset = FFI->getObjectOffset(FPIndex);
1201 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
1207 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
1210 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
1216 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
1218 .addImm(LROffset / 4)
1222 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
1225 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
1231 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
1237 // Skip if a leaf routine.
1238 if (!FrameSize) return;
1240 // Get stack alignments.
1241 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1242 unsigned MaxAlign = MFI->getMaxAlignment();
1244 // Adjust stack pointer: r1 += NegFrameSize.
1245 // If there is a preferred stack alignment, align R1 now
1248 if (ALIGN_STACK && MaxAlign > TargetAlign) {
1249 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
1250 "Invalid alignment!");
1251 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
1253 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
1256 .addImm(32 - Log2_32(MaxAlign))
1258 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
1259 .addReg(PPC::R0, RegState::Kill)
1260 .addImm(NegFrameSize);
1261 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
1265 } else if (isInt<16>(NegFrameSize)) {
1266 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
1268 .addImm(NegFrameSize)
1271 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
1272 .addImm(NegFrameSize >> 16);
1273 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
1274 .addReg(PPC::R0, RegState::Kill)
1275 .addImm(NegFrameSize & 0xFFFF);
1276 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
1282 if (ALIGN_STACK && MaxAlign > TargetAlign) {
1283 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
1284 "Invalid alignment!");
1285 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
1287 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
1290 .addImm(64 - Log2_32(MaxAlign));
1291 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
1293 .addImm(NegFrameSize);
1294 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
1298 } else if (isInt<16>(NegFrameSize)) {
1299 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
1301 .addImm(NegFrameSize / 4)
1304 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
1305 .addImm(NegFrameSize >> 16);
1306 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
1307 .addReg(PPC::X0, RegState::Kill)
1308 .addImm(NegFrameSize & 0xFFFF);
1309 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
1316 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
1318 // Add the "machine moves" for the instructions we generated above, but in
1320 if (needsFrameMoves) {
1321 // Mark effective beginning of when frame pointer becomes valid.
1322 FrameLabel = MMI.getContext().CreateTempSymbol();
1323 BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addSym(FrameLabel);
1325 // Show update of SP.
1327 MachineLocation SPDst(MachineLocation::VirtualFP);
1328 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
1329 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
1331 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31);
1332 Moves.push_back(MachineMove(FrameLabel, SP, SP));
1336 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
1337 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31);
1338 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
1342 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
1343 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR);
1344 Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc));
1348 MCSymbol *ReadyLabel = 0;
1350 // If there is a frame pointer, copy R1 into R31
1353 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
1357 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31)
1362 if (needsFrameMoves) {
1363 ReadyLabel = MMI.getContext().CreateTempSymbol();
1365 // Mark effective beginning of when frame pointer is ready.
1366 BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addSym(ReadyLabel);
1368 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) :
1369 (isPPC64 ? PPC::X1 : PPC::R1));
1370 MachineLocation FPSrc(MachineLocation::VirtualFP);
1371 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc));
1375 if (needsFrameMoves) {
1376 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel;
1378 // Add callee saved registers to move list.
1379 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1380 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1381 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1382 unsigned Reg = CSI[I].getReg();
1383 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
1384 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1385 MachineLocation CSSrc(Reg);
1386 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
1391 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
1392 MachineBasicBlock &MBB) const {
1393 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1394 unsigned RetOpcode = MBBI->getOpcode();
1397 assert( (RetOpcode == PPC::BLR ||
1398 RetOpcode == PPC::TCRETURNri ||
1399 RetOpcode == PPC::TCRETURNdi ||
1400 RetOpcode == PPC::TCRETURNai ||
1401 RetOpcode == PPC::TCRETURNri8 ||
1402 RetOpcode == PPC::TCRETURNdi8 ||
1403 RetOpcode == PPC::TCRETURNai8) &&
1404 "Can only insert epilog into returning blocks");
1406 // Get alignment info so we know how to restore r1
1407 const MachineFrameInfo *MFI = MF.getFrameInfo();
1408 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1409 unsigned MaxAlign = MFI->getMaxAlignment();
1411 // Get the number of bytes allocated from the FrameInfo.
1412 int FrameSize = MFI->getStackSize();
1414 // Get processor type.
1415 bool isPPC64 = Subtarget.isPPC64();
1416 // Get operating system
1417 bool isDarwinABI = Subtarget.isDarwinABI();
1418 // Check if the link register (LR) has been saved.
1419 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1420 bool MustSaveLR = FI->mustSaveLR();
1421 // Do we have a frame pointer for this function?
1422 bool HasFP = hasFP(MF) && FrameSize;
1424 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI);
1428 if (Subtarget.isSVR4ABI()) {
1429 MachineFrameInfo *FFI = MF.getFrameInfo();
1430 int FPIndex = FI->getFramePointerSaveIndex();
1431 assert(FPIndex && "No Frame Pointer Save Slot!");
1432 FPOffset = FFI->getObjectOffset(FPIndex);
1434 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
1438 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1439 RetOpcode == PPC::TCRETURNdi ||
1440 RetOpcode == PPC::TCRETURNai ||
1441 RetOpcode == PPC::TCRETURNri8 ||
1442 RetOpcode == PPC::TCRETURNdi8 ||
1443 RetOpcode == PPC::TCRETURNai8;
1446 int MaxTCRetDelta = FI->getTailCallSPDelta();
1447 MachineOperand &StackAdjust = MBBI->getOperand(1);
1448 assert(StackAdjust.isImm() && "Expecting immediate value.");
1449 // Adjust stack pointer.
1450 int StackAdj = StackAdjust.getImm();
1451 int Delta = StackAdj - MaxTCRetDelta;
1452 assert((Delta >= 0) && "Delta must be positive");
1453 if (MaxTCRetDelta>0)
1454 FrameSize += (StackAdj +Delta);
1456 FrameSize += StackAdj;
1460 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
1461 // on entry to the function. Add this offset back now.
1463 // If this function contained a fastcc call and GuaranteedTailCallOpt is
1464 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
1465 // call which invalidates the stack pointer value in SP(0). So we use the
1466 // value of R31 in this case.
1467 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
1468 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
1469 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
1470 .addReg(PPC::R31).addImm(FrameSize);
1471 } else if(FI->hasFastCall()) {
1472 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
1473 .addImm(FrameSize >> 16);
1474 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
1475 .addReg(PPC::R0, RegState::Kill)
1476 .addImm(FrameSize & 0xFFFF);
1477 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
1481 } else if (isInt<16>(FrameSize) &&
1482 (!ALIGN_STACK || TargetAlign >= MaxAlign) &&
1483 !MFI->hasVarSizedObjects()) {
1484 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
1485 .addReg(PPC::R1).addImm(FrameSize);
1487 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1)
1488 .addImm(0).addReg(PPC::R1);
1491 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
1492 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
1493 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
1494 .addReg(PPC::X31).addImm(FrameSize);
1495 } else if(FI->hasFastCall()) {
1496 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
1497 .addImm(FrameSize >> 16);
1498 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
1499 .addReg(PPC::X0, RegState::Kill)
1500 .addImm(FrameSize & 0xFFFF);
1501 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
1505 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign &&
1506 !MFI->hasVarSizedObjects()) {
1507 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
1508 .addReg(PPC::X1).addImm(FrameSize);
1510 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1)
1511 .addImm(0).addReg(PPC::X1);
1518 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0)
1519 .addImm(LROffset/4).addReg(PPC::X1);
1522 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31)
1523 .addImm(FPOffset/4).addReg(PPC::X1);
1526 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0);
1529 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
1530 .addImm(LROffset).addReg(PPC::R1);
1533 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31)
1534 .addImm(FPOffset).addReg(PPC::R1);
1537 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0);
1540 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1541 // call optimization
1542 if (GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
1543 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
1544 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1545 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1546 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1;
1547 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1548 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0;
1549 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI;
1550 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4;
1551 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS;
1552 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI;
1554 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
1555 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg)
1556 .addReg(StackReg).addImm(CallerAllocatedAmt);
1558 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1559 .addImm(CallerAllocatedAmt >> 16);
1560 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1561 .addReg(TmpReg, RegState::Kill)
1562 .addImm(CallerAllocatedAmt & 0xFFFF);
1563 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
1568 } else if (RetOpcode == PPC::TCRETURNdi) {
1569 MBBI = prior(MBB.end());
1570 MachineOperand &JumpTarget = MBBI->getOperand(0);
1571 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1572 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1573 } else if (RetOpcode == PPC::TCRETURNri) {
1574 MBBI = prior(MBB.end());
1575 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1576 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1577 } else if (RetOpcode == PPC::TCRETURNai) {
1578 MBBI = prior(MBB.end());
1579 MachineOperand &JumpTarget = MBBI->getOperand(0);
1580 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1581 } else if (RetOpcode == PPC::TCRETURNdi8) {
1582 MBBI = prior(MBB.end());
1583 MachineOperand &JumpTarget = MBBI->getOperand(0);
1584 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1585 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1586 } else if (RetOpcode == PPC::TCRETURNri8) {
1587 MBBI = prior(MBB.end());
1588 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1589 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1590 } else if (RetOpcode == PPC::TCRETURNai8) {
1591 MBBI = prior(MBB.end());
1592 MachineOperand &JumpTarget = MBBI->getOperand(0);
1593 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1597 unsigned PPCRegisterInfo::getRARegister() const {
1598 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
1601 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1602 if (!Subtarget.isPPC64())
1603 return hasFP(MF) ? PPC::R31 : PPC::R1;
1605 return hasFP(MF) ? PPC::X31 : PPC::X1;
1608 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1610 // Initial state of the frame pointer is R1.
1611 MachineLocation Dst(MachineLocation::VirtualFP);
1612 MachineLocation Src(PPC::R1, 0);
1613 Moves.push_back(MachineMove(0, Dst, Src));
1616 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
1617 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
1620 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
1621 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
1624 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1625 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
1626 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1629 #include "PPCGenRegisterInfo.inc"