1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PPCInstrBuilder.h"
17 #include "PPCRegisterInfo.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineDebugInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineLocation.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/ADT/STLExtras.h"
38 PPCRegisterInfo::PPCRegisterInfo()
39 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
40 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
41 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
42 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
43 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
44 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
45 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
46 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
47 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
51 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator MI,
53 unsigned SrcReg, int FrameIdx,
54 const TargetRegisterClass *RC) const {
55 if (SrcReg == PPC::LR) {
56 // FIXME: this spills LR immediately to memory in one step. To do this, we
57 // use R11, which we know cannot be used in the prolog/epilog. This is a
59 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
60 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
61 } else if (RC == PPC::CRRCRegisterClass) {
62 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
63 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
64 } else if (RC == PPC::GPRCRegisterClass) {
65 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
66 } else if (RC == PPC::G8RCRegisterClass) {
67 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx);
68 } else if (RC == PPC::F8RCRegisterClass) {
69 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
70 } else if (RC == PPC::F4RCRegisterClass) {
71 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
72 } else if (RC == PPC::VRRCRegisterClass) {
73 // We don't have indexed addressing for vector loads. Emit:
77 // FIXME: We use R0 here, because it isn't available for RA.
78 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
79 BuildMI(MBB, MI, PPC::STVX, 3)
80 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
82 assert(0 && "Unknown regclass!");
88 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
89 MachineBasicBlock::iterator MI,
90 unsigned DestReg, int FrameIdx,
91 const TargetRegisterClass *RC) const {
92 if (DestReg == PPC::LR) {
93 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
94 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
95 } else if (RC == PPC::CRRCRegisterClass) {
96 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
97 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
98 } else if (RC == PPC::GPRCRegisterClass) {
99 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
100 } else if (RC == PPC::G8RCRegisterClass) {
101 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
102 } else if (RC == PPC::F8RCRegisterClass) {
103 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
104 } else if (RC == PPC::F4RCRegisterClass) {
105 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
106 } else if (RC == PPC::VRRCRegisterClass) {
107 // We don't have indexed addressing for vector loads. Emit:
109 // Dest = LVX R0, R11
111 // FIXME: We use R0 here, because it isn't available for RA.
112 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
113 BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
115 assert(0 && "Unknown regclass!");
120 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
121 MachineBasicBlock::iterator MI,
122 unsigned DestReg, unsigned SrcReg,
123 const TargetRegisterClass *RC) const {
124 if (RC == PPC::GPRCRegisterClass) {
125 BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
126 } else if (RC == PPC::G8RCRegisterClass) {
127 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
128 } else if (RC == PPC::F4RCRegisterClass) {
129 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
130 } else if (RC == PPC::F8RCRegisterClass) {
131 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
132 } else if (RC == PPC::CRRCRegisterClass) {
133 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
134 } else if (RC == PPC::VRRCRegisterClass) {
135 BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
137 std::cerr << "Attempt to copy register that is not GPR or FPR";
142 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
143 /// copy instructions, turning them into load/store instructions.
144 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
146 int FrameIndex) const {
147 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
148 // it takes more than one instruction to store it.
149 unsigned Opc = MI->getOpcode();
151 if ((Opc == PPC::OR4 &&
152 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
153 if (OpNum == 0) { // move -> store
154 unsigned InReg = MI->getOperand(1).getReg();
155 return addFrameReference(BuildMI(PPC::STW,
156 3).addReg(InReg), FrameIndex);
157 } else { // move -> load
158 unsigned OutReg = MI->getOperand(0).getReg();
159 return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
161 } else if ((Opc == PPC::OR8 &&
162 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
163 if (OpNum == 0) { // move -> store
164 unsigned InReg = MI->getOperand(1).getReg();
165 return addFrameReference(BuildMI(PPC::STD,
166 3).addReg(InReg), FrameIndex);
167 } else { // move -> load
168 unsigned OutReg = MI->getOperand(0).getReg();
169 return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex);
171 } else if (Opc == PPC::FMRD) {
172 if (OpNum == 0) { // move -> store
173 unsigned InReg = MI->getOperand(1).getReg();
174 return addFrameReference(BuildMI(PPC::STFD,
175 3).addReg(InReg), FrameIndex);
176 } else { // move -> load
177 unsigned OutReg = MI->getOperand(0).getReg();
178 return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex);
180 } else if (Opc == PPC::FMRS) {
181 if (OpNum == 0) { // move -> store
182 unsigned InReg = MI->getOperand(1).getReg();
183 return addFrameReference(BuildMI(PPC::STFS,
184 3).addReg(InReg), FrameIndex);
185 } else { // move -> load
186 unsigned OutReg = MI->getOperand(0).getReg();
187 return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex);
193 //===----------------------------------------------------------------------===//
194 // Stack Frame Processing methods
195 //===----------------------------------------------------------------------===//
197 // hasFP - Return true if the specified function should have a dedicated frame
198 // pointer register. This is true if the function has variable sized allocas or
199 // if frame pointer elimination is disabled.
201 static bool hasFP(const MachineFunction &MF) {
202 const MachineFrameInfo *MFI = MF.getFrameInfo();
203 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
205 // If frame pointers are forced, or if there are variable sized stack objects,
206 // use a frame pointer.
208 return NoFramePointerElim || MFI->hasVarSizedObjects();
211 void PPCRegisterInfo::
212 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
213 MachineBasicBlock::iterator I) const {
215 // If we have a frame pointer, convert as follows:
216 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
217 // ADJCALLSTACKUP -> addi, r1, r1, amount
218 MachineInstr *Old = I;
219 unsigned Amount = Old->getOperand(0).getImmedValue();
221 // We need to keep the stack aligned properly. To do this, we round the
222 // amount of space needed for the outgoing arguments up to the next
223 // alignment boundary.
224 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
225 Amount = (Amount+Align-1)/Align*Align;
227 // Replace the pseudo instruction with a new instruction...
228 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
229 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(-Amount);
231 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
232 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(Amount);
240 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
242 MachineInstr &MI = *II;
243 MachineBasicBlock &MBB = *MI.getParent();
244 MachineFunction &MF = *MBB.getParent();
246 while (!MI.getOperand(i).isFrameIndex()) {
248 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
251 int FrameIndex = MI.getOperand(i).getFrameIndex();
253 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
254 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
256 // Take into account whether it's an add or mem instruction
257 unsigned OffIdx = (i == 2) ? 1 : 2;
259 // Now add the frame object offset to the offset from r1.
260 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
261 MI.getOperand(OffIdx).getImmedValue();
263 // If we're not using a Frame Pointer that has been set to the value of the
264 // SP before having the stack size subtracted from it, then add the stack size
265 // to Offset to get the correct offset.
266 Offset += MF.getFrameInfo()->getStackSize();
268 if (Offset > 32767 || Offset < -32768) {
269 // Insert a set of r0 with the full offset value before the ld, st, or add
270 MachineBasicBlock *MBB = MI.getParent();
271 BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16);
272 BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset);
274 // convert into indexed form of the instruction
275 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
276 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
277 assert(ImmToIdxMap.count(MI.getOpcode()) &&
278 "No indexed form of load or store available!");
279 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
280 MI.setOpcode(NewOpcode);
281 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
282 MI.SetMachineOperandReg(2, PPC::R0);
284 switch (MI.getOpcode()) {
289 assert((Offset & 3) == 0 && "Invalid frame offset!");
290 Offset >>= 2; // The actual encoded value has the low two bits zero.
293 MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
298 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
299 // instruction selector. Based on the vector registers that have been used,
300 // transform this into the appropriate ORI instruction.
301 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) {
302 unsigned UsedRegMask = 0;
303 #define HANDLEREG(N) if (UsedRegs[PPC::V##N]) UsedRegMask |= 1 << (31-N)
304 HANDLEREG( 0); HANDLEREG( 1); HANDLEREG( 2); HANDLEREG( 3);
305 HANDLEREG( 4); HANDLEREG( 5); HANDLEREG( 6); HANDLEREG( 7);
306 HANDLEREG( 8); HANDLEREG( 9); HANDLEREG(10); HANDLEREG(11);
307 HANDLEREG(12); HANDLEREG(13); HANDLEREG(14); HANDLEREG(15);
308 HANDLEREG(16); HANDLEREG(17); HANDLEREG(18); HANDLEREG(19);
309 HANDLEREG(20); HANDLEREG(21); HANDLEREG(22); HANDLEREG(23);
310 HANDLEREG(24); HANDLEREG(25); HANDLEREG(26); HANDLEREG(27);
311 HANDLEREG(28); HANDLEREG(29); HANDLEREG(30); HANDLEREG(31);
313 unsigned SrcReg = MI->getOperand(1).getReg();
314 unsigned DstReg = MI->getOperand(0).getReg();
315 // If no registers are used, turn this into a copy.
316 if (UsedRegMask == 0) {
317 if (SrcReg != DstReg)
318 BuildMI(*MI->getParent(), MI, PPC::OR4, 2, DstReg)
319 .addReg(SrcReg).addReg(SrcReg);
320 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
321 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
322 .addReg(SrcReg).addImm(UsedRegMask);
323 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
324 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
325 .addReg(SrcReg).addImm(UsedRegMask >> 16);
327 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
328 .addReg(SrcReg).addImm(UsedRegMask >> 16);
329 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
330 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
333 // Remove the old UPDATE_VRSAVE instruction.
334 MI->getParent()->erase(MI);
338 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
339 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
340 MachineBasicBlock::iterator MBBI = MBB.begin();
341 MachineFrameInfo *MFI = MF.getFrameInfo();
342 MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo();
344 // Do we have a frame pointer for this function?
345 bool HasFP = hasFP(MF);
347 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
349 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
350 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
351 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
356 // Move MBBI back to the beginning of the function.
359 // Get the number of bytes to allocate from the FrameInfo
360 unsigned NumBytes = MFI->getStackSize();
362 // Get the alignments provided by the target, and the maximum alignment
363 // (if any) of the fixed frame objects.
364 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
365 unsigned MaxAlign = MFI->getMaxAlignment();
367 // If we have calls, we cannot use the red zone to store callee save registers
368 // and we must set up a stack frame, so calculate the necessary size here.
369 if (MFI->hasCalls()) {
370 // We reserve argument space for call sites in the function immediately on
371 // entry to the current function. This eliminates the need for add/sub
372 // brackets around call sites.
373 NumBytes += MFI->getMaxCallFrameSize();
376 // If we are a leaf function, and use up to 224 bytes of stack space,
377 // and don't have a frame pointer, then we do not need to adjust the stack
378 // pointer (we fit in the Red Zone).
379 if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() &&
380 MaxAlign <= TargetAlign)) {
381 MFI->setStackSize(0);
385 // Add the size of R1 to NumBytes size for the store of R1 to the bottom
386 // of the stack and round the size to a multiple of the alignment.
387 unsigned Align = std::max(TargetAlign, MaxAlign);
388 unsigned GPRSize = 4;
389 unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize;
390 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
392 // Update frame info to pretend that this is part of the stack...
393 MFI->setStackSize(NumBytes);
394 int NegNumbytes = -NumBytes;
396 // Adjust stack pointer: r1 -= numbytes.
397 // If there is a preferred stack alignment, align R1 now
398 if (MaxAlign > TargetAlign) {
399 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!");
400 assert(isInt16(MaxAlign-NumBytes) && "Unhandled stack size and alignment!");
401 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
402 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
403 BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
404 .addSImm(MaxAlign-NumBytes);
405 BuildMI(MBB, MBBI, PPC::STWUX, 3)
406 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
407 } else if (NumBytes <= 32768) {
408 BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addSImm(NegNumbytes)
411 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
412 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
413 .addImm(NegNumbytes & 0xFFFF);
414 BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
418 if (DebugInfo && DebugInfo->hasInfo()) {
419 std::vector<MachineMove *> &Moves = DebugInfo->getFrameMoves();
420 unsigned LabelID = DebugInfo->NextLabelID();
422 // Show update of SP.
423 MachineLocation Dst(MachineLocation::VirtualFP);
424 MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes);
425 Moves.push_back(new MachineMove(LabelID, Dst, Src));
427 BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addSImm(LabelID);
430 // If there is a frame pointer, copy R1 (SP) into R31 (FP)
432 BuildMI(MBB, MBBI, PPC::STW, 3)
433 .addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
434 BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
438 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
439 MachineBasicBlock &MBB) const {
440 MachineBasicBlock::iterator MBBI = prior(MBB.end());
441 assert(MBBI->getOpcode() == PPC::BLR &&
442 "Can only insert epilog into returning blocks");
444 // Get alignment info so we know how to restore r1
445 const MachineFrameInfo *MFI = MF.getFrameInfo();
446 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
448 // Get the number of bytes allocated from the FrameInfo.
449 unsigned NumBytes = MFI->getStackSize();
450 unsigned GPRSize = 4;
453 // If this function has a frame pointer, load the saved stack pointer from
456 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
457 .addSImm(GPRSize).addReg(PPC::R31);
460 // The loaded (or persistent) stack pointer value is offseted by the 'stwu'
461 // on entry to the function. Add this offset back now.
462 if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) {
463 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
464 .addReg(PPC::R1).addSImm(NumBytes);
466 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
471 unsigned PPCRegisterInfo::getRARegister() const {
475 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
476 return hasFP(MF) ? PPC::R31 : PPC::R1;
479 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves)
481 // Initial state is the frame pointer is R1.
482 MachineLocation Dst(MachineLocation::VirtualFP);
483 MachineLocation Src(PPC::R1, 0);
484 Moves.push_back(new MachineMove(0, Dst, Src));
487 #include "PPCGenRegisterInfo.inc"