1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "PPCRegisterInfo.h"
17 #include "PPCFrameLowering.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCSubtarget.h"
21 #include "PPCTargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/RegisterScavenging.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Type.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetFrameLowering.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
47 #define DEBUG_TYPE "reginfo"
49 #define GET_REGINFO_TARGET_DESC
50 #include "PPCGenRegisterInfo.inc"
53 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
54 cl::desc("Enable use of a base pointer for complex stack frames"));
57 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
58 cl::desc("Force the use of a base pointer in every function"));
60 PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
61 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
63 TM.isPPC64() ? 0 : 1),
65 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
66 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
67 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
68 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
69 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
70 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
71 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
72 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
73 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
76 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
77 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
78 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
79 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
80 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
83 /// getPointerRegClass - Return the register class to use to hold pointers.
84 /// This is used for addressing modes.
85 const TargetRegisterClass *
86 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
88 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
89 // when it checks for ZERO folding.
92 return &PPC::G8RC_NOX0RegClass;
93 return &PPC::GPRC_NOR0RegClass;
97 return &PPC::G8RCRegClass;
98 return &PPC::GPRCRegClass;
102 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
103 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
104 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg) {
105 if (Subtarget.hasVSX())
106 return CSR_64_AllRegs_VSX_SaveList;
107 if (Subtarget.hasAltivec())
108 return CSR_64_AllRegs_Altivec_SaveList;
109 return CSR_64_AllRegs_SaveList;
112 if (Subtarget.isDarwinABI())
114 ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList
115 : CSR_Darwin64_SaveList)
116 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList
117 : CSR_Darwin32_SaveList);
119 // On PPC64, we might need to save r2 (but only if it is not reserved).
120 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2);
123 ? (Subtarget.hasAltivec()
124 ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList
125 : CSR_SVR464_Altivec_SaveList)
126 : (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList))
127 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList
128 : CSR_SVR432_SaveList);
132 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
133 CallingConv::ID CC) const {
134 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
135 if (CC == CallingConv::AnyReg) {
136 if (Subtarget.hasVSX())
137 return CSR_64_AllRegs_VSX_RegMask;
138 if (Subtarget.hasAltivec())
139 return CSR_64_AllRegs_Altivec_RegMask;
140 return CSR_64_AllRegs_RegMask;
143 if (Subtarget.isDarwinABI())
144 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask
145 : CSR_Darwin64_RegMask)
146 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask
147 : CSR_Darwin32_RegMask);
149 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask
150 : CSR_SVR464_RegMask)
151 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask
152 : CSR_SVR432_RegMask);
156 PPCRegisterInfo::getNoPreservedMask() const {
157 return CSR_NoRegs_RegMask;
160 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
161 for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
162 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
165 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
166 BitVector Reserved(getNumRegs());
167 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
168 const PPCFrameLowering *PPCFI =
169 static_cast<const PPCFrameLowering *>(Subtarget.getFrameLowering());
171 // The ZERO register is not really a register, but the representation of r0
172 // when used in instructions that treat r0 as the constant 0.
173 Reserved.set(PPC::ZERO);
174 Reserved.set(PPC::ZERO8);
176 // The FP register is also not really a register, but is the representation
177 // of the frame pointer register used by ISD::FRAMEADDR.
178 Reserved.set(PPC::FP);
179 Reserved.set(PPC::FP8);
181 // The BP register is also not really a register, but is the representation
182 // of the base pointer register used by setjmp.
183 Reserved.set(PPC::BP);
184 Reserved.set(PPC::BP8);
186 // The counter registers must be reserved so that counter-based loops can
187 // be correctly formed (and the mtctr instructions are not DCE'd).
188 Reserved.set(PPC::CTR);
189 Reserved.set(PPC::CTR8);
191 Reserved.set(PPC::R1);
192 Reserved.set(PPC::LR);
193 Reserved.set(PPC::LR8);
194 Reserved.set(PPC::RM);
196 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec())
197 Reserved.set(PPC::VRSAVE);
199 // The SVR4 ABI reserves r2 and r13
200 if (Subtarget.isSVR4ABI()) {
201 Reserved.set(PPC::R2); // System-reserved register
202 Reserved.set(PPC::R13); // Small Data Area pointer register
205 // On PPC64, r13 is the thread pointer. Never allocate this register.
207 Reserved.set(PPC::R13);
209 Reserved.set(PPC::X1);
210 Reserved.set(PPC::X13);
212 if (PPCFI->needsFP(MF))
213 Reserved.set(PPC::X31);
215 if (hasBasePointer(MF))
216 Reserved.set(PPC::X30);
218 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
219 if (Subtarget.isSVR4ABI()) {
220 // We only reserve r2 if we need to use the TOC pointer. If we have no
221 // explicit uses of the TOC pointer (meaning we're a leaf function with
222 // no constant-pool loads, etc.) and we have no potential uses inside an
223 // inline asm block, then we can treat r2 has an ordinary callee-saved
225 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
226 if (FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
227 Reserved.set(PPC::X2);
229 Reserved.reset(PPC::R2);
233 if (PPCFI->needsFP(MF))
234 Reserved.set(PPC::R31);
236 if (hasBasePointer(MF)) {
237 if (Subtarget.isSVR4ABI() && !TM.isPPC64() &&
238 TM.getRelocationModel() == Reloc::PIC_)
239 Reserved.set(PPC::R29);
241 Reserved.set(PPC::R30);
244 if (Subtarget.isSVR4ABI() && !TM.isPPC64() &&
245 TM.getRelocationModel() == Reloc::PIC_)
246 Reserved.set(PPC::R30);
248 // Reserve Altivec registers when Altivec is unavailable.
249 if (!Subtarget.hasAltivec())
250 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
251 IE = PPC::VRRCRegClass.end(); I != IE; ++I)
257 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
258 MachineFunction &MF) const {
259 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
260 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
261 const unsigned DefaultSafety = 1;
263 switch (RC->getID()) {
266 case PPC::G8RC_NOX0RegClassID:
267 case PPC::GPRC_NOR0RegClassID:
268 case PPC::G8RCRegClassID:
269 case PPC::GPRCRegClassID: {
270 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
271 return 32 - FP - DefaultSafety;
273 case PPC::F8RCRegClassID:
274 case PPC::F4RCRegClassID:
275 case PPC::QFRCRegClassID:
276 case PPC::QSRCRegClassID:
277 case PPC::QBRCRegClassID:
278 case PPC::VRRCRegClassID:
279 case PPC::VFRCRegClassID:
280 case PPC::VSLRCRegClassID:
281 case PPC::VSHRCRegClassID:
282 return 32 - DefaultSafety;
283 case PPC::VSRCRegClassID:
284 case PPC::VSFRCRegClassID:
285 return 64 - DefaultSafety;
286 case PPC::CRRCRegClassID:
287 return 8 - DefaultSafety;
291 const TargetRegisterClass *
292 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
293 const MachineFunction &MF) const {
294 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
295 if (Subtarget.hasVSX()) {
296 // With VSX, we can inflate various sub-register classes to the full VSX
299 if (RC == &PPC::F8RCRegClass)
300 return &PPC::VSFRCRegClass;
301 else if (RC == &PPC::VRRCRegClass)
302 return &PPC::VSRCRegClass;
305 return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
308 //===----------------------------------------------------------------------===//
309 // Stack Frame Processing methods
310 //===----------------------------------------------------------------------===//
312 /// lowerDynamicAlloc - Generate the code for allocating an object in the
313 /// current frame. The sequence of code with be in the general form
315 /// addi R0, SP, \#frameSize ; get the address of the previous frame
316 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
317 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
319 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
320 // Get the instruction.
321 MachineInstr &MI = *II;
322 // Get the instruction's basic block.
323 MachineBasicBlock &MBB = *MI.getParent();
324 // Get the basic block's function.
325 MachineFunction &MF = *MBB.getParent();
326 // Get the frame info.
327 MachineFrameInfo *MFI = MF.getFrameInfo();
328 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
329 // Get the instruction info.
330 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
331 // Determine whether 64-bit pointers are used.
332 bool LP64 = TM.isPPC64();
333 DebugLoc dl = MI.getDebugLoc();
335 // Get the maximum call stack size.
336 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
337 // Get the total frame size.
338 unsigned FrameSize = MFI->getStackSize();
340 // Get stack alignments.
341 unsigned TargetAlign = Subtarget.getFrameLowering()->getStackAlignment();
342 unsigned MaxAlign = MFI->getMaxAlignment();
343 assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
344 "Maximum call-frame size not sufficiently aligned");
346 // Determine the previous frame's address. If FrameSize can't be
347 // represented as 16 bits or we need special alignment, then we load the
348 // previous frame's address from 0(SP). Why not do an addis of the hi?
349 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
350 // Constructing the constant and adding would take 3 instructions.
351 // Fortunately, a frame greater than 32K is rare.
352 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
353 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
354 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
356 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
357 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
361 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
365 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
370 bool KillNegSizeReg = MI.getOperand(1).isKill();
371 unsigned NegSizeReg = MI.getOperand(1).getReg();
373 // Grow the stack and update the stack pointer link, then determine the
374 // address of new allocated space.
376 if (MaxAlign > TargetAlign) {
377 unsigned UnalNegSizeReg = NegSizeReg;
378 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
380 // Unfortunately, there is no andi, only andi., and we can't insert that
381 // here because we might clobber cr0 while it is live.
382 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
383 .addImm(~(MaxAlign-1));
385 unsigned NegSizeReg1 = NegSizeReg;
386 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
387 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
388 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
389 .addReg(NegSizeReg1, RegState::Kill);
390 KillNegSizeReg = true;
393 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
394 .addReg(Reg, RegState::Kill)
396 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
397 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
399 .addImm(maxCallFrameSize);
401 if (MaxAlign > TargetAlign) {
402 unsigned UnalNegSizeReg = NegSizeReg;
403 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
405 // Unfortunately, there is no andi, only andi., and we can't insert that
406 // here because we might clobber cr0 while it is live.
407 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
408 .addImm(~(MaxAlign-1));
410 unsigned NegSizeReg1 = NegSizeReg;
411 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
412 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
413 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
414 .addReg(NegSizeReg1, RegState::Kill);
415 KillNegSizeReg = true;
418 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
419 .addReg(Reg, RegState::Kill)
421 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
422 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
424 .addImm(maxCallFrameSize);
427 // Discard the DYNALLOC instruction.
431 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
432 /// reserving a whole register (R0), we scrounge for one here. This generates
435 /// mfcr rA ; Move the conditional register into GPR rA.
436 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
437 /// stw rA, FI ; Store rA to the frame.
439 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
440 unsigned FrameIndex) const {
441 // Get the instruction.
442 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
443 // Get the instruction's basic block.
444 MachineBasicBlock &MBB = *MI.getParent();
445 MachineFunction &MF = *MBB.getParent();
446 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
447 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
448 DebugLoc dl = MI.getDebugLoc();
450 bool LP64 = TM.isPPC64();
451 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
452 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
454 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
455 unsigned SrcReg = MI.getOperand(0).getReg();
457 // We need to store the CR in the low 4-bits of the saved value. First, issue
458 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
459 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
460 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
462 // If the saved register wasn't CR0, shift the bits left so that they are in
464 if (SrcReg != PPC::CR0) {
466 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
468 // rlwinm rA, rA, ShiftBits, 0, 31.
469 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
470 .addReg(Reg1, RegState::Kill)
471 .addImm(getEncodingValue(SrcReg) * 4)
476 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
477 .addReg(Reg, RegState::Kill),
480 // Discard the pseudo instruction.
484 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
485 unsigned FrameIndex) const {
486 // Get the instruction.
487 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
488 // Get the instruction's basic block.
489 MachineBasicBlock &MBB = *MI.getParent();
490 MachineFunction &MF = *MBB.getParent();
491 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
492 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
493 DebugLoc dl = MI.getDebugLoc();
495 bool LP64 = TM.isPPC64();
496 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
497 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
499 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
500 unsigned DestReg = MI.getOperand(0).getReg();
501 assert(MI.definesRegister(DestReg) &&
502 "RESTORE_CR does not define its destination");
504 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
507 // If the reloaded register isn't CR0, shift the bits right so that they are
508 // in the right CR's slot.
509 if (DestReg != PPC::CR0) {
511 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
513 unsigned ShiftBits = getEncodingValue(DestReg)*4;
514 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
515 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
516 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
520 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
521 .addReg(Reg, RegState::Kill);
523 // Discard the pseudo instruction.
527 static unsigned getCRFromCRBit(unsigned SrcReg) {
529 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
530 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
532 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
533 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
535 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
536 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
538 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
539 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
541 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
542 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
544 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
545 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
547 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
548 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
550 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
551 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
554 assert(Reg != 0 && "Invalid CR bit register");
558 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
559 unsigned FrameIndex) const {
560 // Get the instruction.
561 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
562 // Get the instruction's basic block.
563 MachineBasicBlock &MBB = *MI.getParent();
564 MachineFunction &MF = *MBB.getParent();
565 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
566 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
567 DebugLoc dl = MI.getDebugLoc();
569 bool LP64 = TM.isPPC64();
570 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
571 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
573 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
574 unsigned SrcReg = MI.getOperand(0).getReg();
576 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL),
577 getCRFromCRBit(SrcReg))
578 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
580 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
581 .addReg(getCRFromCRBit(SrcReg));
583 // If the saved register wasn't CR0LT, shift the bits left so that the bit to
584 // store is the first one. Mask all but that bit.
586 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
588 // rlwinm rA, rA, ShiftBits, 0, 0.
589 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
590 .addReg(Reg1, RegState::Kill)
591 .addImm(getEncodingValue(SrcReg))
592 .addImm(0).addImm(0);
594 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
595 .addReg(Reg, RegState::Kill),
598 // Discard the pseudo instruction.
602 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II,
603 unsigned FrameIndex) const {
604 // Get the instruction.
605 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
606 // Get the instruction's basic block.
607 MachineBasicBlock &MBB = *MI.getParent();
608 MachineFunction &MF = *MBB.getParent();
609 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
610 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
611 DebugLoc dl = MI.getDebugLoc();
613 bool LP64 = TM.isPPC64();
614 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
615 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
617 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
618 unsigned DestReg = MI.getOperand(0).getReg();
619 assert(MI.definesRegister(DestReg) &&
620 "RESTORE_CRBIT does not define its destination");
622 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
625 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
627 unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
628 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
629 .addReg(getCRFromCRBit(DestReg));
631 unsigned ShiftBits = getEncodingValue(DestReg);
632 // rlwimi r11, r10, 32-ShiftBits, ..., ...
633 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
634 .addReg(RegO, RegState::Kill).addReg(Reg, RegState::Kill)
635 .addImm(ShiftBits ? 32-ShiftBits : 0)
636 .addImm(ShiftBits).addImm(ShiftBits);
638 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
639 getCRFromCRBit(DestReg))
640 .addReg(RegO, RegState::Kill)
641 // Make sure we have a use dependency all the way through this
642 // sequence of instructions. We can't have the other bits in the CR
643 // modified in between the mfocrf and the mtocrf.
644 .addReg(getCRFromCRBit(DestReg), RegState::Implicit);
646 // Discard the pseudo instruction.
650 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
651 unsigned FrameIndex) const {
652 // Get the instruction.
653 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset>
654 // Get the instruction's basic block.
655 MachineBasicBlock &MBB = *MI.getParent();
656 MachineFunction &MF = *MBB.getParent();
657 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
658 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
659 DebugLoc dl = MI.getDebugLoc();
661 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
662 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
663 unsigned SrcReg = MI.getOperand(0).getReg();
665 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
666 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
668 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
669 .addReg(Reg, RegState::Kill),
672 // Discard the pseudo instruction.
676 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
677 unsigned FrameIndex) const {
678 // Get the instruction.
679 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
680 // Get the instruction's basic block.
681 MachineBasicBlock &MBB = *MI.getParent();
682 MachineFunction &MF = *MBB.getParent();
683 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
684 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
685 DebugLoc dl = MI.getDebugLoc();
687 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
688 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
689 unsigned DestReg = MI.getOperand(0).getReg();
690 assert(MI.definesRegister(DestReg) &&
691 "RESTORE_VRSAVE does not define its destination");
693 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
696 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
697 .addReg(Reg, RegState::Kill);
699 // Discard the pseudo instruction.
704 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
705 unsigned Reg, int &FrameIdx) const {
706 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
707 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
708 // ABI, return true to prevent allocating an additional frame slot.
709 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
710 // is arbitrary and will be subsequently ignored. For 32-bit, we have
711 // previously created the stack slot if needed, so return its FrameIdx.
712 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
716 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
717 FrameIdx = FI->getCRSpillFrameIndex();
724 // Figure out if the offset in the instruction must be a multiple of 4.
725 // This is true for instructions like "STD".
726 static bool usesIXAddr(const MachineInstr &MI) {
727 unsigned OpC = MI.getOpcode();
740 // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
741 static unsigned getOffsetONFromFION(const MachineInstr &MI,
742 unsigned FIOperandNum) {
743 // Take into account whether it's an add or mem instruction
744 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
745 if (MI.isInlineAsm())
746 OffsetOperandNo = FIOperandNum - 1;
747 else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
748 MI.getOpcode() == TargetOpcode::PATCHPOINT)
749 OffsetOperandNo = FIOperandNum + 1;
751 return OffsetOperandNo;
755 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
756 int SPAdj, unsigned FIOperandNum,
757 RegScavenger *RS) const {
758 assert(SPAdj == 0 && "Unexpected");
760 // Get the instruction.
761 MachineInstr &MI = *II;
762 // Get the instruction's basic block.
763 MachineBasicBlock &MBB = *MI.getParent();
764 // Get the basic block's function.
765 MachineFunction &MF = *MBB.getParent();
766 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
767 // Get the instruction info.
768 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
769 // Get the frame info.
770 MachineFrameInfo *MFI = MF.getFrameInfo();
771 DebugLoc dl = MI.getDebugLoc();
773 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
775 // Get the frame index.
776 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
778 // Get the frame pointer save index. Users of this index are primarily
779 // DYNALLOC instructions.
780 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
781 int FPSI = FI->getFramePointerSaveIndex();
782 // Get the instruction opcode.
783 unsigned OpC = MI.getOpcode();
785 // Special case for dynamic alloca.
786 if (FPSI && FrameIndex == FPSI &&
787 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
788 lowerDynamicAlloc(II);
792 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
793 if (OpC == PPC::SPILL_CR) {
794 lowerCRSpilling(II, FrameIndex);
796 } else if (OpC == PPC::RESTORE_CR) {
797 lowerCRRestore(II, FrameIndex);
799 } else if (OpC == PPC::SPILL_CRBIT) {
800 lowerCRBitSpilling(II, FrameIndex);
802 } else if (OpC == PPC::RESTORE_CRBIT) {
803 lowerCRBitRestore(II, FrameIndex);
805 } else if (OpC == PPC::SPILL_VRSAVE) {
806 lowerVRSAVESpilling(II, FrameIndex);
808 } else if (OpC == PPC::RESTORE_VRSAVE) {
809 lowerVRSAVERestore(II, FrameIndex);
813 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
814 MI.getOperand(FIOperandNum).ChangeToRegister(
815 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
817 // Figure out if the offset in the instruction is shifted right two bits.
818 bool isIXAddr = usesIXAddr(MI);
820 // If the instruction is not present in ImmToIdxMap, then it has no immediate
821 // form (and must be r+r).
822 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
823 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
825 // Now add the frame object offset to the offset from r1.
826 int Offset = MFI->getObjectOffset(FrameIndex);
827 Offset += MI.getOperand(OffsetOperandNo).getImm();
829 // If we're not using a Frame Pointer that has been set to the value of the
830 // SP before having the stack size subtracted from it, then add the stack size
831 // to Offset to get the correct offset.
832 // Naked functions have stack size 0, although getStackSize may not reflect that
833 // because we didn't call all the pieces that compute it for naked functions.
834 if (!MF.getFunction()->hasFnAttribute(Attribute::Naked)) {
835 if (!(hasBasePointer(MF) && FrameIndex < 0))
836 Offset += MFI->getStackSize();
839 // If we can, encode the offset directly into the instruction. If this is a
840 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
841 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
842 // clear can be encoded. This is extremely uncommon, because normally you
843 // only "std" to a stack slot that is at least 4-byte aligned, but it can
844 // happen in invalid code.
845 assert(OpC != PPC::DBG_VALUE &&
846 "This should be handled in a target-independent way");
847 if (!noImmForm && ((isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) ||
848 OpC == TargetOpcode::STACKMAP ||
849 OpC == TargetOpcode::PATCHPOINT)) {
850 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
854 // The offset doesn't fit into a single register, scavenge one to build the
857 bool is64Bit = TM.isPPC64();
858 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
859 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
860 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
861 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
862 SReg = MF.getRegInfo().createVirtualRegister(RC);
864 // Insert a set of rA with the full offset value before the ld, st, or add
865 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
866 .addImm(Offset >> 16);
867 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
868 .addReg(SRegHi, RegState::Kill)
871 // Convert into indexed form of the instruction:
873 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
874 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
875 unsigned OperandBase;
879 else if (OpC != TargetOpcode::INLINEASM) {
880 assert(ImmToIdxMap.count(OpC) &&
881 "No indexed form of load or store available!");
882 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
883 MI.setDesc(TII.get(NewOpcode));
886 OperandBase = OffsetOperandNo;
889 unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
890 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
891 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
894 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
895 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
896 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
899 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
901 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
904 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
905 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
906 if (!hasBasePointer(MF))
907 return getFrameRegister(MF);
912 if (Subtarget.isSVR4ABI() &&
913 TM.getRelocationModel() == Reloc::PIC_)
919 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
920 if (!EnableBasePointer)
922 if (AlwaysBasePointer)
925 // If we need to realign the stack, then the stack pointer can no longer
926 // serve as an offset into the caller's stack space. As a result, we need a
928 return needsStackRealignment(MF);
931 bool PPCRegisterInfo::canRealignStack(const MachineFunction &MF) const {
932 if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
938 bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
939 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
940 const MachineFrameInfo *MFI = MF.getFrameInfo();
941 const Function *F = MF.getFunction();
942 unsigned StackAlign = Subtarget.getFrameLowering()->getStackAlignment();
943 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
944 F->hasFnAttribute(Attribute::StackAlignment));
946 return requiresRealignment && canRealignStack(MF);
949 /// Returns true if the instruction's frame index
950 /// reference would be better served by a base register other than FP
951 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
952 /// references it should create new base registers for.
953 bool PPCRegisterInfo::
954 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
955 assert(Offset < 0 && "Local offset must be negative");
957 // It's the load/store FI references that cause issues, as it can be difficult
958 // to materialize the offset if it won't fit in the literal field. Estimate
959 // based on the size of the local frame and some conservative assumptions
960 // about the rest of the stack frame (note, this is pre-regalloc, so
961 // we don't know everything for certain yet) whether this offset is likely
962 // to be out of range of the immediate. Return true if so.
964 // We only generate virtual base registers for loads and stores that have
965 // an r+i form. Return false for everything else.
966 unsigned OpC = MI->getOpcode();
967 if (!ImmToIdxMap.count(OpC))
970 // Don't generate a new virtual base register just to add zero to it.
971 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
972 MI->getOperand(2).getImm() == 0)
975 MachineBasicBlock &MBB = *MI->getParent();
976 MachineFunction &MF = *MBB.getParent();
977 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
978 const PPCFrameLowering *PPCFI =
979 static_cast<const PPCFrameLowering *>(Subtarget.getFrameLowering());
981 PPCFI->determineFrameLayout(MF, false, true);
983 // If we likely don't need a stack frame, then we probably don't need a
984 // virtual base register either.
988 // Estimate an offset from the stack pointer.
989 // The incoming offset is relating to the SP at the start of the function,
990 // but when we access the local it'll be relative to the SP after local
991 // allocation, so adjust our SP-relative offset by that allocation size.
994 // The frame pointer will point to the end of the stack, so estimate the
995 // offset as the difference between the object offset and the FP location.
996 return !isFrameOffsetLegal(MI, Offset);
999 /// Insert defining instruction(s) for BaseReg to
1000 /// be a pointer to FrameIdx at the beginning of the basic block.
1001 void PPCRegisterInfo::
1002 materializeFrameBaseRegister(MachineBasicBlock *MBB,
1003 unsigned BaseReg, int FrameIdx,
1004 int64_t Offset) const {
1005 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
1007 MachineBasicBlock::iterator Ins = MBB->begin();
1008 DebugLoc DL; // Defaults to "unknown"
1009 if (Ins != MBB->end())
1010 DL = Ins->getDebugLoc();
1012 const MachineFunction &MF = *MBB->getParent();
1013 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1014 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1015 const MCInstrDesc &MCID = TII.get(ADDriOpc);
1016 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1017 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
1019 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
1020 .addFrameIndex(FrameIdx).addImm(Offset);
1023 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
1024 int64_t Offset) const {
1025 unsigned FIOperandNum = 0;
1026 while (!MI.getOperand(FIOperandNum).isFI()) {
1028 assert(FIOperandNum < MI.getNumOperands() &&
1029 "Instr doesn't have FrameIndex operand!");
1032 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
1033 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1034 Offset += MI.getOperand(OffsetOperandNo).getImm();
1035 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1037 MachineBasicBlock &MBB = *MI.getParent();
1038 MachineFunction &MF = *MBB.getParent();
1039 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1040 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1041 const MCInstrDesc &MCID = MI.getDesc();
1042 MachineRegisterInfo &MRI = MF.getRegInfo();
1043 MRI.constrainRegClass(BaseReg,
1044 TII.getRegClass(MCID, FIOperandNum, this, MF));
1047 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1048 int64_t Offset) const {
1049 unsigned FIOperandNum = 0;
1050 while (!MI->getOperand(FIOperandNum).isFI()) {
1052 assert(FIOperandNum < MI->getNumOperands() &&
1053 "Instr doesn't have FrameIndex operand!");
1056 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
1057 Offset += MI->getOperand(OffsetOperandNo).getImm();
1059 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
1060 MI->getOpcode() == TargetOpcode::STACKMAP ||
1061 MI->getOpcode() == TargetOpcode::PATCHPOINT ||
1062 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0));