1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "reginfo"
16 #include "PPCRegisterInfo.h"
18 #include "PPCFrameLowering.h"
19 #include "PPCInstrBuilder.h"
20 #include "PPCMachineFunctionInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/RegisterScavenging.h"
30 #include "llvm/CodeGen/ValueTypes.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetFrameLowering.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
46 #define GET_REGINFO_TARGET_DESC
47 #include "PPCGenRegisterInfo.inc"
51 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
52 const TargetInstrInfo &tii)
53 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
55 ST.isPPC64() ? 0 : 1),
56 Subtarget(ST), TII(tii) {
57 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
58 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
59 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
60 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
61 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
62 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
63 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
64 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
67 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
68 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
69 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
70 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
71 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
74 /// getPointerRegClass - Return the register class to use to hold pointers.
75 /// This is used for addressing modes.
76 const TargetRegisterClass *
77 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
80 if (Subtarget.isPPC64())
81 return &PPC::G8RC_NOX0RegClass;
82 return &PPC::GPRC_NOR0RegClass;
85 if (Subtarget.isPPC64())
86 return &PPC::G8RCRegClass;
87 return &PPC::GPRCRegClass;
91 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
92 if (Subtarget.isDarwinABI())
93 return Subtarget.isPPC64() ? CSR_Darwin64_SaveList :
94 CSR_Darwin32_SaveList;
96 return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList;
100 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
101 if (Subtarget.isDarwinABI())
102 return Subtarget.isPPC64() ? CSR_Darwin64_RegMask :
103 CSR_Darwin32_RegMask;
105 return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask;
108 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
109 BitVector Reserved(getNumRegs());
110 const PPCFrameLowering *PPCFI =
111 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
113 // The ZERO register is not really a register, but the representation of r0
114 // when used in instructions that treat r0 as the constant 0.
115 Reserved.set(PPC::ZERO);
117 // The FP register is also not really a register, but is the representation
118 // of the frame pointer register used by ISD::FRAMEADDR.
119 Reserved.set(PPC::FP);
120 Reserved.set(PPC::FP8);
122 Reserved.set(PPC::R0);
123 Reserved.set(PPC::R1);
124 Reserved.set(PPC::LR);
125 Reserved.set(PPC::LR8);
126 Reserved.set(PPC::RM);
128 // The SVR4 ABI reserves r2 and r13
129 if (Subtarget.isSVR4ABI()) {
130 Reserved.set(PPC::R2); // System-reserved register
131 Reserved.set(PPC::R13); // Small Data Area pointer register
134 // On PPC64, r13 is the thread pointer. Never allocate this register.
135 if (Subtarget.isPPC64()) {
136 Reserved.set(PPC::R13);
138 Reserved.set(PPC::X0);
139 Reserved.set(PPC::X1);
140 Reserved.set(PPC::X13);
142 if (PPCFI->needsFP(MF))
143 Reserved.set(PPC::X31);
145 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
146 if (Subtarget.isSVR4ABI()) {
147 Reserved.set(PPC::X2);
151 if (PPCFI->needsFP(MF))
152 Reserved.set(PPC::R31);
158 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
159 MachineFunction &MF) const {
160 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
161 const unsigned DefaultSafety = 1;
163 switch (RC->getID()) {
166 case PPC::G8RC_NOX0RegClassID:
167 case PPC::GPRC_NOR0RegClassID:
168 case PPC::G8RCRegClassID:
169 case PPC::GPRCRegClassID: {
170 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
171 return 32 - FP - DefaultSafety;
173 case PPC::F8RCRegClassID:
174 case PPC::F4RCRegClassID:
175 case PPC::VRRCRegClassID:
176 return 32 - DefaultSafety;
177 case PPC::CRRCRegClassID:
178 return 8 - DefaultSafety;
182 //===----------------------------------------------------------------------===//
183 // Stack Frame Processing methods
184 //===----------------------------------------------------------------------===//
186 /// lowerDynamicAlloc - Generate the code for allocating an object in the
187 /// current frame. The sequence of code with be in the general form
189 /// addi R0, SP, \#frameSize ; get the address of the previous frame
190 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
191 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
193 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
194 int SPAdj, RegScavenger *RS) const {
195 // Get the instruction.
196 MachineInstr &MI = *II;
197 // Get the instruction's basic block.
198 MachineBasicBlock &MBB = *MI.getParent();
199 // Get the basic block's function.
200 MachineFunction &MF = *MBB.getParent();
201 // Get the frame info.
202 MachineFrameInfo *MFI = MF.getFrameInfo();
203 // Determine whether 64-bit pointers are used.
204 bool LP64 = Subtarget.isPPC64();
205 DebugLoc dl = MI.getDebugLoc();
207 // Get the maximum call stack size.
208 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
209 // Get the total frame size.
210 unsigned FrameSize = MFI->getStackSize();
212 // Get stack alignments.
213 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
214 unsigned MaxAlign = MFI->getMaxAlignment();
215 if (MaxAlign > TargetAlign)
216 report_fatal_error("Dynamic alloca with large aligns not supported");
218 // Determine the previous frame's address. If FrameSize can't be
219 // represented as 16 bits or we need special alignment, then we load the
220 // previous frame's address from 0(SP). Why not do an addis of the hi?
221 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
222 // Constructing the constant and adding would take 3 instructions.
223 // Fortunately, a frame greater than 32K is rare.
224 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
225 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
226 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
228 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
229 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
233 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
237 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
242 // Grow the stack and update the stack pointer link, then determine the
243 // address of new allocated space.
245 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
246 .addReg(Reg, RegState::Kill)
248 .addReg(MI.getOperand(1).getReg());
249 if (!MI.getOperand(1).isKill())
250 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
252 .addImm(maxCallFrameSize);
254 // Implicitly kill the register.
255 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
257 .addImm(maxCallFrameSize)
258 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
260 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
261 .addReg(Reg, RegState::Kill)
263 .addReg(MI.getOperand(1).getReg());
265 if (!MI.getOperand(1).isKill())
266 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
268 .addImm(maxCallFrameSize);
270 // Implicitly kill the register.
271 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
273 .addImm(maxCallFrameSize)
274 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
277 // Discard the DYNALLOC instruction.
281 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
282 /// reserving a whole register (R0), we scrounge for one here. This generates
285 /// mfcr rA ; Move the conditional register into GPR rA.
286 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
287 /// stw rA, FI ; Store rA to the frame.
289 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
290 unsigned FrameIndex, int SPAdj,
291 RegScavenger *RS) const {
292 // Get the instruction.
293 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
294 // Get the instruction's basic block.
295 MachineBasicBlock &MBB = *MI.getParent();
296 DebugLoc dl = MI.getDebugLoc();
298 // FIXME: Once LLVM supports creating virtual registers here, or the register
299 // scavenger can return multiple registers, stop using reserved registers
304 bool LP64 = Subtarget.isPPC64();
305 unsigned Reg = LP64 ? PPC::X0 : PPC::R0;
306 unsigned SrcReg = MI.getOperand(0).getReg();
308 // We need to store the CR in the low 4-bits of the saved value. First, issue
309 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
310 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg)
311 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
313 // If the saved register wasn't CR0, shift the bits left so that they are in
315 if (SrcReg != PPC::CR0)
316 // rlwinm rA, rA, ShiftBits, 0, 31.
317 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
318 .addReg(Reg, RegState::Kill)
319 .addImm(getPPCRegisterNumbering(SrcReg) * 4)
323 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
324 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
327 // Discard the pseudo instruction.
331 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
332 unsigned FrameIndex, int SPAdj,
333 RegScavenger *RS) const {
334 // Get the instruction.
335 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
336 // Get the instruction's basic block.
337 MachineBasicBlock &MBB = *MI.getParent();
338 DebugLoc dl = MI.getDebugLoc();
340 // FIXME: Once LLVM supports creating virtual registers here, or the register
341 // scavenger can return multiple registers, stop using reserved registers
346 bool LP64 = Subtarget.isPPC64();
347 unsigned Reg = LP64 ? PPC::X0 : PPC::R0;
348 unsigned DestReg = MI.getOperand(0).getReg();
349 assert(MI.definesRegister(DestReg) &&
350 "RESTORE_CR does not define its destination");
352 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
355 // If the reloaded register isn't CR0, shift the bits right so that they are
356 // in the right CR's slot.
357 if (DestReg != PPC::CR0) {
358 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
359 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
360 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
361 .addReg(Reg).addImm(32-ShiftBits).addImm(0)
365 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg)
368 // Discard the pseudo instruction.
373 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
374 unsigned Reg, int &FrameIdx) const {
376 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
377 // ABI, return true to prevent allocating an additional frame slot.
378 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
379 // is arbitrary and will be subsequently ignored. For 32-bit, we have
380 // previously created the stack slot if needed, so return its FrameIdx.
381 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
382 if (Subtarget.isPPC64())
385 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
386 FrameIdx = FI->getCRSpillFrameIndex();
394 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
395 int SPAdj, unsigned FIOperandNum,
396 RegScavenger *RS) const {
397 assert(SPAdj == 0 && "Unexpected");
399 // Get the instruction.
400 MachineInstr &MI = *II;
401 // Get the instruction's basic block.
402 MachineBasicBlock &MBB = *MI.getParent();
403 // Get the basic block's function.
404 MachineFunction &MF = *MBB.getParent();
405 // Get the frame info.
406 MachineFrameInfo *MFI = MF.getFrameInfo();
407 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
408 DebugLoc dl = MI.getDebugLoc();
410 // Take into account whether it's an add or mem instruction
411 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
412 if (MI.isInlineAsm())
413 OffsetOperandNo = FIOperandNum-1;
415 // Get the frame index.
416 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
418 // Get the frame pointer save index. Users of this index are primarily
419 // DYNALLOC instructions.
420 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
421 int FPSI = FI->getFramePointerSaveIndex();
422 // Get the instruction opcode.
423 unsigned OpC = MI.getOpcode();
425 // Special case for dynamic alloca.
426 if (FPSI && FrameIndex == FPSI &&
427 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
428 lowerDynamicAlloc(II, SPAdj, RS);
432 // Special case for pseudo-ops SPILL_CR and RESTORE_CR.
433 if (OpC == PPC::SPILL_CR) {
434 lowerCRSpilling(II, FrameIndex, SPAdj, RS);
436 } else if (OpC == PPC::RESTORE_CR) {
437 lowerCRRestore(II, FrameIndex, SPAdj, RS);
441 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
443 bool is64Bit = Subtarget.isPPC64();
444 MI.getOperand(FIOperandNum).ChangeToRegister(TFI->hasFP(MF) ?
445 (is64Bit ? PPC::X31 : PPC::R31) :
446 (is64Bit ? PPC::X1 : PPC::R1),
449 // Figure out if the offset in the instruction is shifted right two bits. This
450 // is true for instructions like "STD", which the machine implicitly adds two
452 bool isIXAddr = false;
462 bool noImmForm = false;
480 // Now add the frame object offset to the offset from r1.
481 int Offset = MFI->getObjectOffset(FrameIndex);
483 Offset += MI.getOperand(OffsetOperandNo).getImm();
485 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
487 // If we're not using a Frame Pointer that has been set to the value of the
488 // SP before having the stack size subtracted from it, then add the stack size
489 // to Offset to get the correct offset.
490 // Naked functions have stack size 0, although getStackSize may not reflect that
491 // because we didn't call all the pieces that compute it for naked functions.
492 if (!MF.getFunction()->getAttributes().
493 hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked))
494 Offset += MFI->getStackSize();
496 // If we can, encode the offset directly into the instruction. If this is a
497 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
498 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
499 // clear can be encoded. This is extremely uncommon, because normally you
500 // only "std" to a stack slot that is at least 4-byte aligned, but it can
501 // happen in invalid code.
502 if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
504 isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) {
506 Offset >>= 2; // The actual encoded value has the low two bits zero.
507 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
511 // The offset doesn't fit into a single register, scavenge one to build the
514 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
515 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
516 unsigned SReg = MF.getRegInfo().createVirtualRegister(is64Bit ? G8RC : GPRC);
518 // Insert a set of rA with the full offset value before the ld, st, or add
519 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg)
520 .addImm(Offset >> 16);
521 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
522 .addReg(SReg, RegState::Kill)
525 // Convert into indexed form of the instruction:
527 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
528 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
529 unsigned OperandBase;
533 else if (OpC != TargetOpcode::INLINEASM) {
534 assert(ImmToIdxMap.count(OpC) &&
535 "No indexed form of load or store available!");
536 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
537 MI.setDesc(TII.get(NewOpcode));
540 OperandBase = OffsetOperandNo;
543 unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
544 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
545 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
548 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
549 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
551 if (!Subtarget.isPPC64())
552 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
554 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
557 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
558 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
561 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
562 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;