1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PPCInstrBuilder.h"
17 #include "PPCRegisterInfo.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/ADT/STLExtras.h"
35 PPCRegisterInfo::PPCRegisterInfo()
36 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
37 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
38 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
39 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
40 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
41 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
42 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
43 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
44 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
48 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator MI,
50 unsigned SrcReg, int FrameIdx,
51 const TargetRegisterClass *RC) const {
52 if (SrcReg == PPC::LR) {
53 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
54 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
55 } else if (RC == PPC::CRRCRegisterClass) {
56 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
57 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
58 } else if (RC == PPC::GPRCRegisterClass) {
59 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
60 } else if (RC == PPC::G8RCRegisterClass) {
61 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx);
62 } else if (RC == PPC::F8RCRegisterClass) {
63 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
64 } else if (RC == PPC::F4RCRegisterClass) {
65 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
67 assert(0 && "Unknown regclass!");
73 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
74 MachineBasicBlock::iterator MI,
75 unsigned DestReg, int FrameIdx,
76 const TargetRegisterClass *RC) const {
77 if (DestReg == PPC::LR) {
78 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
79 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
80 } else if (RC == PPC::CRRCRegisterClass) {
81 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
82 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
83 } else if (RC == PPC::GPRCRegisterClass) {
84 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
85 } else if (RC == PPC::G8RCRegisterClass) {
86 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
87 } else if (RC == PPC::F8RCRegisterClass) {
88 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
89 } else if (RC == PPC::F4RCRegisterClass) {
90 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
92 assert(0 && "Unknown regclass!");
97 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
98 MachineBasicBlock::iterator MI,
99 unsigned DestReg, unsigned SrcReg,
100 const TargetRegisterClass *RC) const {
103 if (RC == PPC::GPRCRegisterClass) {
104 BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
105 } else if (RC == PPC::G8RCRegisterClass) {
106 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
107 } else if (RC == PPC::F4RCRegisterClass) {
108 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
109 } else if (RC == PPC::F8RCRegisterClass) {
110 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
111 } else if (RC == PPC::CRRCRegisterClass) {
112 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
114 std::cerr << "Attempt to copy register that is not GPR or FPR";
119 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
120 /// copy instructions, turning them into load/store instructions.
121 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
123 int FrameIndex) const {
124 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
125 // it takes more than one instruction to store it.
126 unsigned Opc = MI->getOpcode();
128 if ((Opc == PPC::OR4 &&
129 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
130 if (OpNum == 0) { // move -> store
131 unsigned InReg = MI->getOperand(1).getReg();
132 return addFrameReference(BuildMI(PPC::STW,
133 3).addReg(InReg), FrameIndex);
134 } else { // move -> load
135 unsigned OutReg = MI->getOperand(0).getReg();
136 return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
138 } else if ((Opc == PPC::OR8 &&
139 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
140 if (OpNum == 0) { // move -> store
141 unsigned InReg = MI->getOperand(1).getReg();
142 return addFrameReference(BuildMI(PPC::STD,
143 3).addReg(InReg), FrameIndex);
144 } else { // move -> load
145 unsigned OutReg = MI->getOperand(0).getReg();
146 return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex);
148 } else if (Opc == PPC::FMRD) {
149 if (OpNum == 0) { // move -> store
150 unsigned InReg = MI->getOperand(1).getReg();
151 return addFrameReference(BuildMI(PPC::STFD,
152 3).addReg(InReg), FrameIndex);
153 } else { // move -> load
154 unsigned OutReg = MI->getOperand(0).getReg();
155 return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex);
157 } else if (Opc == PPC::FMRS) {
158 if (OpNum == 0) { // move -> store
159 unsigned InReg = MI->getOperand(1).getReg();
160 return addFrameReference(BuildMI(PPC::STFS,
161 3).addReg(InReg), FrameIndex);
162 } else { // move -> load
163 unsigned OutReg = MI->getOperand(0).getReg();
164 return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex);
170 //===----------------------------------------------------------------------===//
171 // Stack Frame Processing methods
172 //===----------------------------------------------------------------------===//
174 // hasFP - Return true if the specified function should have a dedicated frame
175 // pointer register. This is true if the function has variable sized allocas or
176 // if frame pointer elimination is disabled.
178 static bool hasFP(MachineFunction &MF) {
179 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
182 void PPCRegisterInfo::
183 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
184 MachineBasicBlock::iterator I) const {
186 // If we have a frame pointer, convert as follows:
187 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
188 // ADJCALLSTACKUP -> addi, r1, r1, amount
189 MachineInstr *Old = I;
190 unsigned Amount = Old->getOperand(0).getImmedValue();
192 // We need to keep the stack aligned properly. To do this, we round the
193 // amount of space needed for the outgoing arguments up to the next
194 // alignment boundary.
195 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
196 Amount = (Amount+Align-1)/Align*Align;
198 // Replace the pseudo instruction with a new instruction...
199 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
200 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(-Amount);
202 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
203 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(Amount);
211 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
213 MachineInstr &MI = *II;
214 MachineBasicBlock &MBB = *MI.getParent();
215 MachineFunction &MF = *MBB.getParent();
217 while (!MI.getOperand(i).isFrameIndex()) {
219 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
222 int FrameIndex = MI.getOperand(i).getFrameIndex();
224 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
225 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
227 // Take into account whether it's an add or mem instruction
228 unsigned OffIdx = (i == 2) ? 1 : 2;
230 // Now add the frame object offset to the offset from r1.
231 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
232 MI.getOperand(OffIdx).getImmedValue();
234 // If we're not using a Frame Pointer that has been set to the value of the
235 // SP before having the stack size subtracted from it, then add the stack size
236 // to Offset to get the correct offset.
237 Offset += MF.getFrameInfo()->getStackSize();
239 if (Offset > 32767 || Offset < -32768) {
240 // Insert a set of r0 with the full offset value before the ld, st, or add
241 MachineBasicBlock *MBB = MI.getParent();
242 BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16);
243 BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset);
245 // convert into indexed form of the instruction
246 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
247 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
248 assert(ImmToIdxMap.count(MI.getOpcode()) &&
249 "No indexed form of load or store available!");
250 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
251 MI.setOpcode(NewOpcode);
252 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
253 MI.SetMachineOperandReg(2, PPC::R0);
255 switch (MI.getOpcode()) {
260 assert((Offset & 3) == 0 && "Invalid frame offset!");
261 Offset >>= 2; // The actual encoded value has the low two bits zero.
264 MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
270 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
271 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
272 MachineBasicBlock::iterator MBBI = MBB.begin();
273 MachineFrameInfo *MFI = MF.getFrameInfo();
275 // Get the number of bytes to allocate from the FrameInfo
276 unsigned NumBytes = MFI->getStackSize();
278 // Get the alignments provided by the target, and the maximum alignment
279 // (if any) of the fixed frame objects.
280 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
281 unsigned MaxAlign = MFI->getMaxAlignment();
283 // If we have calls, we cannot use the red zone to store callee save registers
284 // and we must set up a stack frame, so calculate the necessary size here.
285 if (MFI->hasCalls()) {
286 // We reserve argument space for call sites in the function immediately on
287 // entry to the current function. This eliminates the need for add/sub
288 // brackets around call sites.
289 NumBytes += MFI->getMaxCallFrameSize();
292 // If we are a leaf function, and use up to 224 bytes of stack space,
293 // and don't have a frame pointer, then we do not need to adjust the stack
294 // pointer (we fit in the Red Zone).
295 if ((NumBytes == 0) || (NumBytes <= 224 && !hasFP(MF) && !MFI->hasCalls() &&
296 MaxAlign <= TargetAlign)) {
297 MFI->setStackSize(0);
301 // Add the size of R1 to NumBytes size for the store of R1 to the bottom
302 // of the stack and round the size to a multiple of the alignment.
303 unsigned Align = std::max(TargetAlign, MaxAlign);
304 unsigned GPRSize = 4;
305 unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize;
306 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
308 // Update frame info to pretend that this is part of the stack...
309 MFI->setStackSize(NumBytes);
311 // Adjust stack pointer: r1 -= numbytes.
312 if (NumBytes <= 32768) {
313 BuildMI(MBB, MBBI, PPC::STWU, 3)
314 .addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
316 int NegNumbytes = -NumBytes;
317 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
318 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0)
319 .addReg(PPC::R0).addImm(NegNumbytes & 0xFFFF);
320 BuildMI(MBB, MBBI, PPC::STWUX, 3)
321 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
324 // If there is a preferred stack alignment, align R1 now
325 // FIXME: If this ever matters, this could be made more efficient by folding
326 // this into the code above, so that we don't issue two store+update
328 if (MaxAlign > TargetAlign) {
329 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!");
330 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
331 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
332 BuildMI(MBB, MBBI, PPC::SUBFIC, 2,PPC::R0).addReg(PPC::R0).addImm(MaxAlign);
333 BuildMI(MBB, MBBI, PPC::STWUX, 3)
334 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
337 // If there is a frame pointer, copy R1 (SP) into R31 (FP)
339 BuildMI(MBB, MBBI, PPC::STW, 3)
340 .addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
341 BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
345 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
346 MachineBasicBlock &MBB) const {
347 MachineBasicBlock::iterator MBBI = prior(MBB.end());
348 assert(MBBI->getOpcode() == PPC::BLR &&
349 "Can only insert epilog into returning blocks");
351 // Get the number of bytes allocated from the FrameInfo.
352 unsigned NumBytes = MF.getFrameInfo()->getStackSize();
353 unsigned GPRSize = 4;
356 // If this function has a frame pointer, load the saved stack pointer from
359 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
360 .addSImm(GPRSize).addReg(PPC::R31);
363 // The loaded (or persistent) stack pointer value is offseted by the 'stwu'
364 // on entry to the function. Add this offset back now.
365 if (NumBytes < 32768) {
366 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
367 .addReg(PPC::R1).addSImm(NumBytes);
369 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NumBytes >> 16);
370 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0)
371 .addReg(PPC::R0).addImm(NumBytes & 0xFFFF);
372 BuildMI(MBB, MBBI, PPC::ADD4, 2, PPC::R1)
373 .addReg(PPC::R0).addReg(PPC::R1);
378 #include "PPCGenRegisterInfo.inc"