1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PPCInstrBuilder.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCRegisterInfo.h"
19 #include "PPCFrameInfo.h"
20 #include "PPCSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Type.h"
23 #include "llvm/CodeGen/ValueTypes.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineDebugInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/Target/TargetFrameInfo.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/ADT/STLExtras.h"
41 /// getRegisterNumbering - Given the enum value for some register, e.g.
42 /// PPC::F14, return the number that it corresponds to (e.g. 14).
43 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
46 case R0 : case X0 : case F0 : case V0 : case CR0: return 0;
47 case R1 : case X1 : case F1 : case V1 : case CR1: return 1;
48 case R2 : case X2 : case F2 : case V2 : case CR2: return 2;
49 case R3 : case X3 : case F3 : case V3 : case CR3: return 3;
50 case R4 : case X4 : case F4 : case V4 : case CR4: return 4;
51 case R5 : case X5 : case F5 : case V5 : case CR5: return 5;
52 case R6 : case X6 : case F6 : case V6 : case CR6: return 6;
53 case R7 : case X7 : case F7 : case V7 : case CR7: return 7;
54 case R8 : case X8 : case F8 : case V8 : return 8;
55 case R9 : case X9 : case F9 : case V9 : return 9;
56 case R10: case X10: case F10: case V10: return 10;
57 case R11: case X11: case F11: case V11: return 11;
58 case R12: case X12: case F12: case V12: return 12;
59 case R13: case X13: case F13: case V13: return 13;
60 case R14: case X14: case F14: case V14: return 14;
61 case R15: case X15: case F15: case V15: return 15;
62 case R16: case X16: case F16: case V16: return 16;
63 case R17: case X17: case F17: case V17: return 17;
64 case R18: case X18: case F18: case V18: return 18;
65 case R19: case X19: case F19: case V19: return 19;
66 case R20: case X20: case F20: case V20: return 20;
67 case R21: case X21: case F21: case V21: return 21;
68 case R22: case X22: case F22: case V22: return 22;
69 case R23: case X23: case F23: case V23: return 23;
70 case R24: case X24: case F24: case V24: return 24;
71 case R25: case X25: case F25: case V25: return 25;
72 case R26: case X26: case F26: case V26: return 26;
73 case R27: case X27: case F27: case V27: return 27;
74 case R28: case X28: case F28: case V28: return 28;
75 case R29: case X29: case F29: case V29: return 29;
76 case R30: case X30: case F30: case V30: return 30;
77 case R31: case X31: case F31: case V31: return 31;
79 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
84 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
85 const TargetInstrInfo &tii)
86 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
87 Subtarget(ST), TII(tii) {
88 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
89 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
90 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
91 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
92 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
93 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
94 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
95 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
96 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
100 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
101 MachineBasicBlock::iterator MI,
102 unsigned SrcReg, int FrameIdx,
103 const TargetRegisterClass *RC) const {
104 if (RC == PPC::GPRCRegisterClass) {
105 if (SrcReg != PPC::LR) {
106 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(SrcReg),
109 // FIXME: this spills LR immediately to memory in one step. To do this,
110 // we use R11, which we know cannot be used in the prolog/epilog. This is
112 BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11);
113 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R11),
116 } else if (RC == PPC::G8RCRegisterClass) {
117 if (SrcReg != PPC::LR8) {
118 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(SrcReg),
121 // FIXME: this spills LR immediately to memory in one step. To do this,
122 // we use R11, which we know cannot be used in the prolog/epilog. This is
124 BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11);
125 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(PPC::X11),
128 } else if (RC == PPC::F8RCRegisterClass) {
129 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD)).addReg(SrcReg),
131 } else if (RC == PPC::F4RCRegisterClass) {
132 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS)).addReg(SrcReg),
134 } else if (RC == PPC::CRRCRegisterClass) {
135 // FIXME: We use R0 here, because it isn't available for RA.
136 // We need to store the CR in the low 4-bits of the saved value. First,
137 // issue a MFCR to save all of the CRBits.
138 BuildMI(MBB, MI, TII.get(PPC::MFCR), PPC::R0);
140 // If the saved register wasn't CR0, shift the bits left so that they are in
142 if (SrcReg != PPC::CR0) {
143 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
144 // rlwinm r0, r0, ShiftBits, 0, 31.
145 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0)
146 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31);
149 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R0),
151 } else if (RC == PPC::VRRCRegisterClass) {
152 // We don't have indexed addressing for vector loads. Emit:
154 // Dest = LVX R0, R11
156 // FIXME: We use R0 here, because it isn't available for RA.
157 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
159 BuildMI(MBB, MI, TII.get(PPC::STVX))
160 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
162 assert(0 && "Unknown regclass!");
168 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
169 MachineBasicBlock::iterator MI,
170 unsigned DestReg, int FrameIdx,
171 const TargetRegisterClass *RC) const {
172 if (RC == PPC::GPRCRegisterClass) {
173 if (DestReg != PPC::LR) {
174 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), DestReg), FrameIdx);
176 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R11),FrameIdx);
177 BuildMI(MBB, MI, TII.get(PPC::MTLR)).addReg(PPC::R11);
179 } else if (RC == PPC::G8RCRegisterClass) {
180 if (DestReg != PPC::LR8) {
181 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), DestReg), FrameIdx);
183 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), PPC::R11), FrameIdx);
184 BuildMI(MBB, MI, TII.get(PPC::MTLR8)).addReg(PPC::R11);
186 } else if (RC == PPC::F8RCRegisterClass) {
187 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFD), DestReg), FrameIdx);
188 } else if (RC == PPC::F4RCRegisterClass) {
189 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFS), DestReg), FrameIdx);
190 } else if (RC == PPC::CRRCRegisterClass) {
191 // FIXME: We use R0 here, because it isn't available for RA.
192 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R0), FrameIdx);
194 // If the reloaded register isn't CR0, shift the bits right so that they are
195 // in the right CR's slot.
196 if (DestReg != PPC::CR0) {
197 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
198 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
199 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0)
200 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31);
203 BuildMI(MBB, MI, TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0);
204 } else if (RC == PPC::VRRCRegisterClass) {
205 // We don't have indexed addressing for vector loads. Emit:
207 // Dest = LVX R0, R11
209 // FIXME: We use R0 here, because it isn't available for RA.
210 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
212 BuildMI(MBB, MI, TII.get(PPC::LVX),DestReg).addReg(PPC::R0).addReg(PPC::R0);
214 assert(0 && "Unknown regclass!");
219 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
220 MachineBasicBlock::iterator MI,
221 unsigned DestReg, unsigned SrcReg,
222 const TargetRegisterClass *RC) const {
223 if (RC == PPC::GPRCRegisterClass) {
224 BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
225 } else if (RC == PPC::G8RCRegisterClass) {
226 BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
227 } else if (RC == PPC::F4RCRegisterClass) {
228 BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg);
229 } else if (RC == PPC::F8RCRegisterClass) {
230 BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg);
231 } else if (RC == PPC::CRRCRegisterClass) {
232 BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg);
233 } else if (RC == PPC::VRRCRegisterClass) {
234 BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
236 cerr << "Attempt to copy register that is not GPR or FPR";
241 const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const {
242 // 32-bit Darwin calling convention.
243 static const unsigned Darwin32_CalleeSavedRegs[] = {
244 PPC::R13, PPC::R14, PPC::R15,
245 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
246 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
247 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
248 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
250 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
251 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
252 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
253 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
256 PPC::CR2, PPC::CR3, PPC::CR4,
257 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
258 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
259 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
263 // 64-bit Darwin calling convention.
264 static const unsigned Darwin64_CalleeSavedRegs[] = {
266 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
267 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
268 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
269 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
271 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
272 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
273 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
274 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
277 PPC::CR2, PPC::CR3, PPC::CR4,
278 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
279 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
280 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
285 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
286 Darwin32_CalleeSavedRegs;
289 const TargetRegisterClass* const*
290 PPCRegisterInfo::getCalleeSavedRegClasses() const {
291 // 32-bit Darwin calling convention.
292 static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = {
293 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
294 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
295 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
296 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
297 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
299 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
300 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
301 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
302 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
303 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
305 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
307 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
308 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
309 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
311 &PPC::GPRCRegClass, 0
314 // 64-bit Darwin calling convention.
315 static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = {
316 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
317 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
318 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
319 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
320 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
322 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
323 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
324 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
325 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
326 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
328 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
330 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
331 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
332 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
334 &PPC::G8RCRegClass, 0
337 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses :
338 Darwin32_CalleeSavedRegClasses;
341 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
342 /// copy instructions, turning them into load/store instructions.
343 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
345 int FrameIndex) const {
346 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
347 // it takes more than one instruction to store it.
348 unsigned Opc = MI->getOpcode();
350 MachineInstr *NewMI = NULL;
351 if ((Opc == PPC::OR &&
352 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
353 if (OpNum == 0) { // move -> store
354 unsigned InReg = MI->getOperand(1).getReg();
355 NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg),
357 } else { // move -> load
358 unsigned OutReg = MI->getOperand(0).getReg();
359 NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg),
362 } else if ((Opc == PPC::OR8 &&
363 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
364 if (OpNum == 0) { // move -> store
365 unsigned InReg = MI->getOperand(1).getReg();
366 NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg),
368 } else { // move -> load
369 unsigned OutReg = MI->getOperand(0).getReg();
370 NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex);
372 } else if (Opc == PPC::FMRD) {
373 if (OpNum == 0) { // move -> store
374 unsigned InReg = MI->getOperand(1).getReg();
375 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg),
377 } else { // move -> load
378 unsigned OutReg = MI->getOperand(0).getReg();
379 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex);
381 } else if (Opc == PPC::FMRS) {
382 if (OpNum == 0) { // move -> store
383 unsigned InReg = MI->getOperand(1).getReg();
384 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg),
386 } else { // move -> load
387 unsigned OutReg = MI->getOperand(0).getReg();
388 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex);
393 NewMI->copyKillDeadInfo(MI);
397 //===----------------------------------------------------------------------===//
398 // Stack Frame Processing methods
399 //===----------------------------------------------------------------------===//
401 // needsFP - Return true if the specified function should have a dedicated frame
402 // pointer register. This is true if the function has variable sized allocas or
403 // if frame pointer elimination is disabled.
405 static bool needsFP(const MachineFunction &MF) {
406 const MachineFrameInfo *MFI = MF.getFrameInfo();
407 return NoFramePointerElim || MFI->hasVarSizedObjects();
410 // hasFP - Return true if the specified function actually has a dedicated frame
411 // pointer register. This is true if the function needs a frame pointer and has
412 // a non-zero stack size.
413 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
414 const MachineFrameInfo *MFI = MF.getFrameInfo();
415 return MFI->getStackSize() && needsFP(MF);
418 /// usesLR - Returns if the link registers (LR) has been used in the function.
420 bool PPCRegisterInfo::usesLR(MachineFunction &MF) const {
421 const bool *PhysRegsUsed = MF.getUsedPhysregs();
422 return PhysRegsUsed[getRARegister()];
425 void PPCRegisterInfo::
426 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
427 MachineBasicBlock::iterator I) const {
428 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
432 /// LowerDynamicAlloc - Generate the code for allocating an object in the
433 /// current frame. The sequence of code with be in the general form
435 /// addi R0, SP, #frameSize ; get the address of the previous frame
436 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
437 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation
439 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
440 // Get the instruction.
441 MachineInstr &MI = *II;
442 // Get the instruction's basic block.
443 MachineBasicBlock &MBB = *MI.getParent();
444 // Get the basic block's function.
445 MachineFunction &MF = *MBB.getParent();
446 // Get the frame info.
447 MachineFrameInfo *MFI = MF.getFrameInfo();
448 // Determine whether 64-bit pointers are used.
449 bool LP64 = Subtarget.isPPC64();
451 // Get the maximum call stack size.
452 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
453 // Get the total frame size.
454 unsigned FrameSize = MFI->getStackSize();
456 // Get stack alignments.
457 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
458 unsigned MaxAlign = MFI->getMaxAlignment();
459 assert(MaxAlign <= TargetAlign &&
460 "Dynamic alloca with large aligns not supported");
462 // Determine the previous frame's address. If FrameSize can't be
463 // represented as 16 bits or we need special alignment, then we load the
464 // previous frame's address from 0(SP). Why not do an addis of the hi?
465 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
466 // Constructing the constant and adding would take 3 instructions.
467 // Fortunately, a frame greater than 32K is rare.
468 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
469 BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0)
473 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
477 BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0)
482 // Grow the stack and update the stack pointer link, then
483 // determine the address of new allocated space.
485 BuildMI(MBB, II, TII.get(PPC::STDUX))
488 .addReg(MI.getOperand(1).getReg());
489 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
491 .addImm(maxCallFrameSize);
493 BuildMI(MBB, II, TII.get(PPC::STWUX))
496 .addReg(MI.getOperand(1).getReg());
497 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
499 .addImm(maxCallFrameSize);
502 // Discard the DYNALLOC instruction.
507 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
508 // Get the instruction.
509 MachineInstr &MI = *II;
510 // Get the instruction's basic block.
511 MachineBasicBlock &MBB = *MI.getParent();
512 // Get the basic block's function.
513 MachineFunction &MF = *MBB.getParent();
514 // Get the frame info.
515 MachineFrameInfo *MFI = MF.getFrameInfo();
517 // Find out which operand is the frame index.
519 while (!MI.getOperand(i).isFrameIndex()) {
521 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
523 // Take into account whether it's an add or mem instruction
524 unsigned OffIdx = (i == 2) ? 1 : 2;
525 // Get the frame index.
526 int FrameIndex = MI.getOperand(i).getFrameIndex();
528 // Get the frame pointer save index. Users of this index are primarily
529 // DYNALLOC instructions.
530 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
531 int FPSI = FI->getFramePointerSaveIndex();
532 // Get the instruction opcode.
533 unsigned OpC = MI.getOpcode();
535 // Special case for dynamic alloca.
536 if (FPSI && FrameIndex == FPSI &&
537 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
538 lowerDynamicAlloc(II);
542 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
543 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false);
545 // Figure out if the offset in the instruction is shifted right two bits. This
546 // is true for instructions like "STD", which the machine implicitly adds two
548 bool isIXAddr = false;
558 // Now add the frame object offset to the offset from r1.
559 int Offset = MFI->getObjectOffset(FrameIndex);
562 Offset += MI.getOperand(OffIdx).getImmedValue();
564 Offset += MI.getOperand(OffIdx).getImmedValue() << 2;
566 // If we're not using a Frame Pointer that has been set to the value of the
567 // SP before having the stack size subtracted from it, then add the stack size
568 // to Offset to get the correct offset.
569 Offset += MFI->getStackSize();
571 if (!isInt16(Offset)) {
572 // Insert a set of r0 with the full offset value before the ld, st, or add
573 BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16);
574 BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset);
576 // convert into indexed form of the instruction
577 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
578 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
579 assert(ImmToIdxMap.count(OpC) &&
580 "No indexed form of load or store available!");
581 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
582 MI.setInstrDescriptor(TII.get(NewOpcode));
583 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false);
584 MI.getOperand(2).ChangeToRegister(PPC::R0, false);
587 assert((Offset & 3) == 0 && "Invalid frame offset!");
588 Offset >>= 2; // The actual encoded value has the low two bits zero.
590 MI.getOperand(OffIdx).ChangeToImmediate(Offset);
594 /// VRRegNo - Map from a numbered VR register to its enum value.
596 static const unsigned short VRRegNo[] = {
597 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
598 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
599 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
600 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
603 /// RemoveVRSaveCode - We have found that this function does not need any code
604 /// to manipulate the VRSAVE register, even though it uses vector registers.
605 /// This can happen when the only registers used are known to be live in or out
606 /// of the function. Remove all of the VRSAVE related code from the function.
607 static void RemoveVRSaveCode(MachineInstr *MI) {
608 MachineBasicBlock *Entry = MI->getParent();
609 MachineFunction *MF = Entry->getParent();
611 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
612 MachineBasicBlock::iterator MBBI = MI;
614 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
615 MBBI->eraseFromParent();
617 bool RemovedAllMTVRSAVEs = true;
618 // See if we can find and remove the MTVRSAVE instruction from all of the
620 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
621 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
622 // If last instruction is a return instruction, add an epilogue
623 if (!I->empty() && TII.isReturn(I->back().getOpcode())) {
624 bool FoundIt = false;
625 for (MBBI = I->end(); MBBI != I->begin(); ) {
627 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
628 MBBI->eraseFromParent(); // remove it.
633 RemovedAllMTVRSAVEs &= FoundIt;
637 // If we found and removed all MTVRSAVE instructions, remove the read of
639 if (RemovedAllMTVRSAVEs) {
641 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
643 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
644 MBBI->eraseFromParent();
647 // Finally, nuke the UPDATE_VRSAVE.
648 MI->eraseFromParent();
651 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
652 // instruction selector. Based on the vector registers that have been used,
653 // transform this into the appropriate ORI instruction.
654 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs,
655 const TargetInstrInfo &TII) {
656 unsigned UsedRegMask = 0;
657 for (unsigned i = 0; i != 32; ++i)
658 if (UsedRegs[VRRegNo[i]])
659 UsedRegMask |= 1 << (31-i);
661 // Live in and live out values already must be in the mask, so don't bother
663 MachineFunction *MF = MI->getParent()->getParent();
664 for (MachineFunction::livein_iterator I =
665 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) {
666 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
667 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
668 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
670 for (MachineFunction::liveout_iterator I =
671 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) {
672 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
673 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
674 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
677 unsigned SrcReg = MI->getOperand(1).getReg();
678 unsigned DstReg = MI->getOperand(0).getReg();
679 // If no registers are used, turn this into a copy.
680 if (UsedRegMask == 0) {
681 // Remove all VRSAVE code.
682 RemoveVRSaveCode(MI);
684 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
685 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
686 .addReg(SrcReg).addImm(UsedRegMask);
687 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
688 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
689 .addReg(SrcReg).addImm(UsedRegMask >> 16);
691 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
692 .addReg(SrcReg).addImm(UsedRegMask >> 16);
693 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
694 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
697 // Remove the old UPDATE_VRSAVE instruction.
698 MI->eraseFromParent();
701 /// determineFrameLayout - Determine the size of the frame and maximum call
703 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
704 MachineFrameInfo *MFI = MF.getFrameInfo();
706 // Get the number of bytes to allocate from the FrameInfo
707 unsigned FrameSize = MFI->getStackSize();
709 // Get the alignments provided by the target, and the maximum alignment
710 // (if any) of the fixed frame objects.
711 unsigned MaxAlign = MFI->getMaxAlignment();
712 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
713 unsigned AlignMask = TargetAlign - 1; //
715 // If we are a leaf function, and use up to 224 bytes of stack space,
716 // don't have a frame pointer, calls, or dynamic alloca then we do not need
717 // to adjust the stack pointer (we fit in the Red Zone).
718 if (FrameSize <= 224 && // Fits in red zone.
719 !MFI->hasVarSizedObjects() && // No dynamic alloca.
720 !MFI->hasCalls() && // No calls.
721 MaxAlign <= TargetAlign) { // No special alignment.
723 MFI->setStackSize(0);
727 // Get the maximum call frame size of all the calls.
728 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
730 // Maximum call frame needs to be at least big enough for linkage and 8 args.
731 unsigned minCallFrameSize =
732 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64());
733 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
735 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
736 // that allocations will be aligned.
737 if (MFI->hasVarSizedObjects())
738 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
740 // Update maximum call frame size.
741 MFI->setMaxCallFrameSize(maxCallFrameSize);
743 // Include call frame size in total.
744 FrameSize += maxCallFrameSize;
746 // Make sure the frame is aligned.
747 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
749 // Update frame info.
750 MFI->setStackSize(FrameSize);
753 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
754 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
755 MachineBasicBlock::iterator MBBI = MBB.begin();
756 MachineFrameInfo *MFI = MF.getFrameInfo();
757 MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo();
759 // Prepare for debug frame info.
760 bool hasInfo = DebugInfo && DebugInfo->hasInfo();
761 unsigned FrameLabelId = 0;
763 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
765 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
766 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
767 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs(), TII);
772 // Move MBBI back to the beginning of the function.
775 // Work out frame sizes.
776 determineFrameLayout(MF);
777 unsigned FrameSize = MFI->getStackSize();
779 // Skip if a leaf routine.
780 if (!FrameSize) return;
782 int NegFrameSize = -FrameSize;
784 // Get processor type.
785 bool IsPPC64 = Subtarget.isPPC64();
786 // Check if the link register (LR) has been used.
787 bool UsesLR = MFI->hasCalls() || usesLR(MF);
788 // Do we have a frame pointer for this function?
789 bool HasFP = hasFP(MF);
791 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64);
792 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64);
796 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0);
799 BuildMI(MBB, MBBI, TII.get(PPC::STD))
800 .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1);
803 BuildMI(MBB, MBBI, TII.get(PPC::STD))
804 .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1);
807 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0);
810 BuildMI(MBB, MBBI, TII.get(PPC::STW))
811 .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1);
814 BuildMI(MBB, MBBI, TII.get(PPC::STW))
815 .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1);
818 // Get stack alignments.
819 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
820 unsigned MaxAlign = MFI->getMaxAlignment();
823 // Mark effective beginning of when frame pointer becomes valid.
824 FrameLabelId = DebugInfo->NextLabelID();
825 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId);
828 // Adjust stack pointer: r1 += NegFrameSize.
829 // If there is a preferred stack alignment, align R1 now
832 if (MaxAlign > TargetAlign) {
833 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
834 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
835 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
836 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
837 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0)
838 .addImm(NegFrameSize);
839 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
840 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
841 } else if (isInt16(NegFrameSize)) {
842 BuildMI(MBB, MBBI, TII.get(PPC::STWU),
843 PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1);
845 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16);
846 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0)
847 .addImm(NegFrameSize & 0xFFFF);
848 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1)
852 if (MaxAlign > TargetAlign) {
853 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
854 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
855 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
856 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign));
857 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0)
858 .addImm(NegFrameSize);
859 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
860 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0);
861 } else if (isInt16(NegFrameSize)) {
862 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
863 .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1);
865 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16);
866 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0)
867 .addImm(NegFrameSize & 0xFFFF);
868 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1)
874 std::vector<MachineMove> &Moves = DebugInfo->getFrameMoves();
877 // Show update of SP.
878 MachineLocation SPDst(MachineLocation::VirtualFP);
879 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
880 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
882 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
883 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
887 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
888 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
889 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
892 // Add callee saved registers to move list.
893 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
894 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
895 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
896 unsigned Reg = CSI[I].getReg();
897 if (Reg == PPC::LR || Reg == PPC::LR8) continue;
898 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
899 MachineLocation CSSrc(Reg);
900 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
903 // Mark effective beginning of when frame pointer is ready.
904 unsigned ReadyLabelId = DebugInfo->NextLabelID();
905 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId);
907 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
908 (IsPPC64 ? PPC::X1 : PPC::R1));
909 MachineLocation FPSrc(MachineLocation::VirtualFP);
910 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
913 // If there is a frame pointer, copy R1 into R31
916 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1)
919 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1)
925 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
926 MachineBasicBlock &MBB) const {
927 MachineBasicBlock::iterator MBBI = prior(MBB.end());
928 assert(MBBI->getOpcode() == PPC::BLR &&
929 "Can only insert epilog into returning blocks");
931 // Get alignment info so we know how to restore r1
932 const MachineFrameInfo *MFI = MF.getFrameInfo();
933 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
934 unsigned MaxAlign = MFI->getMaxAlignment();
936 // Get the number of bytes allocated from the FrameInfo.
937 unsigned FrameSize = MFI->getStackSize();
939 if (!FrameSize) return;
941 // Get processor type.
942 bool IsPPC64 = Subtarget.isPPC64();
943 // Check if the link register (LR) has been used.
944 bool UsesLR = MFI->hasCalls() || usesLR(MF);
945 // Do we have a frame pointer for this function?
946 bool HasFP = hasFP(MF);
948 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
949 // on entry to the function. Add this offset back now.
950 if (!Subtarget.isPPC64()) {
951 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
952 !MFI->hasVarSizedObjects()) {
953 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
954 .addReg(PPC::R1).addImm(FrameSize);
956 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
959 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
960 !MFI->hasVarSizedObjects()) {
961 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
962 .addReg(PPC::X1).addImm(FrameSize);
964 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
968 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64);
969 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64);
973 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0)
974 .addImm(LROffset/4).addReg(PPC::X1);
977 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
978 .addImm(FPOffset/4).addReg(PPC::X1);
981 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0);
984 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0)
985 .addImm(LROffset).addReg(PPC::R1);
988 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
989 .addImm(FPOffset).addReg(PPC::R1);
992 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0);
996 unsigned PPCRegisterInfo::getRARegister() const {
997 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
1001 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1002 if (!Subtarget.isPPC64())
1003 return hasFP(MF) ? PPC::R31 : PPC::R1;
1005 return hasFP(MF) ? PPC::X31 : PPC::X1;
1008 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1010 // Initial state of the frame pointer is R1.
1011 MachineLocation Dst(MachineLocation::VirtualFP);
1012 MachineLocation Src(PPC::R1, 0);
1013 Moves.push_back(MachineMove(0, Dst, Src));
1016 #include "PPCGenRegisterInfo.inc"