1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PPCInstrBuilder.h"
17 #include "PPCRegisterInfo.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineDebugInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineLocation.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/ADT/STLExtras.h"
39 /// getRegisterNumbering - Given the enum value for some register, e.g.
40 /// PPC::F14, return the number that it corresponds to (e.g. 14).
41 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
43 case PPC::R0 : case PPC::F0 : case PPC::V0 : case PPC::CR0: return 0;
44 case PPC::R1 : case PPC::F1 : case PPC::V1 : case PPC::CR1: return 1;
45 case PPC::R2 : case PPC::F2 : case PPC::V2 : case PPC::CR2: return 2;
46 case PPC::R3 : case PPC::F3 : case PPC::V3 : case PPC::CR3: return 3;
47 case PPC::R4 : case PPC::F4 : case PPC::V4 : case PPC::CR4: return 4;
48 case PPC::R5 : case PPC::F5 : case PPC::V5 : case PPC::CR5: return 5;
49 case PPC::R6 : case PPC::F6 : case PPC::V6 : case PPC::CR6: return 6;
50 case PPC::R7 : case PPC::F7 : case PPC::V7 : case PPC::CR7: return 7;
51 case PPC::R8 : case PPC::F8 : case PPC::V8 : return 8;
52 case PPC::R9 : case PPC::F9 : case PPC::V9 : return 9;
53 case PPC::R10: case PPC::F10: case PPC::V10: return 10;
54 case PPC::R11: case PPC::F11: case PPC::V11: return 11;
55 case PPC::R12: case PPC::F12: case PPC::V12: return 12;
56 case PPC::R13: case PPC::F13: case PPC::V13: return 13;
57 case PPC::R14: case PPC::F14: case PPC::V14: return 14;
58 case PPC::R15: case PPC::F15: case PPC::V15: return 15;
59 case PPC::R16: case PPC::F16: case PPC::V16: return 16;
60 case PPC::R17: case PPC::F17: case PPC::V17: return 17;
61 case PPC::R18: case PPC::F18: case PPC::V18: return 18;
62 case PPC::R19: case PPC::F19: case PPC::V19: return 19;
63 case PPC::R20: case PPC::F20: case PPC::V20: return 20;
64 case PPC::R21: case PPC::F21: case PPC::V21: return 21;
65 case PPC::R22: case PPC::F22: case PPC::V22: return 22;
66 case PPC::R23: case PPC::F23: case PPC::V23: return 23;
67 case PPC::R24: case PPC::F24: case PPC::V24: return 24;
68 case PPC::R25: case PPC::F25: case PPC::V25: return 25;
69 case PPC::R26: case PPC::F26: case PPC::V26: return 26;
70 case PPC::R27: case PPC::F27: case PPC::V27: return 27;
71 case PPC::R28: case PPC::F28: case PPC::V28: return 28;
72 case PPC::R29: case PPC::F29: case PPC::V29: return 29;
73 case PPC::R30: case PPC::F30: case PPC::V30: return 30;
74 case PPC::R31: case PPC::F31: case PPC::V31: return 31;
76 std::cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
81 PPCRegisterInfo::PPCRegisterInfo()
82 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
83 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
84 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
85 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
86 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
87 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
88 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
89 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
90 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
94 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
95 MachineBasicBlock::iterator MI,
96 unsigned SrcReg, int FrameIdx,
97 const TargetRegisterClass *RC) const {
98 if (SrcReg == PPC::LR) {
99 // FIXME: this spills LR immediately to memory in one step. To do this, we
100 // use R11, which we know cannot be used in the prolog/epilog. This is a
102 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
103 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
104 } else if (RC == PPC::CRRCRegisterClass) {
105 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
106 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
107 } else if (RC == PPC::GPRCRegisterClass) {
108 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
109 } else if (RC == PPC::G8RCRegisterClass) {
110 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx);
111 } else if (RC == PPC::F8RCRegisterClass) {
112 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
113 } else if (RC == PPC::F4RCRegisterClass) {
114 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
115 } else if (RC == PPC::VRRCRegisterClass) {
116 // We don't have indexed addressing for vector loads. Emit:
118 // Dest = LVX R0, R11
120 // FIXME: We use R0 here, because it isn't available for RA.
121 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
122 BuildMI(MBB, MI, PPC::STVX, 3)
123 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
125 assert(0 && "Unknown regclass!");
131 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
132 MachineBasicBlock::iterator MI,
133 unsigned DestReg, int FrameIdx,
134 const TargetRegisterClass *RC) const {
135 if (DestReg == PPC::LR) {
136 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
137 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
138 } else if (RC == PPC::CRRCRegisterClass) {
139 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
140 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
141 } else if (RC == PPC::GPRCRegisterClass) {
142 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
143 } else if (RC == PPC::G8RCRegisterClass) {
144 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
145 } else if (RC == PPC::F8RCRegisterClass) {
146 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
147 } else if (RC == PPC::F4RCRegisterClass) {
148 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
149 } else if (RC == PPC::VRRCRegisterClass) {
150 // We don't have indexed addressing for vector loads. Emit:
152 // Dest = LVX R0, R11
154 // FIXME: We use R0 here, because it isn't available for RA.
155 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
156 BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
158 assert(0 && "Unknown regclass!");
163 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
164 MachineBasicBlock::iterator MI,
165 unsigned DestReg, unsigned SrcReg,
166 const TargetRegisterClass *RC) const {
167 if (RC == PPC::GPRCRegisterClass) {
168 BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
169 } else if (RC == PPC::G8RCRegisterClass) {
170 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
171 } else if (RC == PPC::F4RCRegisterClass) {
172 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
173 } else if (RC == PPC::F8RCRegisterClass) {
174 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
175 } else if (RC == PPC::CRRCRegisterClass) {
176 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
177 } else if (RC == PPC::VRRCRegisterClass) {
178 BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
180 std::cerr << "Attempt to copy register that is not GPR or FPR";
185 const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
186 static const unsigned CalleeSaveRegs[] = {
215 return CalleeSaveRegs;
218 const TargetRegisterClass* const*
219 PPCRegisterInfo::getCalleeSaveRegClasses() const {
220 static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
221 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
222 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
223 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
224 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
225 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
226 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
227 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
228 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
229 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
230 &PPC::GPRCRegClass, &PPC::GPRCRegClass,
231 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
232 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
233 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
234 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
235 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
236 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
237 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
238 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
239 &PPC::F8RCRegClass, &PPC::F8RCRegClass,
240 &PPC::CRRCRegClass, &PPC::CRRCRegClass,
241 &PPC::CRRCRegClass, &PPC::VRRCRegClass,
242 &PPC::VRRCRegClass, &PPC::VRRCRegClass,
243 &PPC::VRRCRegClass, &PPC::VRRCRegClass,
244 &PPC::VRRCRegClass, &PPC::VRRCRegClass,
245 &PPC::VRRCRegClass, &PPC::VRRCRegClass,
246 &PPC::VRRCRegClass, &PPC::VRRCRegClass,
247 &PPC::VRRCRegClass, &PPC::GPRCRegClass, 0
249 return CalleeSaveRegClasses;
252 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
253 /// copy instructions, turning them into load/store instructions.
254 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
256 int FrameIndex) const {
257 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
258 // it takes more than one instruction to store it.
259 unsigned Opc = MI->getOpcode();
261 if ((Opc == PPC::OR4 &&
262 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
263 if (OpNum == 0) { // move -> store
264 unsigned InReg = MI->getOperand(1).getReg();
265 return addFrameReference(BuildMI(PPC::STW,
266 3).addReg(InReg), FrameIndex);
267 } else { // move -> load
268 unsigned OutReg = MI->getOperand(0).getReg();
269 return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
271 } else if ((Opc == PPC::OR8 &&
272 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
273 if (OpNum == 0) { // move -> store
274 unsigned InReg = MI->getOperand(1).getReg();
275 return addFrameReference(BuildMI(PPC::STD,
276 3).addReg(InReg), FrameIndex);
277 } else { // move -> load
278 unsigned OutReg = MI->getOperand(0).getReg();
279 return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex);
281 } else if (Opc == PPC::FMRD) {
282 if (OpNum == 0) { // move -> store
283 unsigned InReg = MI->getOperand(1).getReg();
284 return addFrameReference(BuildMI(PPC::STFD,
285 3).addReg(InReg), FrameIndex);
286 } else { // move -> load
287 unsigned OutReg = MI->getOperand(0).getReg();
288 return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex);
290 } else if (Opc == PPC::FMRS) {
291 if (OpNum == 0) { // move -> store
292 unsigned InReg = MI->getOperand(1).getReg();
293 return addFrameReference(BuildMI(PPC::STFS,
294 3).addReg(InReg), FrameIndex);
295 } else { // move -> load
296 unsigned OutReg = MI->getOperand(0).getReg();
297 return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex);
303 //===----------------------------------------------------------------------===//
304 // Stack Frame Processing methods
305 //===----------------------------------------------------------------------===//
307 // hasFP - Return true if the specified function should have a dedicated frame
308 // pointer register. This is true if the function has variable sized allocas or
309 // if frame pointer elimination is disabled.
311 static bool hasFP(const MachineFunction &MF) {
312 const MachineFrameInfo *MFI = MF.getFrameInfo();
313 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
315 // If frame pointers are forced, or if there are variable sized stack objects,
316 // use a frame pointer.
318 return NoFramePointerElim || MFI->hasVarSizedObjects();
321 void PPCRegisterInfo::
322 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
323 MachineBasicBlock::iterator I) const {
325 // If we have a frame pointer, convert as follows:
326 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
327 // ADJCALLSTACKUP -> addi, r1, r1, amount
328 MachineInstr *Old = I;
329 unsigned Amount = Old->getOperand(0).getImmedValue();
331 // We need to keep the stack aligned properly. To do this, we round the
332 // amount of space needed for the outgoing arguments up to the next
333 // alignment boundary.
334 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
335 Amount = (Amount+Align-1)/Align*Align;
337 // Replace the pseudo instruction with a new instruction...
338 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
339 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(-Amount);
341 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
342 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(Amount);
350 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
352 MachineInstr &MI = *II;
353 MachineBasicBlock &MBB = *MI.getParent();
354 MachineFunction &MF = *MBB.getParent();
356 while (!MI.getOperand(i).isFrameIndex()) {
358 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
361 int FrameIndex = MI.getOperand(i).getFrameIndex();
363 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
364 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1);
366 // Take into account whether it's an add or mem instruction
367 unsigned OffIdx = (i == 2) ? 1 : 2;
369 // Now add the frame object offset to the offset from r1.
370 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
371 MI.getOperand(OffIdx).getImmedValue();
373 // If we're not using a Frame Pointer that has been set to the value of the
374 // SP before having the stack size subtracted from it, then add the stack size
375 // to Offset to get the correct offset.
376 Offset += MF.getFrameInfo()->getStackSize();
378 if (Offset > 32767 || Offset < -32768) {
379 // Insert a set of r0 with the full offset value before the ld, st, or add
380 MachineBasicBlock *MBB = MI.getParent();
381 BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addImm(Offset >> 16);
382 BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset);
384 // convert into indexed form of the instruction
385 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
386 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
387 assert(ImmToIdxMap.count(MI.getOpcode()) &&
388 "No indexed form of load or store available!");
389 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
390 MI.setOpcode(NewOpcode);
391 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg());
392 MI.getOperand(2).ChangeToRegister(PPC::R0);
394 switch (MI.getOpcode()) {
399 assert((Offset & 3) == 0 && "Invalid frame offset!");
400 Offset >>= 2; // The actual encoded value has the low two bits zero.
403 MI.getOperand(OffIdx).ChangeToImmediate(Offset);
407 /// VRRegNo - Map from a numbered VR register to its enum value.
409 static const unsigned short VRRegNo[] = {
410 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
411 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
412 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
413 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
416 /// RemoveVRSaveCode - We have found that this function does not need any code
417 /// to manipulate the VRSAVE register, even though it uses vector registers.
418 /// This can happen when the only registers used are known to be live in or out
419 /// of the function. Remove all of the VRSAVE related code from the function.
420 static void RemoveVRSaveCode(MachineInstr *MI) {
421 MachineBasicBlock *Entry = MI->getParent();
422 MachineFunction *MF = Entry->getParent();
424 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
425 MachineBasicBlock::iterator MBBI = MI;
427 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
428 MBBI->eraseFromParent();
430 bool RemovedAllMTVRSAVEs = true;
431 // See if we can find and remove the MTVRSAVE instruction from all of the
433 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
434 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
435 // If last instruction is a return instruction, add an epilogue
436 if (!I->empty() && TII.isReturn(I->back().getOpcode())) {
437 bool FoundIt = false;
438 for (MBBI = I->end(); MBBI != I->begin(); ) {
440 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
441 MBBI->eraseFromParent(); // remove it.
446 RemovedAllMTVRSAVEs &= FoundIt;
450 // If we found and removed all MTVRSAVE instructions, remove the read of
452 if (RemovedAllMTVRSAVEs) {
454 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
456 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
457 MBBI->eraseFromParent();
460 // Finally, nuke the UPDATE_VRSAVE.
461 MI->eraseFromParent();
464 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
465 // instruction selector. Based on the vector registers that have been used,
466 // transform this into the appropriate ORI instruction.
467 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) {
468 unsigned UsedRegMask = 0;
469 for (unsigned i = 0; i != 32; ++i)
470 if (UsedRegs[VRRegNo[i]])
471 UsedRegMask |= 1 << (31-i);
473 // Live in and live out values already must be in the mask, so don't bother
475 MachineFunction *MF = MI->getParent()->getParent();
476 for (MachineFunction::livein_iterator I =
477 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) {
478 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
479 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
480 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
482 for (MachineFunction::liveout_iterator I =
483 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) {
484 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
485 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
486 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
489 unsigned SrcReg = MI->getOperand(1).getReg();
490 unsigned DstReg = MI->getOperand(0).getReg();
491 // If no registers are used, turn this into a copy.
492 if (UsedRegMask == 0) {
493 // Remove all VRSAVE code.
494 RemoveVRSaveCode(MI);
496 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
497 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
498 .addReg(SrcReg).addImm(UsedRegMask);
499 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
500 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
501 .addReg(SrcReg).addImm(UsedRegMask >> 16);
503 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
504 .addReg(SrcReg).addImm(UsedRegMask >> 16);
505 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
506 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
509 // Remove the old UPDATE_VRSAVE instruction.
510 MI->eraseFromParent();
514 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
515 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
516 MachineBasicBlock::iterator MBBI = MBB.begin();
517 MachineFrameInfo *MFI = MF.getFrameInfo();
518 MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo();
520 // Do we have a frame pointer for this function?
521 bool HasFP = hasFP(MF);
523 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
525 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
526 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
527 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
532 // Move MBBI back to the beginning of the function.
535 // Get the number of bytes to allocate from the FrameInfo
536 unsigned NumBytes = MFI->getStackSize();
538 // Get the alignments provided by the target, and the maximum alignment
539 // (if any) of the fixed frame objects.
540 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
541 unsigned MaxAlign = MFI->getMaxAlignment();
543 // If we have calls, we cannot use the red zone to store callee save registers
544 // and we must set up a stack frame, so calculate the necessary size here.
545 if (MFI->hasCalls()) {
546 // We reserve argument space for call sites in the function immediately on
547 // entry to the current function. This eliminates the need for add/sub
548 // brackets around call sites.
549 NumBytes += MFI->getMaxCallFrameSize();
552 // If we are a leaf function, and use up to 224 bytes of stack space,
553 // and don't have a frame pointer, then we do not need to adjust the stack
554 // pointer (we fit in the Red Zone).
555 if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() &&
556 MaxAlign <= TargetAlign)) {
557 MFI->setStackSize(0);
561 // Add the size of R1 to NumBytes size for the store of R1 to the bottom
562 // of the stack and round the size to a multiple of the alignment.
563 unsigned Align = std::max(TargetAlign, MaxAlign);
564 unsigned GPRSize = 4;
565 unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize;
566 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
568 // Update frame info to pretend that this is part of the stack...
569 MFI->setStackSize(NumBytes);
570 int NegNumbytes = -NumBytes;
572 // Adjust stack pointer: r1 -= numbytes.
573 // If there is a preferred stack alignment, align R1 now
574 if (MaxAlign > TargetAlign) {
575 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!");
576 assert(isInt16(0-NumBytes) && "Unhandled stack size and alignment!");
577 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
578 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
579 BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
581 BuildMI(MBB, MBBI, PPC::STWUX, 3)
582 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
583 } else if (NumBytes <= 32768) {
584 BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addImm(NegNumbytes)
587 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegNumbytes >> 16);
588 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
589 .addImm(NegNumbytes & 0xFFFF);
590 BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
594 if (DebugInfo && DebugInfo->hasInfo()) {
595 std::vector<MachineMove *> &Moves = DebugInfo->getFrameMoves();
596 unsigned LabelID = DebugInfo->NextLabelID();
598 // Show update of SP.
599 MachineLocation Dst(MachineLocation::VirtualFP);
600 MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes);
601 Moves.push_back(new MachineMove(LabelID, Dst, Src));
603 BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addImm(LabelID);
606 // If there is a frame pointer, copy R1 (SP) into R31 (FP)
608 BuildMI(MBB, MBBI, PPC::STW, 3)
609 .addReg(PPC::R31).addImm(GPRSize).addReg(PPC::R1);
610 BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
614 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
615 MachineBasicBlock &MBB) const {
616 MachineBasicBlock::iterator MBBI = prior(MBB.end());
617 assert(MBBI->getOpcode() == PPC::BLR &&
618 "Can only insert epilog into returning blocks");
620 // Get alignment info so we know how to restore r1
621 const MachineFrameInfo *MFI = MF.getFrameInfo();
622 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
624 // Get the number of bytes allocated from the FrameInfo.
625 unsigned NumBytes = MFI->getStackSize();
626 unsigned GPRSize = 4;
629 // If this function has a frame pointer, load the saved stack pointer from
632 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
633 .addImm(GPRSize).addReg(PPC::R31);
636 // The loaded (or persistent) stack pointer value is offseted by the 'stwu'
637 // on entry to the function. Add this offset back now.
638 if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) {
639 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
640 .addReg(PPC::R1).addImm(NumBytes);
642 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addImm(0).addReg(PPC::R1);
647 unsigned PPCRegisterInfo::getRARegister() const {
651 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
652 return hasFP(MF) ? PPC::R31 : PPC::R1;
655 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves)
657 // Initial state is the frame pointer is R1.
658 MachineLocation Dst(MachineLocation::VirtualFP);
659 MachineLocation Src(PPC::R1, 0);
660 Moves.push_back(new MachineMove(0, Dst, Src));
663 #include "PPCGenRegisterInfo.inc"