1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "reginfo"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCRegisterInfo.h"
20 #include "PPCFrameInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Type.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/CodeGen/SelectionDAGNodes.h"
33 #include "llvm/Target/TargetFrameInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/ADT/BitVector.h"
41 #include "llvm/ADT/STLExtras.h"
45 // FIXME This disables some code that aligns the stack to a boundary
46 // bigger than the default (16 bytes on Darwin) when there is a stack local
47 // of greater alignment. This does not currently work, because the delta
48 // between old and new stack pointers is added to offsets that reference
49 // incoming parameters after the prolog is generated, and the code that
50 // does that doesn't handle a variable delta. You don't want to do that
51 // anyway; a better approach is to reserve another register that retains
52 // to the incoming stack pointer, and reference parameters relative to that.
55 // FIXME (64-bit): Eventually enable by default.
56 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger",
58 cl::desc("Enable PPC32 register scavenger"),
60 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger",
62 cl::desc("Enable PPC64 register scavenger"),
64 #define EnableRegisterScavenging \
65 ((EnablePPC32RS && !Subtarget.isPPC64()) || \
66 (EnablePPC64RS && Subtarget.isPPC64()))
68 // FIXME (64-bit): Should be inlined.
70 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
71 return EnableRegisterScavenging;
74 /// getRegisterNumbering - Given the enum value for some register, e.g.
75 /// PPC::F14, return the number that it corresponds to (e.g. 14).
76 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
80 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0;
81 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1;
82 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2;
83 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3;
84 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4;
85 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5;
86 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6;
87 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7;
88 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8;
89 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9;
90 case R10: case X10: case F10: case V10: case CR2EQ: return 10;
91 case R11: case X11: case F11: case V11: case CR2UN: return 11;
92 case R12: case X12: case F12: case V12: case CR3LT: return 12;
93 case R13: case X13: case F13: case V13: case CR3GT: return 13;
94 case R14: case X14: case F14: case V14: case CR3EQ: return 14;
95 case R15: case X15: case F15: case V15: case CR3UN: return 15;
96 case R16: case X16: case F16: case V16: case CR4LT: return 16;
97 case R17: case X17: case F17: case V17: case CR4GT: return 17;
98 case R18: case X18: case F18: case V18: case CR4EQ: return 18;
99 case R19: case X19: case F19: case V19: case CR4UN: return 19;
100 case R20: case X20: case F20: case V20: case CR5LT: return 20;
101 case R21: case X21: case F21: case V21: case CR5GT: return 21;
102 case R22: case X22: case F22: case V22: case CR5EQ: return 22;
103 case R23: case X23: case F23: case V23: case CR5UN: return 23;
104 case R24: case X24: case F24: case V24: case CR6LT: return 24;
105 case R25: case X25: case F25: case V25: case CR6GT: return 25;
106 case R26: case X26: case F26: case V26: case CR6EQ: return 26;
107 case R27: case X27: case F27: case V27: case CR6UN: return 27;
108 case R28: case X28: case F28: case V28: case CR7LT: return 28;
109 case R29: case X29: case F29: case V29: case CR7GT: return 29;
110 case R30: case X30: case F30: case V30: case CR7EQ: return 30;
111 case R31: case X31: case F31: case V31: case CR7UN: return 31;
113 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
118 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
119 const TargetInstrInfo &tii)
120 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
121 Subtarget(ST), TII(tii) {
122 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
123 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
124 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
125 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
126 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
127 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
128 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
129 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
132 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
133 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
134 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
135 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
136 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
140 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
141 // 32-bit Darwin calling convention.
142 static const unsigned Macho32_CalleeSavedRegs[] = {
143 PPC::R13, PPC::R14, PPC::R15,
144 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
145 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
146 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
147 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
149 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
150 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
151 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
152 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
155 PPC::CR2, PPC::CR3, PPC::CR4,
156 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
157 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
158 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
160 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
161 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
162 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
167 static const unsigned ELF32_CalleeSavedRegs[] = {
168 PPC::R13, PPC::R14, PPC::R15,
169 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
170 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
171 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
172 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
175 PPC::F10, PPC::F11, PPC::F12, PPC::F13,
176 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
177 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
178 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
179 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
182 PPC::CR2, PPC::CR3, PPC::CR4,
183 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
184 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
185 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
187 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
188 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
189 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
193 // 64-bit Darwin calling convention.
194 static const unsigned Macho64_CalleeSavedRegs[] = {
196 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
197 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
198 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
199 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
201 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
202 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
203 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
204 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
207 PPC::CR2, PPC::CR3, PPC::CR4,
208 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
209 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
210 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
212 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
213 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
214 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
219 if (Subtarget.isMachoABI())
220 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs :
221 Macho32_CalleeSavedRegs;
224 return ELF32_CalleeSavedRegs;
227 const TargetRegisterClass* const*
228 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
229 // 32-bit Macho calling convention.
230 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
231 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
232 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
233 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
234 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
235 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
237 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
238 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
239 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
240 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
241 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
243 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
245 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
246 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
247 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
249 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
250 &PPC::CRBITRCRegClass,
251 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
252 &PPC::CRBITRCRegClass,
253 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
254 &PPC::CRBITRCRegClass,
256 &PPC::GPRCRegClass, 0
259 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = {
260 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
261 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
262 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
263 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
264 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
267 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
268 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
269 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
270 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
271 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
272 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
274 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
276 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
277 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
278 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
280 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
281 &PPC::CRBITRCRegClass,
282 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
283 &PPC::CRBITRCRegClass,
284 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
285 &PPC::CRBITRCRegClass,
287 &PPC::GPRCRegClass, 0
290 // 64-bit Macho calling convention.
291 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = {
292 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
293 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
294 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
295 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
296 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
298 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
299 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
300 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
301 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
302 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
304 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
306 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
307 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
308 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
310 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
311 &PPC::CRBITRCRegClass,
312 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
313 &PPC::CRBITRCRegClass,
314 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
315 &PPC::CRBITRCRegClass,
317 &PPC::G8RCRegClass, 0
320 if (Subtarget.isMachoABI())
321 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses :
322 Macho32_CalleeSavedRegClasses;
325 return ELF32_CalleeSavedRegClasses;
328 // needsFP - Return true if the specified function should have a dedicated frame
329 // pointer register. This is true if the function has variable sized allocas or
330 // if frame pointer elimination is disabled.
332 static bool needsFP(const MachineFunction &MF) {
333 const MachineFrameInfo *MFI = MF.getFrameInfo();
334 return NoFramePointerElim || MFI->hasVarSizedObjects();
337 static bool spillsCR(const MachineFunction &MF) {
338 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
339 return FuncInfo->isCRSpilled();
342 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
343 BitVector Reserved(getNumRegs());
344 Reserved.set(PPC::R0);
345 Reserved.set(PPC::R1);
346 Reserved.set(PPC::LR);
347 Reserved.set(PPC::LR8);
349 // In Linux, r2 is reserved for the OS.
350 if (!Subtarget.isDarwin())
351 Reserved.set(PPC::R2);
353 // On PPC64, r13 is the thread pointer. Never allocate this register. Note
354 // that this is over conservative, as it also prevents allocation of R31 when
355 // the FP is not needed.
356 if (Subtarget.isPPC64()) {
357 Reserved.set(PPC::R13);
358 Reserved.set(PPC::R31);
360 if (!EnableRegisterScavenging)
361 Reserved.set(PPC::R0); // FIXME (64-bit): Remove
363 Reserved.set(PPC::X0);
364 Reserved.set(PPC::X1);
365 Reserved.set(PPC::X13);
366 Reserved.set(PPC::X31);
370 Reserved.set(PPC::R31);
375 //===----------------------------------------------------------------------===//
376 // Stack Frame Processing methods
377 //===----------------------------------------------------------------------===//
379 // hasFP - Return true if the specified function actually has a dedicated frame
380 // pointer register. This is true if the function needs a frame pointer and has
381 // a non-zero stack size.
382 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
383 const MachineFrameInfo *MFI = MF.getFrameInfo();
384 return MFI->getStackSize() && needsFP(MF);
387 /// MustSaveLR - Return true if this function requires that we save the LR
388 /// register onto the stack in the prolog and restore it in the epilog of the
390 static bool MustSaveLR(const MachineFunction &MF) {
391 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
393 // We need an save/restore of LR if there is any use/def of LR explicitly, or
394 // if there is some use of the LR stack slot (e.g. for builtin_return_address.
395 return MFI->usesLR() || MFI->isLRStoreRequired() ||
396 // FIXME: Anything that has a call should clobber the LR register,
397 // isn't this redundant??
398 MF.getFrameInfo()->hasCalls();
401 void PPCRegisterInfo::
402 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
403 MachineBasicBlock::iterator I) const {
404 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
408 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered
409 /// register first and then a spilled callee-saved register if that fails.
411 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS,
412 const TargetRegisterClass *RC, int SPAdj) {
413 assert(RS && "Register scavenging must be on");
414 unsigned Reg = RS->FindUnusedReg(RC, true);
415 // FIXME: move ARM callee-saved reg scan to target independent code, then
416 // search for already spilled CS register here.
418 Reg = RS->scavengeRegister(RC, II, SPAdj);
422 /// lowerDynamicAlloc - Generate the code for allocating an object in the
423 /// current frame. The sequence of code with be in the general form
425 /// addi R0, SP, #frameSize ; get the address of the previous frame
426 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
427 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation
429 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
430 int SPAdj, RegScavenger *RS) const {
431 // Get the instruction.
432 MachineInstr &MI = *II;
433 // Get the instruction's basic block.
434 MachineBasicBlock &MBB = *MI.getParent();
435 // Get the basic block's function.
436 MachineFunction &MF = *MBB.getParent();
437 // Get the frame info.
438 MachineFrameInfo *MFI = MF.getFrameInfo();
439 // Determine whether 64-bit pointers are used.
440 bool LP64 = Subtarget.isPPC64();
442 // Get the maximum call stack size.
443 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
444 // Get the total frame size.
445 unsigned FrameSize = MFI->getStackSize();
447 // Get stack alignments.
448 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
449 unsigned MaxAlign = MFI->getMaxAlignment();
450 assert(MaxAlign <= TargetAlign &&
451 "Dynamic alloca with large aligns not supported");
453 // Determine the previous frame's address. If FrameSize can't be
454 // represented as 16 bits or we need special alignment, then we load the
455 // previous frame's address from 0(SP). Why not do an addis of the hi?
456 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
457 // Constructing the constant and adding would take 3 instructions.
458 // Fortunately, a frame greater than 32K is rare.
459 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
460 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
461 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
463 // FIXME (64-bit): Use "findScratchRegister"
465 if (EnableRegisterScavenging)
466 Reg = findScratchRegister(II, RS, RC, SPAdj);
470 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
471 BuildMI(MBB, II, TII.get(PPC::ADDI), Reg)
475 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
476 BuildMI(MBB, II, TII.get(PPC::LD), Reg)
480 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
484 BuildMI(MBB, II, TII.get(PPC::LWZ), Reg)
489 // Grow the stack and update the stack pointer link, then determine the
490 // address of new allocated space.
492 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
493 BuildMI(MBB, II, TII.get(PPC::STDUX))
494 .addReg(Reg, false, false, true)
496 .addReg(MI.getOperand(1).getReg());
498 BuildMI(MBB, II, TII.get(PPC::STDUX))
499 .addReg(PPC::X0, false, false, true)
501 .addReg(MI.getOperand(1).getReg());
503 if (!MI.getOperand(1).isKill())
504 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
506 .addImm(maxCallFrameSize);
508 // Implicitly kill the register.
509 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
511 .addImm(maxCallFrameSize)
512 .addReg(MI.getOperand(1).getReg(), false, true, true);
514 BuildMI(MBB, II, TII.get(PPC::STWUX))
515 .addReg(Reg, false, false, true)
517 .addReg(MI.getOperand(1).getReg());
519 if (!MI.getOperand(1).isKill())
520 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
522 .addImm(maxCallFrameSize);
524 // Implicitly kill the register.
525 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
527 .addImm(maxCallFrameSize)
528 .addReg(MI.getOperand(1).getReg(), false, true, true);
531 // Discard the DYNALLOC instruction.
535 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
536 /// reserving a whole register (R0), we scrounge for one here. This generates
539 /// mfcr rA ; Move the conditional register into GPR rA.
540 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
541 /// stw rA, FI ; Store rA to the frame.
543 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
544 unsigned FrameIndex, int SPAdj,
545 RegScavenger *RS) const {
546 // Get the instruction.
547 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI>
548 // Get the instruction's basic block.
549 MachineBasicBlock &MBB = *MI.getParent();
551 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
552 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
553 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
554 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
556 // We need to store the CR in the low 4-bits of the saved value. First, issue
557 // an MFCR to save all of the CRBits. Add an implicit kill of the CR.
558 if (!MI.getOperand(0).isKill())
559 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg);
561 // Implicitly kill the CR register.
562 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg)
563 .addReg(MI.getOperand(0).getReg(), false, true, true);
565 // If the saved register wasn't CR0, shift the bits left so that they are in
567 unsigned SrcReg = MI.getOperand(0).getReg();
568 if (SrcReg != PPC::CR0)
569 // rlwinm rA, rA, ShiftBits, 0, 31.
570 BuildMI(MBB, II, TII.get(PPC::RLWINM), Reg)
571 .addReg(Reg, false, false, true)
572 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4)
576 addFrameReference(BuildMI(MBB, II, TII.get(PPC::STW))
577 .addReg(Reg, false, false, MI.getOperand(1).getImm()),
580 // Discard the pseudo instruction.
584 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
585 int SPAdj, RegScavenger *RS) const {
586 assert(SPAdj == 0 && "Unexpected");
588 // Get the instruction.
589 MachineInstr &MI = *II;
590 // Get the instruction's basic block.
591 MachineBasicBlock &MBB = *MI.getParent();
592 // Get the basic block's function.
593 MachineFunction &MF = *MBB.getParent();
594 // Get the frame info.
595 MachineFrameInfo *MFI = MF.getFrameInfo();
597 // Find out which operand is the frame index.
598 unsigned FIOperandNo = 0;
599 while (!MI.getOperand(FIOperandNo).isFrameIndex()) {
601 assert(FIOperandNo != MI.getNumOperands() &&
602 "Instr doesn't have FrameIndex operand!");
604 // Take into account whether it's an add or mem instruction
605 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
606 if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
607 OffsetOperandNo = FIOperandNo-1;
609 // Get the frame index.
610 int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
612 // Get the frame pointer save index. Users of this index are primarily
613 // DYNALLOC instructions.
614 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
615 int FPSI = FI->getFramePointerSaveIndex();
616 // Get the instruction opcode.
617 unsigned OpC = MI.getOpcode();
619 // Special case for dynamic alloca.
620 if (FPSI && FrameIndex == FPSI &&
621 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
622 lowerDynamicAlloc(II, SPAdj, RS);
626 // Special case for pseudo-op SPILL_CR.
627 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default.
628 if (OpC == PPC::SPILL_CR) {
629 lowerCRSpilling(II, FrameIndex, SPAdj, RS);
633 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
634 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1,
637 // Figure out if the offset in the instruction is shifted right two bits. This
638 // is true for instructions like "STD", which the machine implicitly adds two
640 bool isIXAddr = false;
650 // Now add the frame object offset to the offset from r1.
651 int Offset = MFI->getObjectOffset(FrameIndex);
653 Offset += MI.getOperand(OffsetOperandNo).getImm();
655 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
657 // If we're not using a Frame Pointer that has been set to the value of the
658 // SP before having the stack size subtracted from it, then add the stack size
659 // to Offset to get the correct offset.
660 Offset += MFI->getStackSize();
662 // If we can, encode the offset directly into the instruction. If this is a
663 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
664 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
665 // clear can be encoded. This is extremely uncommon, because normally you
666 // only "std" to a stack slot that is at least 4-byte aligned, but it can
667 // happen in invalid code.
668 if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
670 Offset >>= 2; // The actual encoded value has the low two bits zero.
671 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
675 // The offset doesn't fit into a single register, scavenge one to build the
677 // FIXME: figure out what SPAdj is doing here.
679 // FIXME (64-bit): Use "findScratchRegister".
681 if (EnableRegisterScavenging)
682 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
686 // Insert a set of rA with the full offset value before the ld, st, or add
687 BuildMI(MBB, II, TII.get(PPC::LIS), SReg)
688 .addImm(Offset >> 16);
689 BuildMI(MBB, II, TII.get(PPC::ORI), SReg)
690 .addReg(SReg, false, false, true)
693 // Convert into indexed form of the instruction:
695 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
696 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
697 unsigned OperandBase;
699 if (OpC != TargetInstrInfo::INLINEASM) {
700 assert(ImmToIdxMap.count(OpC) &&
701 "No indexed form of load or store available!");
702 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
703 MI.setDesc(TII.get(NewOpcode));
706 OperandBase = OffsetOperandNo;
709 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
710 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
711 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
714 /// VRRegNo - Map from a numbered VR register to its enum value.
716 static const unsigned short VRRegNo[] = {
717 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
718 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
719 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
720 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
723 /// RemoveVRSaveCode - We have found that this function does not need any code
724 /// to manipulate the VRSAVE register, even though it uses vector registers.
725 /// This can happen when the only registers used are known to be live in or out
726 /// of the function. Remove all of the VRSAVE related code from the function.
727 static void RemoveVRSaveCode(MachineInstr *MI) {
728 MachineBasicBlock *Entry = MI->getParent();
729 MachineFunction *MF = Entry->getParent();
731 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
732 MachineBasicBlock::iterator MBBI = MI;
734 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
735 MBBI->eraseFromParent();
737 bool RemovedAllMTVRSAVEs = true;
738 // See if we can find and remove the MTVRSAVE instruction from all of the
740 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
741 // If last instruction is a return instruction, add an epilogue
742 if (!I->empty() && I->back().getDesc().isReturn()) {
743 bool FoundIt = false;
744 for (MBBI = I->end(); MBBI != I->begin(); ) {
746 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
747 MBBI->eraseFromParent(); // remove it.
752 RemovedAllMTVRSAVEs &= FoundIt;
756 // If we found and removed all MTVRSAVE instructions, remove the read of
758 if (RemovedAllMTVRSAVEs) {
760 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
762 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
763 MBBI->eraseFromParent();
766 // Finally, nuke the UPDATE_VRSAVE.
767 MI->eraseFromParent();
770 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
771 // instruction selector. Based on the vector registers that have been used,
772 // transform this into the appropriate ORI instruction.
773 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
774 MachineFunction *MF = MI->getParent()->getParent();
776 unsigned UsedRegMask = 0;
777 for (unsigned i = 0; i != 32; ++i)
778 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
779 UsedRegMask |= 1 << (31-i);
781 // Live in and live out values already must be in the mask, so don't bother
783 for (MachineRegisterInfo::livein_iterator
784 I = MF->getRegInfo().livein_begin(),
785 E = MF->getRegInfo().livein_end(); I != E; ++I) {
786 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
787 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
788 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
790 for (MachineRegisterInfo::liveout_iterator
791 I = MF->getRegInfo().liveout_begin(),
792 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
793 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
794 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
795 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
798 // If no registers are used, turn this into a copy.
799 if (UsedRegMask == 0) {
800 // Remove all VRSAVE code.
801 RemoveVRSaveCode(MI);
805 unsigned SrcReg = MI->getOperand(1).getReg();
806 unsigned DstReg = MI->getOperand(0).getReg();
808 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
809 if (DstReg != SrcReg)
810 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
812 .addImm(UsedRegMask);
814 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
815 .addReg(SrcReg, false, false, true)
816 .addImm(UsedRegMask);
817 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
818 if (DstReg != SrcReg)
819 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
821 .addImm(UsedRegMask >> 16);
823 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
824 .addReg(SrcReg, false, false, true)
825 .addImm(UsedRegMask >> 16);
827 if (DstReg != SrcReg)
828 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
830 .addImm(UsedRegMask >> 16);
832 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
833 .addReg(SrcReg, false, false, true)
834 .addImm(UsedRegMask >> 16);
836 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
837 .addReg(DstReg, false, false, true)
838 .addImm(UsedRegMask & 0xFFFF);
841 // Remove the old UPDATE_VRSAVE instruction.
842 MI->eraseFromParent();
845 /// determineFrameLayout - Determine the size of the frame and maximum call
847 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
848 MachineFrameInfo *MFI = MF.getFrameInfo();
850 // Get the number of bytes to allocate from the FrameInfo
851 unsigned FrameSize = MFI->getStackSize();
853 // Get the alignments provided by the target, and the maximum alignment
854 // (if any) of the fixed frame objects.
855 unsigned MaxAlign = MFI->getMaxAlignment();
856 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
857 unsigned AlignMask = TargetAlign - 1; //
859 // If we are a leaf function, and use up to 224 bytes of stack space,
860 // don't have a frame pointer, calls, or dynamic alloca then we do not need
861 // to adjust the stack pointer (we fit in the Red Zone).
862 if (FrameSize <= 224 && // Fits in red zone.
863 !MFI->hasVarSizedObjects() && // No dynamic alloca.
864 !MFI->hasCalls() && // No calls.
865 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
867 MFI->setStackSize(0);
871 // Get the maximum call frame size of all the calls.
872 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
874 // Maximum call frame needs to be at least big enough for linkage and 8 args.
875 unsigned minCallFrameSize =
876 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
877 Subtarget.isMachoABI());
878 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
880 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
881 // that allocations will be aligned.
882 if (MFI->hasVarSizedObjects())
883 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
885 // Update maximum call frame size.
886 MFI->setMaxCallFrameSize(maxCallFrameSize);
888 // Include call frame size in total.
889 FrameSize += maxCallFrameSize;
891 // Make sure the frame is aligned.
892 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
894 // Update frame info.
895 MFI->setStackSize(FrameSize);
899 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
900 RegScavenger *RS) const {
901 // Save and clear the LR state.
902 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
903 unsigned LR = getRARegister();
904 FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR));
905 MF.getRegInfo().setPhysRegUnused(LR);
907 // Save R31 if necessary
908 int FPSI = FI->getFramePointerSaveIndex();
909 bool IsPPC64 = Subtarget.isPPC64();
910 bool IsELF32_ABI = Subtarget.isELF32_ABI();
911 bool IsMachoABI = Subtarget.isMachoABI();
912 MachineFrameInfo *MFI = MF.getFrameInfo();
914 // If the frame pointer save index hasn't been defined yet.
915 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) &&
917 // Find out what the fix offset of the frame pointer save area.
918 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
920 // Allocate the frame index for frame pointer save area.
921 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
923 FI->setFramePointerSaveIndex(FPSI);
926 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
927 // a large stack, which will require scavenging a register to materialize a
929 // FIXME: this doesn't actually check stack size, so is a bit pessimistic
930 // FIXME: doesn't detect whether or not we need to spill vXX, which requires
933 if (EnableRegisterScavenging) // FIXME (64-bit): Enable.
934 if (needsFP(MF) || spillsCR(MF)) {
935 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
936 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
937 const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC;
938 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
939 RC->getAlignment()));
944 PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
945 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
946 MachineBasicBlock::iterator MBBI = MBB.begin();
947 MachineFrameInfo *MFI = MF.getFrameInfo();
948 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
950 // Prepare for frame info.
951 unsigned FrameLabelId = 0;
953 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
955 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
956 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
957 HandleVRSaveUpdate(MBBI, TII);
962 // Move MBBI back to the beginning of the function.
965 // Work out frame sizes.
966 determineFrameLayout(MF);
967 unsigned FrameSize = MFI->getStackSize();
969 int NegFrameSize = -FrameSize;
971 // Get processor type.
972 bool IsPPC64 = Subtarget.isPPC64();
973 // Get operating system
974 bool IsMachoABI = Subtarget.isMachoABI();
975 // Check if the link register (LR) has been used.
976 bool UsesLR = MustSaveLR(MF);
977 // Do we have a frame pointer for this function?
978 bool HasFP = hasFP(MF) && FrameSize;
980 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
981 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
985 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0);
988 BuildMI(MBB, MBBI, TII.get(PPC::STD))
994 BuildMI(MBB, MBBI, TII.get(PPC::STD))
996 .addImm(LROffset / 4)
1000 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0);
1003 BuildMI(MBB, MBBI, TII.get(PPC::STW))
1009 BuildMI(MBB, MBBI, TII.get(PPC::STW))
1015 // Skip if a leaf routine.
1016 if (!FrameSize) return;
1018 // Get stack alignments.
1019 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1020 unsigned MaxAlign = MFI->getMaxAlignment();
1022 if (MMI && MMI->needsFrameInfo()) {
1023 // Mark effective beginning of when frame pointer becomes valid.
1024 FrameLabelId = MMI->NextLabelID();
1025 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId).addImm(0);
1028 // Adjust stack pointer: r1 += NegFrameSize.
1029 // If there is a preferred stack alignment, align R1 now
1032 if (ALIGN_STACK && MaxAlign > TargetAlign) {
1033 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1034 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1036 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
1039 .addImm(32 - Log2_32(MaxAlign))
1041 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0)
1042 .addReg(PPC::R0, false, false, true)
1043 .addImm(NegFrameSize);
1044 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
1048 } else if (isInt16(NegFrameSize)) {
1049 BuildMI(MBB, MBBI, TII.get(PPC::STWU), PPC::R1)
1051 .addImm(NegFrameSize)
1054 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0)
1055 .addImm(NegFrameSize >> 16);
1056 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0)
1057 .addReg(PPC::R0, false, false, true)
1058 .addImm(NegFrameSize & 0xFFFF);
1059 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
1065 if (ALIGN_STACK && MaxAlign > TargetAlign) {
1066 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1067 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1069 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
1072 .addImm(64 - Log2_32(MaxAlign));
1073 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0)
1075 .addImm(NegFrameSize);
1076 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
1080 } else if (isInt16(NegFrameSize)) {
1081 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
1083 .addImm(NegFrameSize / 4)
1086 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0)
1087 .addImm(NegFrameSize >> 16);
1088 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0)
1089 .addReg(PPC::X0, false, false, true)
1090 .addImm(NegFrameSize & 0xFFFF);
1091 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
1098 if (MMI && MMI->needsFrameInfo()) {
1099 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1102 // Show update of SP.
1103 MachineLocation SPDst(MachineLocation::VirtualFP);
1104 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
1105 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1107 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
1108 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
1112 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
1113 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
1114 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
1117 // Add callee saved registers to move list.
1118 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1119 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1120 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1121 unsigned Reg = CSI[I].getReg();
1122 if (Reg == PPC::LR || Reg == PPC::LR8) continue;
1123 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1124 MachineLocation CSSrc(Reg);
1125 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1128 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
1129 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
1130 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
1132 // Mark effective beginning of when frame pointer is ready.
1133 unsigned ReadyLabelId = MMI->NextLabelID();
1134 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId).addImm(0);
1136 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
1137 (IsPPC64 ? PPC::X1 : PPC::R1));
1138 MachineLocation FPSrc(MachineLocation::VirtualFP);
1139 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1142 // If there is a frame pointer, copy R1 into R31
1145 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31)
1149 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31)
1156 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
1157 MachineBasicBlock &MBB) const {
1158 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1159 assert(MBBI->getOpcode() == PPC::BLR &&
1160 "Can only insert epilog into returning blocks");
1162 // Get alignment info so we know how to restore r1
1163 const MachineFrameInfo *MFI = MF.getFrameInfo();
1164 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1165 unsigned MaxAlign = MFI->getMaxAlignment();
1167 // Get the number of bytes allocated from the FrameInfo.
1168 unsigned FrameSize = MFI->getStackSize();
1170 // Get processor type.
1171 bool IsPPC64 = Subtarget.isPPC64();
1172 // Get operating system
1173 bool IsMachoABI = Subtarget.isMachoABI();
1174 // Check if the link register (LR) has been used.
1175 bool UsesLR = MustSaveLR(MF);
1176 // Do we have a frame pointer for this function?
1177 bool HasFP = hasFP(MF) && FrameSize;
1179 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
1180 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
1183 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
1184 // on entry to the function. Add this offset back now.
1185 if (!Subtarget.isPPC64()) {
1186 if (isInt16(FrameSize) && (!ALIGN_STACK || TargetAlign >= MaxAlign) &&
1187 !MFI->hasVarSizedObjects()) {
1188 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
1189 .addReg(PPC::R1).addImm(FrameSize);
1191 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
1194 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1195 !MFI->hasVarSizedObjects()) {
1196 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
1197 .addReg(PPC::X1).addImm(FrameSize);
1199 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
1206 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0)
1207 .addImm(LROffset/4).addReg(PPC::X1);
1210 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
1211 .addImm(FPOffset/4).addReg(PPC::X1);
1214 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0);
1217 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0)
1218 .addImm(LROffset).addReg(PPC::R1);
1221 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
1222 .addImm(FPOffset).addReg(PPC::R1);
1225 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0);
1229 unsigned PPCRegisterInfo::getRARegister() const {
1230 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
1233 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1234 if (!Subtarget.isPPC64())
1235 return hasFP(MF) ? PPC::R31 : PPC::R1;
1237 return hasFP(MF) ? PPC::X31 : PPC::X1;
1240 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1242 // Initial state of the frame pointer is R1.
1243 MachineLocation Dst(MachineLocation::VirtualFP);
1244 MachineLocation Src(PPC::R1, 0);
1245 Moves.push_back(MachineMove(0, Dst, Src));
1248 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
1249 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
1252 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
1253 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
1256 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1257 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
1258 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1261 #include "PPCGenRegisterInfo.inc"