1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
16 #include "PPCRegisterInfo.h"
17 #include "PPCFixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Support/ErrorHandling.h"
25 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
28 class PPCMCCodeEmitter : public MCCodeEmitter {
29 PPCMCCodeEmitter(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT
30 void operator=(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT
31 const TargetMachine &TM;
35 PPCMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
39 ~PPCMCCodeEmitter() {}
41 unsigned getNumFixupKinds() const { return PPC::NumTargetFixupKinds; }
43 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
44 const static MCFixupKindInfo Infos[] = {
45 // name offset bits flags
46 { "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
47 { "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel },
48 { "fixup_ppc_lo16", 16, 16, 0 },
49 { "fixup_ppc_ha16", 16, 16, 0 },
50 { "fixup_ppc_lo14", 16, 14, 0 }
53 if (Kind < FirstTargetFixupKind)
54 return MCCodeEmitter::getFixupKindInfo(Kind);
56 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
58 return Infos[Kind - FirstTargetFixupKind];
61 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
62 SmallVectorImpl<MCFixup> &Fixups) const;
63 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
64 SmallVectorImpl<MCFixup> &Fixups) const;
65 unsigned getHA16Encoding(const MCInst &MI, unsigned OpNo,
66 SmallVectorImpl<MCFixup> &Fixups) const;
67 unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo,
68 SmallVectorImpl<MCFixup> &Fixups) const;
69 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
70 SmallVectorImpl<MCFixup> &Fixups) const;
71 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
72 SmallVectorImpl<MCFixup> &Fixups) const;
73 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
74 SmallVectorImpl<MCFixup> &Fixups) const;
76 /// getMachineOpValue - Return binary encoding of operand. If the machine
77 /// operand requires relocation, record the relocation and return zero.
78 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
79 SmallVectorImpl<MCFixup> &Fixups) const;
81 // getBinaryCodeForInstr - TableGen'erated function for getting the
82 // binary encoding for an instruction.
83 unsigned getBinaryCodeForInstr(const MCInst &MI,
84 SmallVectorImpl<MCFixup> &Fixups) const;
85 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
86 SmallVectorImpl<MCFixup> &Fixups) const {
87 unsigned Bits = getBinaryCodeForInstr(MI, Fixups);
89 // Output the constant in big endian byte order.
90 for (unsigned i = 0; i != 4; ++i) {
91 OS << (char)(Bits >> 24);
95 ++MCNumEmitted; // Keep track of the # of mi's emitted.
100 } // end anonymous namespace
102 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const Target &, TargetMachine &TM,
104 return new PPCMCCodeEmitter(TM, Ctx);
107 unsigned PPCMCCodeEmitter::
108 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
109 SmallVectorImpl<MCFixup> &Fixups) const {
110 const MCOperand &MO = MI.getOperand(OpNo);
111 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
113 // Add a fixup for the branch target.
114 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
115 (MCFixupKind)PPC::fixup_ppc_br24));
119 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
120 SmallVectorImpl<MCFixup> &Fixups) const {
121 const MCOperand &MO = MI.getOperand(OpNo);
122 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
124 // Add a fixup for the branch target.
125 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
126 (MCFixupKind)PPC::fixup_ppc_brcond14));
130 unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo,
131 SmallVectorImpl<MCFixup> &Fixups) const {
132 const MCOperand &MO = MI.getOperand(OpNo);
133 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
135 // Add a fixup for the branch target.
136 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
137 (MCFixupKind)PPC::fixup_ppc_ha16));
141 unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo,
142 SmallVectorImpl<MCFixup> &Fixups) const {
143 const MCOperand &MO = MI.getOperand(OpNo);
144 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
146 // Add a fixup for the branch target.
147 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
148 (MCFixupKind)PPC::fixup_ppc_lo16));
152 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
153 SmallVectorImpl<MCFixup> &Fixups) const {
154 // Encode (imm, reg) as a memri, which has the low 16-bits as the
155 // displacement and the next 5 bits as the register #.
156 assert(MI.getOperand(OpNo+1).isReg());
157 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
159 const MCOperand &MO = MI.getOperand(OpNo);
161 return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
163 // Add a fixup for the displacement field.
164 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
165 (MCFixupKind)PPC::fixup_ppc_lo16));
170 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
171 SmallVectorImpl<MCFixup> &Fixups) const {
172 // Encode (imm, reg) as a memrix, which has the low 14-bits as the
173 // displacement and the next 5 bits as the register #.
174 assert(MI.getOperand(OpNo+1).isReg());
175 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14;
177 const MCOperand &MO = MI.getOperand(OpNo);
179 return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits;
181 // Add a fixup for the branch target.
182 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
183 (MCFixupKind)PPC::fixup_ppc_lo14));
188 unsigned PPCMCCodeEmitter::
189 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
190 SmallVectorImpl<MCFixup> &Fixups) const {
191 const MCOperand &MO = MI.getOperand(OpNo);
192 assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
193 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
194 return 0x80 >> PPCRegisterInfo::getRegisterNumbering(MO.getReg());
198 unsigned PPCMCCodeEmitter::
199 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
200 SmallVectorImpl<MCFixup> &Fixups) const {
202 assert(MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF);
203 return PPCRegisterInfo::getRegisterNumbering(MO.getReg());
207 "Relocation required in an instruction that we cannot encode!");
212 #include "PPCGenMCCodeEmitter.inc"