1 //===-- PPCJITInfo.cpp - Implement the JIT interfaces for the PowerPC -----===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the JIT interfaces for the 32-bit PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "jit"
15 #include "PPCJITInfo.h"
16 #include "PPCRelocations.h"
17 #include "llvm/CodeGen/MachineCodeEmitter.h"
18 #include "llvm/Config/alloca.h"
19 #include "llvm/Support/Debug.h"
23 static TargetJITInfo::JITCompilerFn JITCompilerFunction;
25 #define BUILD_ADDIS(RD,RS,IMM16) \
26 ((15 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
27 #define BUILD_ORI(RD,RS,UIMM16) \
28 ((24 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
29 #define BUILD_ORIS(RD,RS,UIMM16) \
30 ((25 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
31 #define BUILD_RLDICR(RD,RS,SH,ME) \
32 ((30 << 26) | ((RS) << 21) | ((RD) << 16) | (((SH) & 31) << 11) | \
33 (((ME) & 63) << 6) | (1 << 2) | ((((SH) >> 5) & 1) << 1))
34 #define BUILD_MTSPR(RS,SPR) \
35 ((31 << 26) | ((RS) << 21) | ((SPR) << 16) | (467 << 1))
36 #define BUILD_BCCTRx(BO,BI,LINK) \
37 ((19 << 26) | ((BO) << 21) | ((BI) << 16) | (528 << 1) | ((LINK) & 1))
38 #define BUILD_B(TARGET, LINK) \
39 ((18 << 26) | (((TARGET) & 0x00FFFFFF) << 2) | ((LINK) & 1))
42 #define BUILD_LIS(RD,IMM16) BUILD_ADDIS(RD,0,IMM16)
43 #define BUILD_SLDI(RD,RS,IMM6) BUILD_RLDICR(RD,RS,IMM6,63-IMM6)
44 #define BUILD_MTCTR(RS) BUILD_MTSPR(RS,9)
45 #define BUILD_BCTR(LINK) BUILD_BCCTRx(20,0,LINK)
47 static void EmitBranchToAt(uint64_t At, uint64_t To, bool isCall, bool is64Bit){
48 intptr_t Offset = ((intptr_t)To - (intptr_t)At) >> 2;
49 unsigned *AtI = (unsigned*)(intptr_t)At;
51 if (Offset >= -(1 << 23) && Offset < (1 << 23)) { // In range?
52 AtI[0] = BUILD_B(Offset, isCall); // b/bl target
53 } else if (!is64Bit) {
54 AtI[0] = BUILD_LIS(12, To >> 16); // lis r12, hi16(address)
55 AtI[1] = BUILD_ORI(12, 12, To); // ori r12, r12, lo16(address)
56 AtI[2] = BUILD_MTCTR(12); // mtctr r12
57 AtI[3] = BUILD_BCTR(isCall); // bctr/bctrl
59 AtI[0] = BUILD_LIS(12, To >> 48); // lis r12, hi16(address)
60 AtI[1] = BUILD_ORI(12, 12, To >> 32); // ori r12, r12, lo16(address)
61 AtI[2] = BUILD_SLDI(12, 12, 32); // sldi r12, r12, 32
62 AtI[3] = BUILD_ORIS(12, 12, To >> 16); // oris r12, r12, hi16(address)
63 AtI[4] = BUILD_ORI(12, 12, To); // ori r12, r12, lo16(address)
64 AtI[5] = BUILD_MTCTR(12); // mtctr r12
65 AtI[6] = BUILD_BCTR(isCall); // bctr/bctrl
69 extern "C" void PPC32CompilationCallback();
70 extern "C" void PPC64CompilationCallback();
72 #if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \
74 // CompilationCallback stub - We can't use a C function with inline assembly in
75 // it, because we the prolog/epilog inserted by GCC won't work for us. Instead,
76 // write our own wrapper, which does things our way, so we have complete control
77 // over register saving and restoring.
81 ".globl _PPC32CompilationCallback\n"
82 "_PPC32CompilationCallback:\n"
83 // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the
84 // FIXME: need to save v[0-19] for altivec?
85 // FIXME: could shrink frame
86 // Set up a proper stack frame
90 // Save all int arg registers
91 "stw r10, 204(r1)\n" "stw r9, 200(r1)\n"
92 "stw r8, 196(r1)\n" "stw r7, 192(r1)\n"
93 "stw r6, 188(r1)\n" "stw r5, 184(r1)\n"
94 "stw r4, 180(r1)\n" "stw r3, 176(r1)\n"
95 // Save all call-clobbered FP regs.
96 "stfd f13, 168(r1)\n" "stfd f12, 160(r1)\n"
97 "stfd f11, 152(r1)\n" "stfd f10, 144(r1)\n"
98 "stfd f9, 136(r1)\n" "stfd f8, 128(r1)\n"
99 "stfd f7, 120(r1)\n" "stfd f6, 112(r1)\n"
100 "stfd f5, 104(r1)\n" "stfd f4, 96(r1)\n"
101 "stfd f3, 88(r1)\n" "stfd f2, 80(r1)\n"
103 // Arguments to Compilation Callback:
104 // r3 - our lr (address of the call instruction in stub plus 4)
105 // r4 - stub's lr (address of instruction that called the stub plus 4)
106 // r5 - is64Bit - always 0.
108 "lwz r2, 208(r1)\n" // stub's frame
109 "lwz r4, 8(r2)\n" // stub's lr
110 "li r5, 0\n" // 0 == 32 bit
111 "bl _PPCCompilationCallbackC\n"
113 // Restore all int arg registers
114 "lwz r10, 204(r1)\n" "lwz r9, 200(r1)\n"
115 "lwz r8, 196(r1)\n" "lwz r7, 192(r1)\n"
116 "lwz r6, 188(r1)\n" "lwz r5, 184(r1)\n"
117 "lwz r4, 180(r1)\n" "lwz r3, 176(r1)\n"
118 // Restore all FP arg registers
119 "lfd f13, 168(r1)\n" "lfd f12, 160(r1)\n"
120 "lfd f11, 152(r1)\n" "lfd f10, 144(r1)\n"
121 "lfd f9, 136(r1)\n" "lfd f8, 128(r1)\n"
122 "lfd f7, 120(r1)\n" "lfd f6, 112(r1)\n"
123 "lfd f5, 104(r1)\n" "lfd f4, 96(r1)\n"
124 "lfd f3, 88(r1)\n" "lfd f2, 80(r1)\n"
126 // Pop 3 frames off the stack and branch to target
133 void PPC32CompilationCallback() {
134 assert(0 && "This is not a power pc, you can't execute this!");
139 #if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \
144 ".globl _PPC64CompilationCallback\n"
145 "_PPC64CompilationCallback:\n"
146 // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the
147 // FIXME: need to save v[0-19] for altivec?
148 // Set up a proper stack frame
149 "stdu r1, -208(r1)\n"
152 // Save all int arg registers
153 "std r10, 200(r1)\n" "std r9, 192(r1)\n"
154 "std r8, 184(r1)\n" "std r7, 176(r1)\n"
155 "std r6, 168(r1)\n" "std r5, 160(r1)\n"
156 "std r4, 152(r1)\n" "std r3, 144(r1)\n"
157 // Save all call-clobbered FP regs.
158 "stfd f13, 136(r1)\n" "stfd f12, 128(r1)\n"
159 "stfd f11, 120(r1)\n" "stfd f10, 112(r1)\n"
160 "stfd f9, 104(r1)\n" "stfd f8, 96(r1)\n"
161 "stfd f7, 88(r1)\n" "stfd f6, 80(r1)\n"
162 "stfd f5, 72(r1)\n" "stfd f4, 64(r1)\n"
163 "stfd f3, 56(r1)\n" "stfd f2, 48(r1)\n"
165 // Arguments to Compilation Callback:
166 // r3 - our lr (address of the call instruction in stub plus 4)
167 // r4 - stub's lr (address of instruction that called the stub plus 4)
168 // r5 - is64Bit - always 1.
170 "ld r2, 208(r1)\n" // stub's frame
171 "ld r4, 16(r2)\n" // stub's lr
172 "li r5, 1\n" // 1 == 64 bit
173 "bl _PPCCompilationCallbackC\n"
175 // Restore all int arg registers
176 "ld r10, 200(r1)\n" "ld r9, 192(r1)\n"
177 "ld r8, 184(r1)\n" "ld r7, 176(r1)\n"
178 "ld r6, 168(r1)\n" "ld r5, 160(r1)\n"
179 "ld r4, 152(r1)\n" "ld r3, 144(r1)\n"
180 // Restore all FP arg registers
181 "lfd f13, 136(r1)\n" "lfd f12, 128(r1)\n"
182 "lfd f11, 120(r1)\n" "lfd f10, 112(r1)\n"
183 "lfd f9, 104(r1)\n" "lfd f8, 96(r1)\n"
184 "lfd f7, 88(r1)\n" "lfd f6, 80(r1)\n"
185 "lfd f5, 72(r1)\n" "lfd f4, 64(r1)\n"
186 "lfd f3, 56(r1)\n" "lfd f2, 48(r1)\n"
188 // Pop 3 frames off the stack and branch to target
195 void PPC64CompilationCallback() {
196 assert(0 && "This is not a power pc, you can't execute this!");
201 extern "C" void *PPCCompilationCallbackC(unsigned *StubCallAddrPlus4,
202 unsigned *OrigCallAddrPlus4,
204 // Adjust the pointer to the address of the call instruction in the stub
205 // emitted by emitFunctionStub, rather than the instruction after it.
206 unsigned *StubCallAddr = StubCallAddrPlus4 - 1;
207 unsigned *OrigCallAddr = OrigCallAddrPlus4 - 1;
209 void *Target = JITCompilerFunction(StubCallAddr);
211 // Check to see if *OrigCallAddr is a 'bl' instruction, and if we can rewrite
212 // it to branch directly to the destination. If so, rewrite it so it does not
213 // need to go through the stub anymore.
214 unsigned OrigCallInst = *OrigCallAddr;
215 if ((OrigCallInst >> 26) == 18) { // Direct call.
216 intptr_t Offset = ((intptr_t)Target - (intptr_t)OrigCallAddr) >> 2;
218 if (Offset >= -(1 << 23) && Offset < (1 << 23)) { // In range?
219 // Clear the original target out.
220 OrigCallInst &= (63 << 26) | 3;
221 // Fill in the new target.
222 OrigCallInst |= (Offset & ((1 << 24)-1)) << 2;
224 *OrigCallAddr = OrigCallInst;
228 // Assert that we are coming from a stub that was created with our
230 if ((*StubCallAddr >> 26) == 18)
233 assert((*StubCallAddr >> 26) == 19 && "Call in stub is not indirect!");
234 StubCallAddr -= is64Bit ? 9 : 6;
237 // Rewrite the stub with an unconditional branch to the target, for any users
238 // who took the address of the stub.
239 EmitBranchToAt((intptr_t)StubCallAddr, (intptr_t)Target, false, is64Bit);
241 // Put the address of the target function to call and the address to return to
242 // after calling the target function in a place that is easy to get on the
243 // stack after we restore all regs.
249 TargetJITInfo::LazyResolverFn
250 PPCJITInfo::getLazyResolverFunction(JITCompilerFn Fn) {
251 JITCompilerFunction = Fn;
252 return is64Bit ? PPC64CompilationCallback : PPC32CompilationCallback;
255 void *PPCJITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
256 // If this is just a call to an external function, emit a branch instead of a
257 // call. The code is the same except for one bit of the last instruction.
258 if (Fn != (void*)(intptr_t)PPC32CompilationCallback &&
259 Fn != (void*)(intptr_t)PPC64CompilationCallback) {
260 MCE.startFunctionStub(7*4);
261 intptr_t Addr = (intptr_t)MCE.getCurrentPCValue();
269 EmitBranchToAt(Addr, (intptr_t)Fn, false, is64Bit);
270 return MCE.finishFunctionStub(0);
273 MCE.startFunctionStub(10*4);
275 MCE.emitWordBE(0xf821ffb1); // stdu r1,-80(r1)
276 MCE.emitWordBE(0x7d6802a6); // mflr r11
277 MCE.emitWordBE(0xf9610060); // std r11, 96(r1)
279 MCE.emitWordBE(0x9421ffe0); // stwu r1,-32(r1)
280 MCE.emitWordBE(0x7d6802a6); // mflr r11
281 MCE.emitWordBE(0x91610028); // stw r11, 40(r1)
283 intptr_t Addr = (intptr_t)MCE.getCurrentPCValue();
291 EmitBranchToAt(Addr, (intptr_t)Fn, true, is64Bit);
292 return MCE.finishFunctionStub(0);
296 void PPCJITInfo::relocate(void *Function, MachineRelocation *MR,
297 unsigned NumRelocs, unsigned char* GOTBase) {
298 for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
299 unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4;
300 intptr_t ResultPtr = (intptr_t)MR->getResultPointer();
301 switch ((PPC::RelocationType)MR->getRelocationType()) {
302 default: assert(0 && "Unknown relocation type!");
303 case PPC::reloc_pcrel_bx:
304 // PC-relative relocation for b and bl instructions.
305 ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;
306 assert(ResultPtr >= -(1 << 23) && ResultPtr < (1 << 23) &&
307 "Relocation out of range!");
308 *RelocPos |= (ResultPtr & ((1 << 24)-1)) << 2;
310 case PPC::reloc_pcrel_bcx:
311 // PC-relative relocation for BLT,BLE,BEQ,BGE,BGT,BNE, or other
313 ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;
314 assert(ResultPtr >= -(1 << 13) && ResultPtr < (1 << 13) &&
315 "Relocation out of range!");
316 *RelocPos |= (ResultPtr & ((1 << 14)-1)) << 2;
318 case PPC::reloc_absolute_high: // high bits of ref -> low 16 of instr
319 case PPC::reloc_absolute_low: { // low bits of ref -> low 16 of instr
320 ResultPtr += MR->getConstantVal();
322 // If this is a high-part access, get the high-part.
323 if (MR->getRelocationType() == PPC::reloc_absolute_high) {
324 // If the low part will have a carry (really a borrow) from the low
325 // 16-bits into the high 16, add a bit to borrow from.
326 if (((int)ResultPtr << 16) < 0)
327 ResultPtr += 1 << 16;
331 // Do the addition then mask, so the addition does not overflow the 16-bit
332 // immediate section of the instruction.
333 unsigned LowBits = (*RelocPos + ResultPtr) & 65535;
334 unsigned HighBits = *RelocPos & ~65535;
335 *RelocPos = LowBits | HighBits; // Slam into low 16-bits
338 case PPC::reloc_absolute_low_ix: { // low bits of ref -> low 14 of instr
339 ResultPtr += MR->getConstantVal();
340 // Do the addition then mask, so the addition does not overflow the 16-bit
341 // immediate section of the instruction.
342 unsigned LowBits = (*RelocPos + ResultPtr) & 0xFFFC;
343 unsigned HighBits = *RelocPos & 0xFFFF0003;
344 *RelocPos = LowBits | HighBits; // Slam into low 14-bits.
351 void PPCJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
352 EmitBranchToAt((intptr_t)Old, (intptr_t)New, false, is64Bit);