1 //===-- PPCJITInfo.cpp - Implement the JIT interfaces for the PowerPC -----===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the JIT interfaces for the 32-bit PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "jit"
15 #include "PPCJITInfo.h"
16 #include "PPCRelocations.h"
17 #include "llvm/CodeGen/MachineCodeEmitter.h"
18 #include "llvm/Config/alloca.h"
19 #include "llvm/Support/Debug.h"
24 static TargetJITInfo::JITCompilerFn JITCompilerFunction;
26 #define BUILD_ADDIS(RD,RS,IMM16) \
27 ((15 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
28 #define BUILD_ORI(RD,RS,UIMM16) \
29 ((24 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
30 #define BUILD_ORIS(RD,RS,UIMM16) \
31 ((25 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
32 #define BUILD_RLDICR(RD,RS,SH,ME) \
33 ((30 << 26) | ((RS) << 21) | ((RD) << 16) | (((SH) & 31) << 11) | \
34 (((ME) & 63) << 6) | (1 << 3) | (((SH) >> 5) & 1))
35 #define BUILD_MTSPR(RS,SPR) \
36 ((31 << 26) | ((RS) << 21) | ((SPR) << 16) | (467 << 1))
37 #define BUILD_BCCTRx(BO,BI,LINK) \
38 ((19 << 26) | ((BO) << 21) | ((BI) << 16) | (528 << 1) | ((LINK) & 1))
39 #define BUILD_B(TARGET, LINK) \
40 ((18 << 26) | (((TARGET) & 0x00FFFFFF) << 2) | ((LINK) & 1))
43 #define BUILD_LIS(RD,IMM16) BUILD_ADDIS(RD,0,IMM16)
44 #define BUILD_SLDI(RD,RS,IMM6) BUILD_RLDICR(RD,RS,IMM6,63-IMM6)
45 #define BUILD_MTCTR(RS) BUILD_MTSPR(RS,9)
46 #define BUILD_BCTR(LINK) BUILD_BCCTRx(20,0,LINK)
48 static void EmitBranchToAt(uint64_t At, uint64_t To, bool isCall, bool is64Bit){
49 intptr_t Offset = ((intptr_t)To - (intptr_t)At) >> 2;
50 unsigned *AtI = (unsigned*)(intptr_t)At;
52 if (Offset >= -(1 << 23) && Offset < (1 << 23)) { // In range?
53 AtI[0] = BUILD_B(Offset, isCall); // b/bl target
54 } else if (!is64Bit) {
55 AtI[0] = BUILD_LIS(12, To >> 16); // lis r12, hi16(address)
56 AtI[1] = BUILD_ORI(12, 12, To); // ori r12, r12, lo16(address)
57 AtI[2] = BUILD_MTCTR(12); // mtctr r12
58 AtI[3] = BUILD_BCTR(isCall); // bctr/bctrl
60 AtI[0] = BUILD_LIS(12, To >> 48); // lis r12, hi16(address)
61 AtI[1] = BUILD_ORI(12, 12, To >> 32); // ori r12, r12, lo16(address)
62 AtI[2] = BUILD_SLDI(12, 12, 32); // sldi r12, r12, 32
63 AtI[3] = BUILD_ORIS(12, 12, To >> 16); // oris r12, r12, hi16(address)
64 AtI[4] = BUILD_ORI(12, 12, To); // ori r12, r12, lo16(address)
65 AtI[5] = BUILD_MTCTR(12); // mtctr r12
66 AtI[6] = BUILD_BCTR(isCall); // bctr/bctrl
70 extern "C" void PPC32CompilationCallback();
71 extern "C" void PPC64CompilationCallback();
73 #if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \
75 // CompilationCallback stub - We can't use a C function with inline assembly in
76 // it, because we the prolog/epilog inserted by GCC won't work for us. Instead,
77 // write our own wrapper, which does things our way, so we have complete control
78 // over register saving and restoring.
82 ".globl _PPC32CompilationCallback\n"
83 "_PPC32CompilationCallback:\n"
84 // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the
85 // FIXME: need to save v[0-19] for altivec?
86 // FIXME: could shrink frame
87 // Set up a proper stack frame
91 // Save all int arg registers
92 "stw r10, 204(r1)\n" "stw r9, 200(r1)\n"
93 "stw r8, 196(r1)\n" "stw r7, 192(r1)\n"
94 "stw r6, 188(r1)\n" "stw r5, 184(r1)\n"
95 "stw r4, 180(r1)\n" "stw r3, 176(r1)\n"
96 // Save all call-clobbered FP regs.
97 "stfd f13, 168(r1)\n" "stfd f12, 160(r1)\n"
98 "stfd f11, 152(r1)\n" "stfd f10, 144(r1)\n"
99 "stfd f9, 136(r1)\n" "stfd f8, 128(r1)\n"
100 "stfd f7, 120(r1)\n" "stfd f6, 112(r1)\n"
101 "stfd f5, 104(r1)\n" "stfd f4, 96(r1)\n"
102 "stfd f3, 88(r1)\n" "stfd f2, 80(r1)\n"
104 // Arguments to Compilation Callback:
105 // r3 - our lr (address of the call instruction in stub plus 4)
106 // r4 - stub's lr (address of instruction that called the stub plus 4)
108 "lwz r2, 208(r1)\n" // stub's frame
109 "lwz r4, 8(r2)\n" // stub's lr
110 "li r5, 0\n" // 0 == 32 bit
111 "bl _PPCCompilationCallbackC\n"
113 // Restore all int arg registers
114 "lwz r10, 204(r1)\n" "lwz r9, 200(r1)\n"
115 "lwz r8, 196(r1)\n" "lwz r7, 192(r1)\n"
116 "lwz r6, 188(r1)\n" "lwz r5, 184(r1)\n"
117 "lwz r4, 180(r1)\n" "lwz r3, 176(r1)\n"
118 // Restore all FP arg registers
119 "lfd f13, 168(r1)\n" "lfd f12, 160(r1)\n"
120 "lfd f11, 152(r1)\n" "lfd f10, 144(r1)\n"
121 "lfd f9, 136(r1)\n" "lfd f8, 128(r1)\n"
122 "lfd f7, 120(r1)\n" "lfd f6, 112(r1)\n"
123 "lfd f5, 104(r1)\n" "lfd f4, 96(r1)\n"
124 "lfd f3, 88(r1)\n" "lfd f2, 80(r1)\n"
126 // Pop 3 frames off the stack and branch to target
133 void PPC32CompilationCallback() {
134 assert(0 && "This is not a power pc, you can't execute this!");
139 #if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \
144 ".globl _PPC64CompilationCallback\n"
145 "_PPC64CompilationCallback:\n"
146 // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the
147 // FIXME: need to save v[0-19] for altivec?
148 // Set up a proper stack frame
149 "stdu r1, -208(r1)\n"
152 // Save all int arg registers
153 "std r10, 200(r1)\n" "std r9, 192(r1)\n"
154 "std r8, 184(r1)\n" "std r7, 176(r1)\n"
155 "std r6, 168(r1)\n" "std r5, 160(r1)\n"
156 "std r4, 152(r1)\n" "std r3, 144(r1)\n"
157 // Save all call-clobbered FP regs.
158 "stfd f13, 136(r1)\n" "stfd f12, 128(r1)\n"
159 "stfd f11, 120(r1)\n" "stfd f10, 112(r1)\n"
160 "stfd f9, 104(r1)\n" "stfd f8, 96(r1)\n"
161 "stfd f7, 88(r1)\n" "stfd f6, 80(r1)\n"
162 "stfd f5, 72(r1)\n" "stfd f4, 64(r1)\n"
163 "stfd f3, 56(r1)\n" "stfd f2, 48(r1)\n"
165 // Arguments to Compilation Callback:
166 // r3 - our lr (address of the call instruction in stub plus 4)
167 // r4 - stub's lr (address of instruction that called the stub plus 4)
169 "ld r2, 208(r1)\n" // stub's frame
170 "ld r4, 16(r2)\n" // stub's lr
171 "li r5, 1\n" // 1 == 64 bit
172 "bl _PPCCompilationCallbackC\n"
174 // Restore all int arg registers
175 "ld r10, 200(r1)\n" "ld r9, 192(r1)\n"
176 "ld r8, 184(r1)\n" "ld r7, 176(r1)\n"
177 "ld r6, 168(r1)\n" "ld r5, 160(r1)\n"
178 "ld r4, 152(r1)\n" "ld r3, 144(r1)\n"
179 // Restore all FP arg registers
180 "lfd f13, 136(r1)\n" "lfd f12, 128(r1)\n"
181 "lfd f11, 120(r1)\n" "lfd f10, 112(r1)\n"
182 "lfd f9, 104(r1)\n" "lfd f8, 96(r1)\n"
183 "lfd f7, 88(r1)\n" "lfd f6, 80(r1)\n"
184 "lfd f5, 72(r1)\n" "lfd f4, 64(r1)\n"
185 "lfd f3, 56(r1)\n" "lfd f2, 48(r1)\n"
187 // Pop 3 frames off the stack and branch to target
194 void PPC64CompilationCallback() {
195 assert(0 && "This is not a power pc, you can't execute this!");
200 extern "C" void *PPCCompilationCallbackC(unsigned *StubCallAddrPlus4,
201 unsigned *OrigCallAddrPlus4,
203 // Adjust the pointer to the address of the call instruction in the stub
204 // emitted by emitFunctionStub, rather than the instruction after it.
205 unsigned *StubCallAddr = StubCallAddrPlus4 - 1;
206 unsigned *OrigCallAddr = OrigCallAddrPlus4 - 1;
208 void *Target = JITCompilerFunction(StubCallAddr);
210 // Check to see if *OrigCallAddr is a 'bl' instruction, and if we can rewrite
211 // it to branch directly to the destination. If so, rewrite it so it does not
212 // need to go through the stub anymore.
213 unsigned OrigCallInst = *OrigCallAddr;
214 if ((OrigCallInst >> 26) == 18) { // Direct call.
215 intptr_t Offset = ((intptr_t)Target - (intptr_t)OrigCallAddr) >> 2;
217 if (Offset >= -(1 << 23) && Offset < (1 << 23)) { // In range?
218 // Clear the original target out.
219 OrigCallInst &= (63 << 26) | 3;
220 // Fill in the new target.
221 OrigCallInst |= (Offset & ((1 << 24)-1)) << 2;
223 *OrigCallAddr = OrigCallInst;
227 // Assert that we are coming from a stub that was created with our
229 if ((*StubCallAddr >> 26) == 18)
232 assert((*StubCallAddr >> 26) == 19 && "Call in stub is not indirect!");
233 StubCallAddr -= is64Bit ? 9 : 6;
236 // Rewrite the stub with an unconditional branch to the target, for any users
237 // who took the address of the stub.
238 EmitBranchToAt((intptr_t)StubCallAddr, (intptr_t)Target, false, is64Bit);
240 // Put the address of the target function to call and the address to return to
241 // after calling the target function in a place that is easy to get on the
242 // stack after we restore all regs.
248 TargetJITInfo::LazyResolverFn
249 PPCJITInfo::getLazyResolverFunction(JITCompilerFn Fn) {
250 JITCompilerFunction = Fn;
251 return is64Bit ? PPC64CompilationCallback : PPC32CompilationCallback;
254 void *PPCJITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
255 // If this is just a call to an external function, emit a branch instead of a
256 // call. The code is the same except for one bit of the last instruction.
257 if (Fn != (void*)(intptr_t)PPC32CompilationCallback &&
258 Fn != (void*)(intptr_t)PPC64CompilationCallback) {
259 MCE.startFunctionStub(7*4);
260 intptr_t Addr = (intptr_t)MCE.getCurrentPCValue();
268 EmitBranchToAt(Addr, (intptr_t)Fn, false, is64Bit);
269 return MCE.finishFunctionStub(0);
272 MCE.startFunctionStub(10*4);
274 MCE.emitWordBE(0xf821ffb1); // stdu r1,-80(r1)
275 MCE.emitWordBE(0x7d6802a6); // mflr r11
276 MCE.emitWordBE(0xf9610060); // std r11, 96(r1)
278 MCE.emitWordBE(0x9421ffe0); // stwu r1,-32(r1)
279 MCE.emitWordBE(0x7d6802a6); // mflr r11
280 MCE.emitWordBE(0x91610028); // stw r11, 40(r1)
282 intptr_t Addr = (intptr_t)MCE.getCurrentPCValue();
290 EmitBranchToAt(Addr, (intptr_t)Fn, true, is64Bit);
291 return MCE.finishFunctionStub(0);
295 void PPCJITInfo::relocate(void *Function, MachineRelocation *MR,
296 unsigned NumRelocs, unsigned char* GOTBase) {
297 for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
298 unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4;
299 intptr_t ResultPtr = (intptr_t)MR->getResultPointer();
300 switch ((PPC::RelocationType)MR->getRelocationType()) {
301 default: assert(0 && "Unknown relocation type!");
302 case PPC::reloc_pcrel_bx:
303 // PC-relative relocation for b and bl instructions.
304 ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;
305 assert(ResultPtr >= -(1 << 23) && ResultPtr < (1 << 23) &&
306 "Relocation out of range!");
307 *RelocPos |= (ResultPtr & ((1 << 24)-1)) << 2;
309 case PPC::reloc_pcrel_bcx:
310 // PC-relative relocation for BLT,BLE,BEQ,BGE,BGT,BNE, or other
312 ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;
313 assert(ResultPtr >= -(1 << 13) && ResultPtr < (1 << 13) &&
314 "Relocation out of range!");
315 *RelocPos |= (ResultPtr & ((1 << 14)-1)) << 2;
317 case PPC::reloc_absolute_high: // high bits of ref -> low 16 of instr
318 case PPC::reloc_absolute_low: { // low bits of ref -> low 16 of instr
319 ResultPtr += MR->getConstantVal();
321 // If this is a high-part access, get the high-part.
322 if (MR->getRelocationType() == PPC::reloc_absolute_high) {
323 // If the low part will have a carry (really a borrow) from the low
324 // 16-bits into the high 16, add a bit to borrow from.
325 if (((int)ResultPtr << 16) < 0)
326 ResultPtr += 1 << 16;
330 // Do the addition then mask, so the addition does not overflow the 16-bit
331 // immediate section of the instruction.
332 unsigned LowBits = (*RelocPos + ResultPtr) & 65535;
333 unsigned HighBits = *RelocPos & ~65535;
334 *RelocPos = LowBits | HighBits; // Slam into low 16-bits
337 case PPC::reloc_absolute_low_ix: { // low bits of ref -> low 14 of instr
338 ResultPtr += MR->getConstantVal();
339 // Do the addition then mask, so the addition does not overflow the 16-bit
340 // immediate section of the instruction.
341 unsigned LowBits = (*RelocPos + ResultPtr) & 0xFFFC;
342 unsigned HighBits = *RelocPos & 0xFFFF0003;
343 *RelocPos = LowBits | HighBits; // Slam into low 14-bits.
350 void PPCJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
351 EmitBranchToAt((intptr_t)Old, (intptr_t)New, false, is64Bit);