1 //===- PPCInstrVSX.td - The PowerPC VSX Extension --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the VSX extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 // *********************************** NOTE ***********************************
15 // ** For POWER8 Little Endian, the VSX swap optimization relies on knowing **
16 // ** which VMX and VSX instructions are lane-sensitive and which are not. **
17 // ** A lane-sensitive instruction relies, implicitly or explicitly, on **
18 // ** whether lanes are numbered from left to right. An instruction like **
19 // ** VADDFP is not lane-sensitive, because each lane of the result vector **
20 // ** relies only on the corresponding lane of the source vectors. However, **
21 // ** an instruction like VMULESB is lane-sensitive, because "even" and **
22 // ** "odd" lanes are different for big-endian and little-endian numbering. **
24 // ** When adding new VMX and VSX instructions, please consider whether they **
25 // ** are lane-sensitive. If so, they must be added to a switch statement **
26 // ** in PPCVSXSwapRemoval::gatherVectorInstructions(). **
27 // ****************************************************************************
29 def PPCRegVSRCAsmOperand : AsmOperandClass {
30 let Name = "RegVSRC"; let PredicateMethod = "isVSRegNumber";
32 def vsrc : RegisterOperand<VSRC> {
33 let ParserMatchClass = PPCRegVSRCAsmOperand;
36 def PPCRegVSFRCAsmOperand : AsmOperandClass {
37 let Name = "RegVSFRC"; let PredicateMethod = "isVSRegNumber";
39 def vsfrc : RegisterOperand<VSFRC> {
40 let ParserMatchClass = PPCRegVSFRCAsmOperand;
43 def PPCRegVSSRCAsmOperand : AsmOperandClass {
44 let Name = "RegVSSRC"; let PredicateMethod = "isVSRegNumber";
46 def vssrc : RegisterOperand<VSSRC> {
47 let ParserMatchClass = PPCRegVSSRCAsmOperand;
50 // Little-endian-specific nodes.
51 def SDT_PPClxvd2x : SDTypeProfile<1, 1, [
52 SDTCisVT<0, v2f64>, SDTCisPtrTy<1>
54 def SDT_PPCstxvd2x : SDTypeProfile<0, 2, [
55 SDTCisVT<0, v2f64>, SDTCisPtrTy<1>
57 def SDT_PPCxxswapd : SDTypeProfile<1, 1, [
61 def PPClxvd2x : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x,
62 [SDNPHasChain, SDNPMayLoad]>;
63 def PPCstxvd2x : SDNode<"PPCISD::STXVD2X", SDT_PPCstxvd2x,
64 [SDNPHasChain, SDNPMayStore]>;
65 def PPCxxswapd : SDNode<"PPCISD::XXSWAPD", SDT_PPCxxswapd, [SDNPHasChain]>;
66 def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
67 def PPCmtvsra : SDNode<"PPCISD::MTVSRA", SDTUnaryOp, []>;
68 def PPCmtvsrz : SDNode<"PPCISD::MTVSRZ", SDTUnaryOp, []>;
70 multiclass XX3Form_Rcr<bits<6> opcode, bits<7> xo, dag OOL, dag IOL,
71 string asmbase, string asmstr, InstrItinClass itin,
73 let BaseName = asmbase in {
74 def NAME : XX3Form_Rc<opcode, xo, OOL, IOL,
75 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
78 def o : XX3Form_Rc<opcode, xo, OOL, IOL,
79 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
84 def HasVSX : Predicate<"PPCSubTarget->hasVSX()">;
85 def IsLittleEndian : Predicate<"PPCSubTarget->isLittleEndian()">;
86 def IsBigEndian : Predicate<"!PPCSubTarget->isLittleEndian()">;
88 let Predicates = [HasVSX] in {
89 let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
90 let hasSideEffects = 0 in { // VSX instructions don't have side effects.
93 // Load indexed instructions
95 def LXSDX : XX1Form<31, 588,
96 (outs vsfrc:$XT), (ins memrr:$src),
97 "lxsdx $XT, $src", IIC_LdStLFD,
98 [(set f64:$XT, (load xoaddr:$src))]>;
100 def LXVD2X : XX1Form<31, 844,
101 (outs vsrc:$XT), (ins memrr:$src),
102 "lxvd2x $XT, $src", IIC_LdStLFD,
103 [(set v2f64:$XT, (int_ppc_vsx_lxvd2x xoaddr:$src))]>;
105 def LXVDSX : XX1Form<31, 332,
106 (outs vsrc:$XT), (ins memrr:$src),
107 "lxvdsx $XT, $src", IIC_LdStLFD, []>;
109 def LXVW4X : XX1Form<31, 780,
110 (outs vsrc:$XT), (ins memrr:$src),
111 "lxvw4x $XT, $src", IIC_LdStLFD,
112 [(set v4i32:$XT, (int_ppc_vsx_lxvw4x xoaddr:$src))]>;
115 // Store indexed instructions
116 let mayStore = 1 in {
117 def STXSDX : XX1Form<31, 716,
118 (outs), (ins vsfrc:$XT, memrr:$dst),
119 "stxsdx $XT, $dst", IIC_LdStSTFD,
120 [(store f64:$XT, xoaddr:$dst)]>;
122 def STXVD2X : XX1Form<31, 972,
123 (outs), (ins vsrc:$XT, memrr:$dst),
124 "stxvd2x $XT, $dst", IIC_LdStSTFD,
125 [(store v2f64:$XT, xoaddr:$dst)]>;
127 def STXVW4X : XX1Form<31, 908,
128 (outs), (ins vsrc:$XT, memrr:$dst),
129 "stxvw4x $XT, $dst", IIC_LdStSTFD,
130 [(store v4i32:$XT, xoaddr:$dst)]>;
134 // Add/Mul Instructions
135 let isCommutable = 1 in {
136 def XSADDDP : XX3Form<60, 32,
137 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
138 "xsadddp $XT, $XA, $XB", IIC_VecFP,
139 [(set f64:$XT, (fadd f64:$XA, f64:$XB))]>;
140 def XSMULDP : XX3Form<60, 48,
141 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
142 "xsmuldp $XT, $XA, $XB", IIC_VecFP,
143 [(set f64:$XT, (fmul f64:$XA, f64:$XB))]>;
145 def XVADDDP : XX3Form<60, 96,
146 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
147 "xvadddp $XT, $XA, $XB", IIC_VecFP,
148 [(set v2f64:$XT, (fadd v2f64:$XA, v2f64:$XB))]>;
150 def XVADDSP : XX3Form<60, 64,
151 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
152 "xvaddsp $XT, $XA, $XB", IIC_VecFP,
153 [(set v4f32:$XT, (fadd v4f32:$XA, v4f32:$XB))]>;
155 def XVMULDP : XX3Form<60, 112,
156 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
157 "xvmuldp $XT, $XA, $XB", IIC_VecFP,
158 [(set v2f64:$XT, (fmul v2f64:$XA, v2f64:$XB))]>;
160 def XVMULSP : XX3Form<60, 80,
161 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
162 "xvmulsp $XT, $XA, $XB", IIC_VecFP,
163 [(set v4f32:$XT, (fmul v4f32:$XA, v4f32:$XB))]>;
166 // Subtract Instructions
167 def XSSUBDP : XX3Form<60, 40,
168 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
169 "xssubdp $XT, $XA, $XB", IIC_VecFP,
170 [(set f64:$XT, (fsub f64:$XA, f64:$XB))]>;
172 def XVSUBDP : XX3Form<60, 104,
173 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
174 "xvsubdp $XT, $XA, $XB", IIC_VecFP,
175 [(set v2f64:$XT, (fsub v2f64:$XA, v2f64:$XB))]>;
176 def XVSUBSP : XX3Form<60, 72,
177 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
178 "xvsubsp $XT, $XA, $XB", IIC_VecFP,
179 [(set v4f32:$XT, (fsub v4f32:$XA, v4f32:$XB))]>;
182 let BaseName = "XSMADDADP" in {
183 let isCommutable = 1 in
184 def XSMADDADP : XX3Form<60, 33,
185 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
186 "xsmaddadp $XT, $XA, $XB", IIC_VecFP,
187 [(set f64:$XT, (fma f64:$XA, f64:$XB, f64:$XTi))]>,
188 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
190 let IsVSXFMAAlt = 1 in
191 def XSMADDMDP : XX3Form<60, 41,
192 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
193 "xsmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
194 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
198 let BaseName = "XSMSUBADP" in {
199 let isCommutable = 1 in
200 def XSMSUBADP : XX3Form<60, 49,
201 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
202 "xsmsubadp $XT, $XA, $XB", IIC_VecFP,
203 [(set f64:$XT, (fma f64:$XA, f64:$XB, (fneg f64:$XTi)))]>,
204 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
206 let IsVSXFMAAlt = 1 in
207 def XSMSUBMDP : XX3Form<60, 57,
208 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
209 "xsmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
210 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
214 let BaseName = "XSNMADDADP" in {
215 let isCommutable = 1 in
216 def XSNMADDADP : XX3Form<60, 161,
217 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
218 "xsnmaddadp $XT, $XA, $XB", IIC_VecFP,
219 [(set f64:$XT, (fneg (fma f64:$XA, f64:$XB, f64:$XTi)))]>,
220 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
222 let IsVSXFMAAlt = 1 in
223 def XSNMADDMDP : XX3Form<60, 169,
224 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
225 "xsnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
226 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
230 let BaseName = "XSNMSUBADP" in {
231 let isCommutable = 1 in
232 def XSNMSUBADP : XX3Form<60, 177,
233 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
234 "xsnmsubadp $XT, $XA, $XB", IIC_VecFP,
235 [(set f64:$XT, (fneg (fma f64:$XA, f64:$XB, (fneg f64:$XTi))))]>,
236 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
238 let IsVSXFMAAlt = 1 in
239 def XSNMSUBMDP : XX3Form<60, 185,
240 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
241 "xsnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
242 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
246 let BaseName = "XVMADDADP" in {
247 let isCommutable = 1 in
248 def XVMADDADP : XX3Form<60, 97,
249 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
250 "xvmaddadp $XT, $XA, $XB", IIC_VecFP,
251 [(set v2f64:$XT, (fma v2f64:$XA, v2f64:$XB, v2f64:$XTi))]>,
252 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
254 let IsVSXFMAAlt = 1 in
255 def XVMADDMDP : XX3Form<60, 105,
256 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
257 "xvmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
258 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
262 let BaseName = "XVMADDASP" in {
263 let isCommutable = 1 in
264 def XVMADDASP : XX3Form<60, 65,
265 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
266 "xvmaddasp $XT, $XA, $XB", IIC_VecFP,
267 [(set v4f32:$XT, (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi))]>,
268 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
270 let IsVSXFMAAlt = 1 in
271 def XVMADDMSP : XX3Form<60, 73,
272 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
273 "xvmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
274 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
278 let BaseName = "XVMSUBADP" in {
279 let isCommutable = 1 in
280 def XVMSUBADP : XX3Form<60, 113,
281 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
282 "xvmsubadp $XT, $XA, $XB", IIC_VecFP,
283 [(set v2f64:$XT, (fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi)))]>,
284 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
286 let IsVSXFMAAlt = 1 in
287 def XVMSUBMDP : XX3Form<60, 121,
288 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
289 "xvmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
290 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
294 let BaseName = "XVMSUBASP" in {
295 let isCommutable = 1 in
296 def XVMSUBASP : XX3Form<60, 81,
297 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
298 "xvmsubasp $XT, $XA, $XB", IIC_VecFP,
299 [(set v4f32:$XT, (fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi)))]>,
300 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
302 let IsVSXFMAAlt = 1 in
303 def XVMSUBMSP : XX3Form<60, 89,
304 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
305 "xvmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
306 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
310 let BaseName = "XVNMADDADP" in {
311 let isCommutable = 1 in
312 def XVNMADDADP : XX3Form<60, 225,
313 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
314 "xvnmaddadp $XT, $XA, $XB", IIC_VecFP,
315 [(set v2f64:$XT, (fneg (fma v2f64:$XA, v2f64:$XB, v2f64:$XTi)))]>,
316 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
318 let IsVSXFMAAlt = 1 in
319 def XVNMADDMDP : XX3Form<60, 233,
320 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
321 "xvnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
322 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
326 let BaseName = "XVNMADDASP" in {
327 let isCommutable = 1 in
328 def XVNMADDASP : XX3Form<60, 193,
329 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
330 "xvnmaddasp $XT, $XA, $XB", IIC_VecFP,
331 [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi)))]>,
332 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
334 let IsVSXFMAAlt = 1 in
335 def XVNMADDMSP : XX3Form<60, 201,
336 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
337 "xvnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
338 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
342 let BaseName = "XVNMSUBADP" in {
343 let isCommutable = 1 in
344 def XVNMSUBADP : XX3Form<60, 241,
345 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
346 "xvnmsubadp $XT, $XA, $XB", IIC_VecFP,
347 [(set v2f64:$XT, (fneg (fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi))))]>,
348 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
350 let IsVSXFMAAlt = 1 in
351 def XVNMSUBMDP : XX3Form<60, 249,
352 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
353 "xvnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
354 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
358 let BaseName = "XVNMSUBASP" in {
359 let isCommutable = 1 in
360 def XVNMSUBASP : XX3Form<60, 209,
361 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
362 "xvnmsubasp $XT, $XA, $XB", IIC_VecFP,
363 [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi))))]>,
364 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
366 let IsVSXFMAAlt = 1 in
367 def XVNMSUBMSP : XX3Form<60, 217,
368 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
369 "xvnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
370 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
374 // Division Instructions
375 def XSDIVDP : XX3Form<60, 56,
376 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
377 "xsdivdp $XT, $XA, $XB", IIC_FPDivD,
378 [(set f64:$XT, (fdiv f64:$XA, f64:$XB))]>;
379 def XSSQRTDP : XX2Form<60, 75,
380 (outs vsfrc:$XT), (ins vsfrc:$XB),
381 "xssqrtdp $XT, $XB", IIC_FPSqrtD,
382 [(set f64:$XT, (fsqrt f64:$XB))]>;
384 def XSREDP : XX2Form<60, 90,
385 (outs vsfrc:$XT), (ins vsfrc:$XB),
386 "xsredp $XT, $XB", IIC_VecFP,
387 [(set f64:$XT, (PPCfre f64:$XB))]>;
388 def XSRSQRTEDP : XX2Form<60, 74,
389 (outs vsfrc:$XT), (ins vsfrc:$XB),
390 "xsrsqrtedp $XT, $XB", IIC_VecFP,
391 [(set f64:$XT, (PPCfrsqrte f64:$XB))]>;
393 def XSTDIVDP : XX3Form_1<60, 61,
394 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
395 "xstdivdp $crD, $XA, $XB", IIC_FPCompare, []>;
396 def XSTSQRTDP : XX2Form_1<60, 106,
397 (outs crrc:$crD), (ins vsfrc:$XB),
398 "xstsqrtdp $crD, $XB", IIC_FPCompare, []>;
400 def XVDIVDP : XX3Form<60, 120,
401 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
402 "xvdivdp $XT, $XA, $XB", IIC_FPDivD,
403 [(set v2f64:$XT, (fdiv v2f64:$XA, v2f64:$XB))]>;
404 def XVDIVSP : XX3Form<60, 88,
405 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
406 "xvdivsp $XT, $XA, $XB", IIC_FPDivS,
407 [(set v4f32:$XT, (fdiv v4f32:$XA, v4f32:$XB))]>;
409 def XVSQRTDP : XX2Form<60, 203,
410 (outs vsrc:$XT), (ins vsrc:$XB),
411 "xvsqrtdp $XT, $XB", IIC_FPSqrtD,
412 [(set v2f64:$XT, (fsqrt v2f64:$XB))]>;
413 def XVSQRTSP : XX2Form<60, 139,
414 (outs vsrc:$XT), (ins vsrc:$XB),
415 "xvsqrtsp $XT, $XB", IIC_FPSqrtS,
416 [(set v4f32:$XT, (fsqrt v4f32:$XB))]>;
418 def XVTDIVDP : XX3Form_1<60, 125,
419 (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
420 "xvtdivdp $crD, $XA, $XB", IIC_FPCompare, []>;
421 def XVTDIVSP : XX3Form_1<60, 93,
422 (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
423 "xvtdivsp $crD, $XA, $XB", IIC_FPCompare, []>;
425 def XVTSQRTDP : XX2Form_1<60, 234,
426 (outs crrc:$crD), (ins vsrc:$XB),
427 "xvtsqrtdp $crD, $XB", IIC_FPCompare, []>;
428 def XVTSQRTSP : XX2Form_1<60, 170,
429 (outs crrc:$crD), (ins vsrc:$XB),
430 "xvtsqrtsp $crD, $XB", IIC_FPCompare, []>;
432 def XVREDP : XX2Form<60, 218,
433 (outs vsrc:$XT), (ins vsrc:$XB),
434 "xvredp $XT, $XB", IIC_VecFP,
435 [(set v2f64:$XT, (PPCfre v2f64:$XB))]>;
436 def XVRESP : XX2Form<60, 154,
437 (outs vsrc:$XT), (ins vsrc:$XB),
438 "xvresp $XT, $XB", IIC_VecFP,
439 [(set v4f32:$XT, (PPCfre v4f32:$XB))]>;
441 def XVRSQRTEDP : XX2Form<60, 202,
442 (outs vsrc:$XT), (ins vsrc:$XB),
443 "xvrsqrtedp $XT, $XB", IIC_VecFP,
444 [(set v2f64:$XT, (PPCfrsqrte v2f64:$XB))]>;
445 def XVRSQRTESP : XX2Form<60, 138,
446 (outs vsrc:$XT), (ins vsrc:$XB),
447 "xvrsqrtesp $XT, $XB", IIC_VecFP,
448 [(set v4f32:$XT, (PPCfrsqrte v4f32:$XB))]>;
450 // Compare Instructions
451 def XSCMPODP : XX3Form_1<60, 43,
452 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
453 "xscmpodp $crD, $XA, $XB", IIC_FPCompare, []>;
454 def XSCMPUDP : XX3Form_1<60, 35,
455 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
456 "xscmpudp $crD, $XA, $XB", IIC_FPCompare, []>;
458 defm XVCMPEQDP : XX3Form_Rcr<60, 99,
459 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
460 "xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
461 defm XVCMPEQSP : XX3Form_Rcr<60, 67,
462 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
463 "xvcmpeqsp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
464 defm XVCMPGEDP : XX3Form_Rcr<60, 115,
465 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
466 "xvcmpgedp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
467 defm XVCMPGESP : XX3Form_Rcr<60, 83,
468 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
469 "xvcmpgesp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
470 defm XVCMPGTDP : XX3Form_Rcr<60, 107,
471 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
472 "xvcmpgtdp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
473 defm XVCMPGTSP : XX3Form_Rcr<60, 75,
474 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
475 "xvcmpgtsp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
478 def XSABSDP : XX2Form<60, 345,
479 (outs vsfrc:$XT), (ins vsfrc:$XB),
480 "xsabsdp $XT, $XB", IIC_VecFP,
481 [(set f64:$XT, (fabs f64:$XB))]>;
482 def XSNABSDP : XX2Form<60, 361,
483 (outs vsfrc:$XT), (ins vsfrc:$XB),
484 "xsnabsdp $XT, $XB", IIC_VecFP,
485 [(set f64:$XT, (fneg (fabs f64:$XB)))]>;
486 def XSNEGDP : XX2Form<60, 377,
487 (outs vsfrc:$XT), (ins vsfrc:$XB),
488 "xsnegdp $XT, $XB", IIC_VecFP,
489 [(set f64:$XT, (fneg f64:$XB))]>;
490 def XSCPSGNDP : XX3Form<60, 176,
491 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
492 "xscpsgndp $XT, $XA, $XB", IIC_VecFP,
493 [(set f64:$XT, (fcopysign f64:$XB, f64:$XA))]>;
495 def XVABSDP : XX2Form<60, 473,
496 (outs vsrc:$XT), (ins vsrc:$XB),
497 "xvabsdp $XT, $XB", IIC_VecFP,
498 [(set v2f64:$XT, (fabs v2f64:$XB))]>;
500 def XVABSSP : XX2Form<60, 409,
501 (outs vsrc:$XT), (ins vsrc:$XB),
502 "xvabssp $XT, $XB", IIC_VecFP,
503 [(set v4f32:$XT, (fabs v4f32:$XB))]>;
505 def XVCPSGNDP : XX3Form<60, 240,
506 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
507 "xvcpsgndp $XT, $XA, $XB", IIC_VecFP,
508 [(set v2f64:$XT, (fcopysign v2f64:$XB, v2f64:$XA))]>;
509 def XVCPSGNSP : XX3Form<60, 208,
510 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
511 "xvcpsgnsp $XT, $XA, $XB", IIC_VecFP,
512 [(set v4f32:$XT, (fcopysign v4f32:$XB, v4f32:$XA))]>;
514 def XVNABSDP : XX2Form<60, 489,
515 (outs vsrc:$XT), (ins vsrc:$XB),
516 "xvnabsdp $XT, $XB", IIC_VecFP,
517 [(set v2f64:$XT, (fneg (fabs v2f64:$XB)))]>;
518 def XVNABSSP : XX2Form<60, 425,
519 (outs vsrc:$XT), (ins vsrc:$XB),
520 "xvnabssp $XT, $XB", IIC_VecFP,
521 [(set v4f32:$XT, (fneg (fabs v4f32:$XB)))]>;
523 def XVNEGDP : XX2Form<60, 505,
524 (outs vsrc:$XT), (ins vsrc:$XB),
525 "xvnegdp $XT, $XB", IIC_VecFP,
526 [(set v2f64:$XT, (fneg v2f64:$XB))]>;
527 def XVNEGSP : XX2Form<60, 441,
528 (outs vsrc:$XT), (ins vsrc:$XB),
529 "xvnegsp $XT, $XB", IIC_VecFP,
530 [(set v4f32:$XT, (fneg v4f32:$XB))]>;
532 // Conversion Instructions
533 def XSCVDPSP : XX2Form<60, 265,
534 (outs vsfrc:$XT), (ins vsfrc:$XB),
535 "xscvdpsp $XT, $XB", IIC_VecFP, []>;
536 def XSCVDPSXDS : XX2Form<60, 344,
537 (outs vsfrc:$XT), (ins vsfrc:$XB),
538 "xscvdpsxds $XT, $XB", IIC_VecFP,
539 [(set f64:$XT, (PPCfctidz f64:$XB))]>;
540 def XSCVDPSXWS : XX2Form<60, 88,
541 (outs vsfrc:$XT), (ins vsfrc:$XB),
542 "xscvdpsxws $XT, $XB", IIC_VecFP,
543 [(set f64:$XT, (PPCfctiwz f64:$XB))]>;
544 def XSCVDPUXDS : XX2Form<60, 328,
545 (outs vsfrc:$XT), (ins vsfrc:$XB),
546 "xscvdpuxds $XT, $XB", IIC_VecFP,
547 [(set f64:$XT, (PPCfctiduz f64:$XB))]>;
548 def XSCVDPUXWS : XX2Form<60, 72,
549 (outs vsfrc:$XT), (ins vsfrc:$XB),
550 "xscvdpuxws $XT, $XB", IIC_VecFP,
551 [(set f64:$XT, (PPCfctiwuz f64:$XB))]>;
552 def XSCVSPDP : XX2Form<60, 329,
553 (outs vsfrc:$XT), (ins vsfrc:$XB),
554 "xscvspdp $XT, $XB", IIC_VecFP, []>;
555 def XSCVSXDDP : XX2Form<60, 376,
556 (outs vsfrc:$XT), (ins vsfrc:$XB),
557 "xscvsxddp $XT, $XB", IIC_VecFP,
558 [(set f64:$XT, (PPCfcfid f64:$XB))]>;
559 def XSCVUXDDP : XX2Form<60, 360,
560 (outs vsfrc:$XT), (ins vsfrc:$XB),
561 "xscvuxddp $XT, $XB", IIC_VecFP,
562 [(set f64:$XT, (PPCfcfidu f64:$XB))]>;
564 def XVCVDPSP : XX2Form<60, 393,
565 (outs vsrc:$XT), (ins vsrc:$XB),
566 "xvcvdpsp $XT, $XB", IIC_VecFP, []>;
567 def XVCVDPSXDS : XX2Form<60, 472,
568 (outs vsrc:$XT), (ins vsrc:$XB),
569 "xvcvdpsxds $XT, $XB", IIC_VecFP,
570 [(set v2i64:$XT, (fp_to_sint v2f64:$XB))]>;
571 def XVCVDPSXWS : XX2Form<60, 216,
572 (outs vsrc:$XT), (ins vsrc:$XB),
573 "xvcvdpsxws $XT, $XB", IIC_VecFP, []>;
574 def XVCVDPUXDS : XX2Form<60, 456,
575 (outs vsrc:$XT), (ins vsrc:$XB),
576 "xvcvdpuxds $XT, $XB", IIC_VecFP,
577 [(set v2i64:$XT, (fp_to_uint v2f64:$XB))]>;
578 def XVCVDPUXWS : XX2Form<60, 200,
579 (outs vsrc:$XT), (ins vsrc:$XB),
580 "xvcvdpuxws $XT, $XB", IIC_VecFP, []>;
582 def XVCVSPDP : XX2Form<60, 457,
583 (outs vsrc:$XT), (ins vsrc:$XB),
584 "xvcvspdp $XT, $XB", IIC_VecFP, []>;
585 def XVCVSPSXDS : XX2Form<60, 408,
586 (outs vsrc:$XT), (ins vsrc:$XB),
587 "xvcvspsxds $XT, $XB", IIC_VecFP, []>;
588 def XVCVSPSXWS : XX2Form<60, 152,
589 (outs vsrc:$XT), (ins vsrc:$XB),
590 "xvcvspsxws $XT, $XB", IIC_VecFP, []>;
591 def XVCVSPUXDS : XX2Form<60, 392,
592 (outs vsrc:$XT), (ins vsrc:$XB),
593 "xvcvspuxds $XT, $XB", IIC_VecFP, []>;
594 def XVCVSPUXWS : XX2Form<60, 136,
595 (outs vsrc:$XT), (ins vsrc:$XB),
596 "xvcvspuxws $XT, $XB", IIC_VecFP, []>;
597 def XVCVSXDDP : XX2Form<60, 504,
598 (outs vsrc:$XT), (ins vsrc:$XB),
599 "xvcvsxddp $XT, $XB", IIC_VecFP,
600 [(set v2f64:$XT, (sint_to_fp v2i64:$XB))]>;
601 def XVCVSXDSP : XX2Form<60, 440,
602 (outs vsrc:$XT), (ins vsrc:$XB),
603 "xvcvsxdsp $XT, $XB", IIC_VecFP, []>;
604 def XVCVSXWDP : XX2Form<60, 248,
605 (outs vsrc:$XT), (ins vsrc:$XB),
606 "xvcvsxwdp $XT, $XB", IIC_VecFP, []>;
607 def XVCVSXWSP : XX2Form<60, 184,
608 (outs vsrc:$XT), (ins vsrc:$XB),
609 "xvcvsxwsp $XT, $XB", IIC_VecFP, []>;
610 def XVCVUXDDP : XX2Form<60, 488,
611 (outs vsrc:$XT), (ins vsrc:$XB),
612 "xvcvuxddp $XT, $XB", IIC_VecFP,
613 [(set v2f64:$XT, (uint_to_fp v2i64:$XB))]>;
614 def XVCVUXDSP : XX2Form<60, 424,
615 (outs vsrc:$XT), (ins vsrc:$XB),
616 "xvcvuxdsp $XT, $XB", IIC_VecFP, []>;
617 def XVCVUXWDP : XX2Form<60, 232,
618 (outs vsrc:$XT), (ins vsrc:$XB),
619 "xvcvuxwdp $XT, $XB", IIC_VecFP, []>;
620 def XVCVUXWSP : XX2Form<60, 168,
621 (outs vsrc:$XT), (ins vsrc:$XB),
622 "xvcvuxwsp $XT, $XB", IIC_VecFP, []>;
624 // Rounding Instructions
625 def XSRDPI : XX2Form<60, 73,
626 (outs vsfrc:$XT), (ins vsfrc:$XB),
627 "xsrdpi $XT, $XB", IIC_VecFP,
628 [(set f64:$XT, (frnd f64:$XB))]>;
629 def XSRDPIC : XX2Form<60, 107,
630 (outs vsfrc:$XT), (ins vsfrc:$XB),
631 "xsrdpic $XT, $XB", IIC_VecFP,
632 [(set f64:$XT, (fnearbyint f64:$XB))]>;
633 def XSRDPIM : XX2Form<60, 121,
634 (outs vsfrc:$XT), (ins vsfrc:$XB),
635 "xsrdpim $XT, $XB", IIC_VecFP,
636 [(set f64:$XT, (ffloor f64:$XB))]>;
637 def XSRDPIP : XX2Form<60, 105,
638 (outs vsfrc:$XT), (ins vsfrc:$XB),
639 "xsrdpip $XT, $XB", IIC_VecFP,
640 [(set f64:$XT, (fceil f64:$XB))]>;
641 def XSRDPIZ : XX2Form<60, 89,
642 (outs vsfrc:$XT), (ins vsfrc:$XB),
643 "xsrdpiz $XT, $XB", IIC_VecFP,
644 [(set f64:$XT, (ftrunc f64:$XB))]>;
646 def XVRDPI : XX2Form<60, 201,
647 (outs vsrc:$XT), (ins vsrc:$XB),
648 "xvrdpi $XT, $XB", IIC_VecFP,
649 [(set v2f64:$XT, (frnd v2f64:$XB))]>;
650 def XVRDPIC : XX2Form<60, 235,
651 (outs vsrc:$XT), (ins vsrc:$XB),
652 "xvrdpic $XT, $XB", IIC_VecFP,
653 [(set v2f64:$XT, (fnearbyint v2f64:$XB))]>;
654 def XVRDPIM : XX2Form<60, 249,
655 (outs vsrc:$XT), (ins vsrc:$XB),
656 "xvrdpim $XT, $XB", IIC_VecFP,
657 [(set v2f64:$XT, (ffloor v2f64:$XB))]>;
658 def XVRDPIP : XX2Form<60, 233,
659 (outs vsrc:$XT), (ins vsrc:$XB),
660 "xvrdpip $XT, $XB", IIC_VecFP,
661 [(set v2f64:$XT, (fceil v2f64:$XB))]>;
662 def XVRDPIZ : XX2Form<60, 217,
663 (outs vsrc:$XT), (ins vsrc:$XB),
664 "xvrdpiz $XT, $XB", IIC_VecFP,
665 [(set v2f64:$XT, (ftrunc v2f64:$XB))]>;
667 def XVRSPI : XX2Form<60, 137,
668 (outs vsrc:$XT), (ins vsrc:$XB),
669 "xvrspi $XT, $XB", IIC_VecFP,
670 [(set v4f32:$XT, (frnd v4f32:$XB))]>;
671 def XVRSPIC : XX2Form<60, 171,
672 (outs vsrc:$XT), (ins vsrc:$XB),
673 "xvrspic $XT, $XB", IIC_VecFP,
674 [(set v4f32:$XT, (fnearbyint v4f32:$XB))]>;
675 def XVRSPIM : XX2Form<60, 185,
676 (outs vsrc:$XT), (ins vsrc:$XB),
677 "xvrspim $XT, $XB", IIC_VecFP,
678 [(set v4f32:$XT, (ffloor v4f32:$XB))]>;
679 def XVRSPIP : XX2Form<60, 169,
680 (outs vsrc:$XT), (ins vsrc:$XB),
681 "xvrspip $XT, $XB", IIC_VecFP,
682 [(set v4f32:$XT, (fceil v4f32:$XB))]>;
683 def XVRSPIZ : XX2Form<60, 153,
684 (outs vsrc:$XT), (ins vsrc:$XB),
685 "xvrspiz $XT, $XB", IIC_VecFP,
686 [(set v4f32:$XT, (ftrunc v4f32:$XB))]>;
688 // Max/Min Instructions
689 let isCommutable = 1 in {
690 def XSMAXDP : XX3Form<60, 160,
691 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
692 "xsmaxdp $XT, $XA, $XB", IIC_VecFP,
694 (int_ppc_vsx_xsmaxdp vsfrc:$XA, vsfrc:$XB))]>;
695 def XSMINDP : XX3Form<60, 168,
696 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
697 "xsmindp $XT, $XA, $XB", IIC_VecFP,
699 (int_ppc_vsx_xsmindp vsfrc:$XA, vsfrc:$XB))]>;
701 def XVMAXDP : XX3Form<60, 224,
702 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
703 "xvmaxdp $XT, $XA, $XB", IIC_VecFP,
705 (int_ppc_vsx_xvmaxdp vsrc:$XA, vsrc:$XB))]>;
706 def XVMINDP : XX3Form<60, 232,
707 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
708 "xvmindp $XT, $XA, $XB", IIC_VecFP,
710 (int_ppc_vsx_xvmindp vsrc:$XA, vsrc:$XB))]>;
712 def XVMAXSP : XX3Form<60, 192,
713 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
714 "xvmaxsp $XT, $XA, $XB", IIC_VecFP,
716 (int_ppc_vsx_xvmaxsp vsrc:$XA, vsrc:$XB))]>;
717 def XVMINSP : XX3Form<60, 200,
718 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
719 "xvminsp $XT, $XA, $XB", IIC_VecFP,
721 (int_ppc_vsx_xvminsp vsrc:$XA, vsrc:$XB))]>;
725 // Logical Instructions
726 let isCommutable = 1 in
727 def XXLAND : XX3Form<60, 130,
728 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
729 "xxland $XT, $XA, $XB", IIC_VecGeneral,
730 [(set v4i32:$XT, (and v4i32:$XA, v4i32:$XB))]>;
731 def XXLANDC : XX3Form<60, 138,
732 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
733 "xxlandc $XT, $XA, $XB", IIC_VecGeneral,
734 [(set v4i32:$XT, (and v4i32:$XA,
735 (vnot_ppc v4i32:$XB)))]>;
736 let isCommutable = 1 in {
737 def XXLNOR : XX3Form<60, 162,
738 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
739 "xxlnor $XT, $XA, $XB", IIC_VecGeneral,
740 [(set v4i32:$XT, (vnot_ppc (or v4i32:$XA,
742 def XXLOR : XX3Form<60, 146,
743 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
744 "xxlor $XT, $XA, $XB", IIC_VecGeneral,
745 [(set v4i32:$XT, (or v4i32:$XA, v4i32:$XB))]>;
746 let isCodeGenOnly = 1 in
747 def XXLORf: XX3Form<60, 146,
748 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
749 "xxlor $XT, $XA, $XB", IIC_VecGeneral, []>;
750 def XXLXOR : XX3Form<60, 154,
751 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
752 "xxlxor $XT, $XA, $XB", IIC_VecGeneral,
753 [(set v4i32:$XT, (xor v4i32:$XA, v4i32:$XB))]>;
756 // Permutation Instructions
757 def XXMRGHW : XX3Form<60, 18,
758 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
759 "xxmrghw $XT, $XA, $XB", IIC_VecPerm, []>;
760 def XXMRGLW : XX3Form<60, 50,
761 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
762 "xxmrglw $XT, $XA, $XB", IIC_VecPerm, []>;
764 def XXPERMDI : XX3Form_2<60, 10,
765 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$DM),
766 "xxpermdi $XT, $XA, $XB, $DM", IIC_VecPerm, []>;
767 def XXSEL : XX4Form<60, 3,
768 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC),
769 "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>;
771 def XXSLDWI : XX3Form_2<60, 2,
772 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$SHW),
773 "xxsldwi $XT, $XA, $XB, $SHW", IIC_VecPerm, []>;
774 def XXSPLTW : XX2Form_2<60, 164,
775 (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM),
776 "xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>;
779 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
780 // instruction selection into a branch sequence.
781 let usesCustomInserter = 1, // Expanded after instruction selection.
782 PPC970_Single = 1 in {
784 def SELECT_CC_VSRC: Pseudo<(outs vsrc:$dst),
785 (ins crrc:$cond, vsrc:$T, vsrc:$F, i32imm:$BROPC),
788 def SELECT_VSRC: Pseudo<(outs vsrc:$dst),
789 (ins crbitrc:$cond, vsrc:$T, vsrc:$F),
792 (select i1:$cond, v2f64:$T, v2f64:$F))]>;
793 def SELECT_CC_VSFRC: Pseudo<(outs f8rc:$dst),
794 (ins crrc:$cond, f8rc:$T, f8rc:$F,
795 i32imm:$BROPC), "#SELECT_CC_VSFRC",
797 def SELECT_VSFRC: Pseudo<(outs f8rc:$dst),
798 (ins crbitrc:$cond, f8rc:$T, f8rc:$F),
801 (select i1:$cond, f64:$T, f64:$F))]>;
802 def SELECT_CC_VSSRC: Pseudo<(outs f4rc:$dst),
803 (ins crrc:$cond, f4rc:$T, f4rc:$F,
804 i32imm:$BROPC), "#SELECT_CC_VSSRC",
806 def SELECT_VSSRC: Pseudo<(outs f4rc:$dst),
807 (ins crbitrc:$cond, f4rc:$T, f4rc:$F),
810 (select i1:$cond, f32:$T, f32:$F))]>;
811 } // usesCustomInserter
814 def : InstAlias<"xvmovdp $XT, $XB",
815 (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
816 def : InstAlias<"xvmovsp $XT, $XB",
817 (XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
819 def : InstAlias<"xxspltd $XT, $XB, 0",
820 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0)>;
821 def : InstAlias<"xxspltd $XT, $XB, 1",
822 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3)>;
823 def : InstAlias<"xxmrghd $XT, $XA, $XB",
824 (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 0)>;
825 def : InstAlias<"xxmrgld $XT, $XA, $XB",
826 (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3)>;
827 def : InstAlias<"xxswapd $XT, $XB",
828 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>;
830 let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
832 let Predicates = [IsBigEndian] in {
833 def : Pat<(v2f64 (scalar_to_vector f64:$A)),
834 (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;
836 def : Pat<(f64 (vector_extract v2f64:$S, 0)),
837 (f64 (EXTRACT_SUBREG $S, sub_64))>;
838 def : Pat<(f64 (vector_extract v2f64:$S, 1)),
839 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
842 let Predicates = [IsLittleEndian] in {
843 def : Pat<(v2f64 (scalar_to_vector f64:$A)),
844 (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64),
845 (SUBREG_TO_REG (i64 1), $A, sub_64), 0))>;
847 def : Pat<(f64 (vector_extract v2f64:$S, 0)),
848 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
849 def : Pat<(f64 (vector_extract v2f64:$S, 1)),
850 (f64 (EXTRACT_SUBREG $S, sub_64))>;
853 // Additional fnmsub patterns: -a*c + b == -(a*c - b)
854 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
855 (XSNMSUBADP $B, $C, $A)>;
856 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
857 (XSNMSUBADP $B, $C, $A)>;
859 def : Pat<(fma (fneg v2f64:$A), v2f64:$C, v2f64:$B),
860 (XVNMSUBADP $B, $C, $A)>;
861 def : Pat<(fma v2f64:$A, (fneg v2f64:$C), v2f64:$B),
862 (XVNMSUBADP $B, $C, $A)>;
864 def : Pat<(fma (fneg v4f32:$A), v4f32:$C, v4f32:$B),
865 (XVNMSUBASP $B, $C, $A)>;
866 def : Pat<(fma v4f32:$A, (fneg v4f32:$C), v4f32:$B),
867 (XVNMSUBASP $B, $C, $A)>;
869 def : Pat<(v2f64 (bitconvert v4f32:$A)),
870 (COPY_TO_REGCLASS $A, VSRC)>;
871 def : Pat<(v2f64 (bitconvert v4i32:$A)),
872 (COPY_TO_REGCLASS $A, VSRC)>;
873 def : Pat<(v2f64 (bitconvert v8i16:$A)),
874 (COPY_TO_REGCLASS $A, VSRC)>;
875 def : Pat<(v2f64 (bitconvert v16i8:$A)),
876 (COPY_TO_REGCLASS $A, VSRC)>;
878 def : Pat<(v4f32 (bitconvert v2f64:$A)),
879 (COPY_TO_REGCLASS $A, VRRC)>;
880 def : Pat<(v4i32 (bitconvert v2f64:$A)),
881 (COPY_TO_REGCLASS $A, VRRC)>;
882 def : Pat<(v8i16 (bitconvert v2f64:$A)),
883 (COPY_TO_REGCLASS $A, VRRC)>;
884 def : Pat<(v16i8 (bitconvert v2f64:$A)),
885 (COPY_TO_REGCLASS $A, VRRC)>;
887 def : Pat<(v2i64 (bitconvert v4f32:$A)),
888 (COPY_TO_REGCLASS $A, VSRC)>;
889 def : Pat<(v2i64 (bitconvert v4i32:$A)),
890 (COPY_TO_REGCLASS $A, VSRC)>;
891 def : Pat<(v2i64 (bitconvert v8i16:$A)),
892 (COPY_TO_REGCLASS $A, VSRC)>;
893 def : Pat<(v2i64 (bitconvert v16i8:$A)),
894 (COPY_TO_REGCLASS $A, VSRC)>;
896 def : Pat<(v4f32 (bitconvert v2i64:$A)),
897 (COPY_TO_REGCLASS $A, VRRC)>;
898 def : Pat<(v4i32 (bitconvert v2i64:$A)),
899 (COPY_TO_REGCLASS $A, VRRC)>;
900 def : Pat<(v8i16 (bitconvert v2i64:$A)),
901 (COPY_TO_REGCLASS $A, VRRC)>;
902 def : Pat<(v16i8 (bitconvert v2i64:$A)),
903 (COPY_TO_REGCLASS $A, VRRC)>;
905 def : Pat<(v2f64 (bitconvert v2i64:$A)),
906 (COPY_TO_REGCLASS $A, VRRC)>;
907 def : Pat<(v2i64 (bitconvert v2f64:$A)),
908 (COPY_TO_REGCLASS $A, VRRC)>;
910 def : Pat<(v2f64 (bitconvert v1i128:$A)),
911 (COPY_TO_REGCLASS $A, VRRC)>;
912 def : Pat<(v1i128 (bitconvert v2f64:$A)),
913 (COPY_TO_REGCLASS $A, VRRC)>;
915 // sign extension patterns
916 // To extend "in place" from v2i32 to v2i64, we have input data like:
917 // | undef | i32 | undef | i32 |
918 // but xvcvsxwdp expects the input in big-Endian format:
919 // | i32 | undef | i32 | undef |
920 // so we need to shift everything to the left by one i32 (word) before
922 def : Pat<(sext_inreg v2i64:$C, v2i32),
923 (XVCVDPSXDS (XVCVSXWDP (XXSLDWI $C, $C, 1)))>;
924 def : Pat<(v2f64 (sint_to_fp (sext_inreg v2i64:$C, v2i32))),
925 (XVCVSXWDP (XXSLDWI $C, $C, 1))>;
928 def : Pat<(v2f64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>;
929 def : Pat<(v2i64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>;
930 def : Pat<(v4i32 (load xoaddr:$src)), (LXVW4X xoaddr:$src)>;
931 def : Pat<(v2f64 (PPClxvd2x xoaddr:$src)), (LXVD2X xoaddr:$src)>;
934 def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, xoaddr:$dst),
935 (STXVD2X $rS, xoaddr:$dst)>;
936 def : Pat<(store v2i64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
937 def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, xoaddr:$dst),
938 (STXVW4X $rS, xoaddr:$dst)>;
939 def : Pat<(PPCstxvd2x v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
942 def : Pat<(v2f64 (PPCxxswapd v2f64:$src)), (XXPERMDI $src, $src, 2)>;
943 def : Pat<(v2i64 (PPCxxswapd v2i64:$src)), (XXPERMDI $src, $src, 2)>;
944 def : Pat<(v4f32 (PPCxxswapd v4f32:$src)), (XXPERMDI $src, $src, 2)>;
945 def : Pat<(v4i32 (PPCxxswapd v4i32:$src)), (XXPERMDI $src, $src, 2)>;
948 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLT)),
949 (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
950 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLE)),
951 (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>;
952 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETEQ)),
953 (SELECT_VSRC (CREQV $lhs, $rhs), $tval, $fval)>;
954 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGE)),
955 (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>;
956 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGT)),
957 (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
958 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETNE)),
959 (SELECT_VSRC (CRXOR $lhs, $rhs), $tval, $fval)>;
961 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
962 (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>;
963 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
964 (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>;
965 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
966 (SELECT_VSFRC (CREQV $lhs, $rhs), $tval, $fval)>;
967 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
968 (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>;
969 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
970 (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>;
971 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
972 (SELECT_VSFRC (CRXOR $lhs, $rhs), $tval, $fval)>;
975 def : Pat<(int_ppc_vsx_xvdivsp v4f32:$A, v4f32:$B),
977 def : Pat<(int_ppc_vsx_xvdivdp v2f64:$A, v2f64:$B),
983 // The following VSX instructions were introduced in Power ISA 2.07
984 /* FIXME: if the operands are v2i64, these patterns will not match.
985 we should define new patterns or otherwise match the same patterns
986 when the elements are larger than i32.
988 def HasP8Vector : Predicate<"PPCSubTarget->hasP8Vector()">;
989 def HasDirectMove : Predicate<"PPCSubTarget->hasDirectMove()">;
990 let Predicates = [HasP8Vector] in {
991 let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
992 let isCommutable = 1 in {
993 def XXLEQV : XX3Form<60, 186,
994 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
995 "xxleqv $XT, $XA, $XB", IIC_VecGeneral,
996 [(set v4i32:$XT, (vnot_ppc (xor v4i32:$XA, v4i32:$XB)))]>;
997 def XXLNAND : XX3Form<60, 178,
998 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
999 "xxlnand $XT, $XA, $XB", IIC_VecGeneral,
1000 [(set v4i32:$XT, (vnot_ppc (and v4i32:$XA,
1004 def XXLORC : XX3Form<60, 170,
1005 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1006 "xxlorc $XT, $XA, $XB", IIC_VecGeneral,
1007 [(set v4i32:$XT, (or v4i32:$XA, (vnot_ppc v4i32:$XB)))]>;
1009 // VSX scalar loads introduced in ISA 2.07
1010 let mayLoad = 1 in {
1011 def LXSSPX : XX1Form<31, 524, (outs vssrc:$XT), (ins memrr:$src),
1012 "lxsspx $XT, $src", IIC_LdStLFD,
1013 [(set f32:$XT, (load xoaddr:$src))]>;
1014 def LXSIWAX : XX1Form<31, 76, (outs vsfrc:$XT), (ins memrr:$src),
1015 "lxsiwax $XT, $src", IIC_LdStLFD,
1016 [(set f64:$XT, (PPClfiwax xoaddr:$src))]>;
1017 def LXSIWZX : XX1Form<31, 12, (outs vsfrc:$XT), (ins memrr:$src),
1018 "lxsiwzx $XT, $src", IIC_LdStLFD,
1019 [(set f64:$XT, (PPClfiwzx xoaddr:$src))]>;
1022 // VSX scalar stores introduced in ISA 2.07
1023 let mayStore = 1 in {
1024 def STXSSPX : XX1Form<31, 652, (outs), (ins vssrc:$XT, memrr:$dst),
1025 "stxsspx $XT, $dst", IIC_LdStSTFD,
1026 [(store f32:$XT, xoaddr:$dst)]>;
1027 def STXSIWX : XX1Form<31, 140, (outs), (ins vsfrc:$XT, memrr:$dst),
1028 "stxsiwx $XT, $dst", IIC_LdStSTFD,
1029 [(PPCstfiwx f64:$XT, xoaddr:$dst)]>;
1032 def : Pat<(f64 (extloadf32 xoaddr:$src)),
1033 (COPY_TO_REGCLASS (LXSSPX xoaddr:$src), VSFRC)>;
1034 def : Pat<(f64 (fextend f32:$src)),
1035 (COPY_TO_REGCLASS $src, VSFRC)>;
1036 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
1037 (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
1038 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
1039 (SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>;
1040 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
1041 (SELECT_VSSRC (CREQV $lhs, $rhs), $tval, $fval)>;
1042 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
1043 (SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>;
1044 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
1045 (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
1046 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
1047 (SELECT_VSSRC (CRXOR $lhs, $rhs), $tval, $fval)>;
1049 // VSX Elementary Scalar FP arithmetic (SP)
1050 let isCommutable = 1 in {
1051 def XSADDSP : XX3Form<60, 0,
1052 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),
1053 "xsaddsp $XT, $XA, $XB", IIC_VecFP,
1054 [(set f32:$XT, (fadd f32:$XA, f32:$XB))]>;
1055 def XSMULSP : XX3Form<60, 16,
1056 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),
1057 "xsmulsp $XT, $XA, $XB", IIC_VecFP,
1058 [(set f32:$XT, (fmul f32:$XA, f32:$XB))]>;
1061 def XSDIVSP : XX3Form<60, 24,
1062 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),
1063 "xsdivsp $XT, $XA, $XB", IIC_FPDivS,
1064 [(set f32:$XT, (fdiv f32:$XA, f32:$XB))]>;
1065 def XSRESP : XX2Form<60, 26,
1066 (outs vssrc:$XT), (ins vssrc:$XB),
1067 "xsresp $XT, $XB", IIC_VecFP,
1068 [(set f32:$XT, (PPCfre f32:$XB))]>;
1069 def XSSQRTSP : XX2Form<60, 11,
1070 (outs vssrc:$XT), (ins vssrc:$XB),
1071 "xssqrtsp $XT, $XB", IIC_FPSqrtS,
1072 [(set f32:$XT, (fsqrt f32:$XB))]>;
1073 def XSRSQRTESP : XX2Form<60, 10,
1074 (outs vssrc:$XT), (ins vssrc:$XB),
1075 "xsrsqrtesp $XT, $XB", IIC_VecFP,
1076 [(set f32:$XT, (PPCfrsqrte f32:$XB))]>;
1077 def XSSUBSP : XX3Form<60, 8,
1078 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),
1079 "xssubsp $XT, $XA, $XB", IIC_VecFP,
1080 [(set f32:$XT, (fsub f32:$XA, f32:$XB))]>;
1083 let BaseName = "XSMADDASP" in {
1084 let isCommutable = 1 in
1085 def XSMADDASP : XX3Form<60, 1,
1087 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1088 "xsmaddasp $XT, $XA, $XB", IIC_VecFP,
1089 [(set f32:$XT, (fma f32:$XA, f32:$XB, f32:$XTi))]>,
1090 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1092 let IsVSXFMAAlt = 1 in
1093 def XSMADDMSP : XX3Form<60, 9,
1095 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1096 "xsmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
1097 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1101 let BaseName = "XSMSUBASP" in {
1102 let isCommutable = 1 in
1103 def XSMSUBASP : XX3Form<60, 17,
1105 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1106 "xsmsubasp $XT, $XA, $XB", IIC_VecFP,
1107 [(set f32:$XT, (fma f32:$XA, f32:$XB,
1108 (fneg f32:$XTi)))]>,
1109 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1111 let IsVSXFMAAlt = 1 in
1112 def XSMSUBMSP : XX3Form<60, 25,
1114 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1115 "xsmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
1116 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1120 let BaseName = "XSNMADDASP" in {
1121 let isCommutable = 1 in
1122 def XSNMADDASP : XX3Form<60, 129,
1124 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1125 "xsnmaddasp $XT, $XA, $XB", IIC_VecFP,
1126 [(set f32:$XT, (fneg (fma f32:$XA, f32:$XB,
1128 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1130 let IsVSXFMAAlt = 1 in
1131 def XSNMADDMSP : XX3Form<60, 137,
1133 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1134 "xsnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
1135 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1139 let BaseName = "XSNMSUBASP" in {
1140 let isCommutable = 1 in
1141 def XSNMSUBASP : XX3Form<60, 145,
1143 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1144 "xsnmsubasp $XT, $XA, $XB", IIC_VecFP,
1145 [(set f32:$XT, (fneg (fma f32:$XA, f32:$XB,
1146 (fneg f32:$XTi))))]>,
1147 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1149 let IsVSXFMAAlt = 1 in
1150 def XSNMSUBMSP : XX3Form<60, 153,
1152 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1153 "xsnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
1154 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1157 } // AddedComplexity = 400
1160 let Predicates = [HasDirectMove, HasVSX] in {
1161 // VSX direct move instructions
1162 def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT),
1163 "mfvsrd $rA, $XT", IIC_VecGeneral,
1164 [(set i64:$rA, (PPCmfvsr f64:$XT))]>,
1165 Requires<[In64BitMode]>;
1166 def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
1167 "mfvsrwz $rA, $XT", IIC_VecGeneral,
1168 [(set i32:$rA, (PPCmfvsr f64:$XT))]>;
1169 def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA),
1170 "mtvsrd $XT, $rA", IIC_VecGeneral,
1171 [(set f64:$XT, (PPCmtvsra i64:$rA))]>,
1172 Requires<[In64BitMode]>;
1173 def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$rA),
1174 "mtvsrwa $XT, $rA", IIC_VecGeneral,
1175 [(set f64:$XT, (PPCmtvsra i32:$rA))]>;
1176 def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$rA),
1177 "mtvsrwz $XT, $rA", IIC_VecGeneral,
1178 [(set f64:$XT, (PPCmtvsrz i32:$rA))]>;
1179 } // HasDirectMove, HasVSX