2 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
4 // The LLVM Compiler Infrastructure
6 // This file was developed by the LLVM research group and is distributed under
7 // the University of Illinois Open Source License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the subset of the 32-bit PowerPC instruction set, as used
12 // by the PowerPC instruction selector.
14 //===----------------------------------------------------------------------===//
16 include "PowerPCInstrFormats.td"
18 class isPPC64 { bit PPC64 = 1; }
19 class isVMX { bit VMX = 1; }
21 list<Register> Defs = [CR0];
25 let isTerminator = 1 in {
27 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">;
28 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">;
31 def u5imm : Operand<i8> {
32 let PrintMethod = "printU5ImmOperand";
34 def u6imm : Operand<i8> {
35 let PrintMethod = "printU6ImmOperand";
37 def s16imm : Operand<i16> {
38 let PrintMethod = "printS16ImmOperand";
40 def u16imm : Operand<i16> {
41 let PrintMethod = "printU16ImmOperand";
43 def target : Operand<i32> {
44 let PrintMethod = "printBranchOperand";
46 def piclabel: Operand<i32> {
47 let PrintMethod = "printPICLabel";
49 def symbolHi: Operand<i32> {
50 let PrintMethod = "printSymbolHi";
52 def symbolLo: Operand<i32> {
53 let PrintMethod = "printSymbolLo";
55 def crbit: Operand<i8> {
56 let PrintMethod = "printcrbit";
59 // Pseudo-instructions:
60 def PHI : Pseudo<(ops), "; PHI">;
62 def ADJCALLSTACKDOWN : Pseudo<(ops), "; ADJCALLSTACKDOWN">;
63 def ADJCALLSTACKUP : Pseudo<(ops), "; ADJCALLSTACKUP">;
65 def IMPLICIT_DEF : Pseudo<(ops), "; IMPLICIT_DEF">;
68 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
70 let isBranch = 1, isTerminator = 1 in {
71 def COND_BRANCH : Pseudo<(ops), "; COND_BRANCH">;
72 def B : IForm<18, 0, 0, (ops target:$func), "b $func">;
73 //def BA : IForm<18, 1, 0, (ops target:$func), "ba $func">;
74 def BL : IForm<18, 0, 1, (ops target:$func), "bl $func">;
75 //def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func">;
77 // FIXME: 4*CR# needs to be added to the BI field!
78 // This will only work for CR0 as it stands now
79 def BLT : BForm_ext<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
81 def BLE : BForm_ext<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
83 def BEQ : BForm_ext<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
85 def BGE : BForm_ext<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
87 def BGT : BForm_ext<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
89 def BNE : BForm_ext<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
94 // All calls clobber the non-callee saved registers...
95 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
96 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
98 CR0,CR1,CR5,CR6,CR7] in {
99 // Convenient aliases for call instructions
100 def CALLpcrel : IForm<18, 0, 1, (ops target:$func), "bl $func">;
101 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1, (ops), "bctrl">;
104 // D-Form instructions. Most instructions that perform an operation on a
105 // register and an immediate are of this type.
108 def LBZ : DForm_1<34, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
109 "lbz $rD, $disp($rA)">;
110 def LHA : DForm_1<42, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
111 "lha $rD, $disp($rA)">;
112 def LHZ : DForm_1<40, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
113 "lhz $rD, $disp($rA)">;
114 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
115 "lmw $rD, $disp($rA)">;
116 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
117 "lwz $rD, $disp($rA)">;
118 def LWZU : DForm_1<35, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
119 "lwzu $rD, $disp($rA)">;
121 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
122 "addi $rD, $rA, $imm">;
123 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
124 "addic $rD, $rA, $imm">;
125 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
126 "addic. $rD, $rA, $imm">;
127 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
128 "addis $rD, $rA, $imm">;
129 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
130 "la $rD, $sym($rA)">;
131 def LOADHiAddr : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$sym),
132 "addis $rD, $rA, $sym">;
133 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
134 "mulli $rD, $rA, $imm">;
135 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
136 "subfic $rD, $rA, $imm">;
137 def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
139 def LIS : DForm_2_r0<15, (ops GPRC:$rD, s16imm:$imm),
142 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
143 "stmw $rS, $disp($rA)">;
144 def STB : DForm_3<38, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
145 "stb $rS, $disp($rA)">;
146 def STH : DForm_3<44, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
147 "sth $rS, $disp($rA)">;
148 def STW : DForm_3<36, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
149 "stw $rS, $disp($rA)">;
150 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
151 "stwu $rS, $disp($rA)">;
153 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
154 "andi. $dst, $src1, $src2">, isDOT;
155 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
156 "andis. $dst, $src1, $src2">, isDOT;
157 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
158 "ori $dst, $src1, $src2">;
159 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
160 "oris $dst, $src1, $src2">;
161 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
162 "xori $dst, $src1, $src2">;
163 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
164 "xoris $dst, $src1, $src2">;
165 def NOP : DForm_4_zero<24, (ops), "nop">;
166 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
167 "cmpi $crD, $L, $rA, $imm">;
168 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
169 "cmpwi $crD, $rA, $imm">;
170 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
171 "cmpdi $crD, $rA, $imm">, isPPC64;
172 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
173 "cmpli $dst, $size, $src1, $src2">;
174 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
175 "cmplwi $dst, $src1, $src2">;
176 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
177 "cmpldi $dst, $src1, $src2">, isPPC64;
179 def LFS : DForm_8<48, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
180 "lfs $rD, $disp($rA)">;
181 def LFD : DForm_8<50, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
182 "lfd $rD, $disp($rA)">;
185 def STFS : DForm_9<52, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
186 "stfs $rS, $disp($rA)">;
187 def STFD : DForm_9<54, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
188 "stfd $rS, $disp($rA)">;
191 // DS-Form instructions. Load/Store instructions available in PPC-64
194 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
195 "lwa $rT, $DS($rA)">, isPPC64;
196 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
197 "ld $rT, $DS($rA)">, isPPC64;
200 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
201 "std $rT, $DS($rA)">, isPPC64;
202 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
203 "stdu $rT, $DS($rA)">, isPPC64;
206 // X-Form instructions. Most instructions that perform an operation on a
207 // register and another register are of this type.
210 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
211 "lbzx $dst, $base, $index">;
212 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
213 "lhax $dst, $base, $index">;
214 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
215 "lhzx $dst, $base, $index">;
216 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
217 "lwax $dst, $base, $index">, isPPC64;
218 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
219 "lwzx $dst, $base, $index">;
220 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
221 "ldx $dst, $base, $index">, isPPC64;
223 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
224 "and $rA, $rS, $rB">;
225 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
226 "and. $rA, $rS, $rB">, isDOT;
227 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
228 "andc $rA, $rS, $rB">;
229 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
230 "eqv $rA, $rS, $rB">;
231 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
232 "nand $rA, $rS, $rB">;
233 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
234 "nor $rA, $rS, $rB">;
235 def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
237 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
238 "or. $rA, $rS, $rB">, isDOT;
239 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
240 "orc $rA, $rS, $rB">;
241 def SLD : XForm_6<31, 27, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
242 "sld $rA, $rS, $rB">, isPPC64;
243 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
244 "slw $rA, $rS, $rB">;
245 def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
246 "srd $rA, $rS, $rB">, isPPC64;
247 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
248 "srw $rA, $rS, $rB">;
249 def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
250 "srad $rA, $rS, $rB">, isPPC64;
251 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
252 "sraw $rA, $rS, $rB">;
253 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
254 "xor $rA, $rS, $rB">;
256 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
257 "stbx $rS, $rA, $rB">;
258 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
259 "sthx $rS, $rA, $rB">;
260 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
261 "stwx $rS, $rA, $rB">;
262 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
263 "stwux $rS, $rA, $rB">;
264 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
265 "stdx $rS, $rA, $rB">, isPPC64;
266 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
267 "stdux $rS, $rA, $rB">, isPPC64;
269 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
270 "srawi $rA, $rS, $SH">;
271 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
273 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
275 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
277 def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
278 "extsw $rA, $rS">, isPPC64;
279 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
280 "cmp $crD, $long, $rA, $rB">;
281 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
282 "cmpl $crD, $long, $rA, $rB">;
283 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
284 "cmpw $crD, $rA, $rB">;
285 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
286 "cmpd $crD, $rA, $rB">, isPPC64;
287 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
288 "cmplw $crD, $rA, $rB">;
289 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
290 "cmpld $crD, $rA, $rB">, isPPC64;
291 def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
292 "fcmpo $crD, $fA, $fB">;
293 def FCMPU : XForm_17<63, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
294 "fcmpu $crD, $fA, $fB">;
296 def LFSX : XForm_25<31, 535, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
297 "lfsx $dst, $base, $index">;
298 def LFDX : XForm_25<31, 599, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
299 "lfdx $dst, $base, $index">;
301 def FCFID : XForm_26<63, 846, (ops FPRC:$frD, FPRC:$frB),
302 "fcfid $frD, $frB">, isPPC64;
303 def FCTIDZ : XForm_26<63, 815, (ops FPRC:$frD, FPRC:$frB),
304 "fctidz $frD, $frB">, isPPC64;
305 def FCTIWZ : XForm_26<63, 15, (ops FPRC:$frD, FPRC:$frB),
306 "fctiwz $frD, $frB">;
307 def FABS : XForm_26<63, 264, (ops FPRC:$frD, FPRC:$frB),
309 def FMR : XForm_26<63, 72, (ops FPRC:$frD, FPRC:$frB),
311 def FNABS : XForm_26<63, 136, (ops FPRC:$frD, FPRC:$frB),
313 def FNEG : XForm_26<63, 40, (ops FPRC:$frD, FPRC:$frB),
315 def FRSP : XForm_26<63, 12, (ops FPRC:$frD, FPRC:$frB),
318 def STFSX : XForm_28<31, 663, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
319 "stfsx $frS, $rA, $rB">;
320 def STFDX : XForm_28<31, 727, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
321 "stfdx $frS, $rA, $rB">;
324 // XL-Form instructions. condition register logical ops.
326 def CRAND : XLForm_1<19, 257, (ops CRRC:$D, crbit:$Db,
327 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
328 "crand $Db, $Ab, $Bb">;
329 def CRANDC : XLForm_1<19, 129, (ops CRRC:$D, crbit:$Db,
330 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
331 "crandc $Db, $Ab, $Bb">;
332 def CREQV : XLForm_1<19, 289, (ops CRRC:$D, crbit:$Db,
333 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
334 "creqv $Db, $Ab, $Bb">;
335 def CRNAND : XLForm_1<19, 225, (ops CRRC:$D, crbit:$Db,
336 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
337 "crnand $Db, $Ab, $Bb">;
338 def CRNOR : XLForm_1<19, 33, (ops CRRC:$D, crbit:$Db,
339 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
340 "crnor $Db, $Ab, $Bb">;
341 def CROR : XLForm_1<19, 449, (ops CRRC:$D, crbit:$Db,
342 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
343 "cror $Db, $Ab, $Bb">;
344 def CRORC : XLForm_1<19, 417, (ops CRRC:$D, crbit:$Db,
345 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
346 "crorc $Db, $Ab, $Bb">;
347 def CRXOR : XLForm_1<19, 193, (ops CRRC:$D, crbit:$Db,
348 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
349 "crxor $Db, $Ab, $Bb">;
350 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
353 // XFX-Form instructions. Instructions that deal with SPRs
355 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
356 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
357 // which means the SPR value needs to be multiplied by a factor of 32.
358 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT">;
359 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT">;
360 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">;
361 def MTCRF : XFXForm_5<31, 0, 144, (ops CRRC:$FXM, GPRC:$rS),
363 def MFCRF : XFXForm_5<31, 1, 19, (ops GPRC:$rT, CRRC:$FXM),
365 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">;
366 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;
368 // XS-Form instructions. Just 'sradi'
370 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
371 "sradi $rA, $rS, $SH">, isPPC64;
373 // XO-Form instructions. Arithmetic instructions that can set overflow bit
375 def ADD : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
376 "add $rT, $rA, $rB">;
377 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
378 "addc $rT, $rA, $rB">;
379 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
380 "adde $rT, $rA, $rB">;
381 def DIVD : XOForm_1<31, 489, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
382 "divd $rT, $rA, $rB">, isPPC64;
383 def DIVDU : XOForm_1<31, 457, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
384 "divdu $rT, $rA, $rB">, isPPC64;
385 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
386 "divw $rT, $rA, $rB">;
387 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
388 "divwu $rT, $rA, $rB">;
389 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
390 "mulhw $rT, $rA, $rB">;
391 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
392 "mulhwu $rT, $rA, $rB">;
393 def MULLD : XOForm_1<31, 233, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
394 "mulld $rT, $rA, $rB">, isPPC64;
395 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
396 "mullw $rT, $rA, $rB">;
397 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
398 "subf $rT, $rA, $rB">;
399 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
400 "subfc $rT, $rA, $rB">;
401 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
402 "subfe $rT, $rA, $rB">;
403 def SUB : XOForm_1r<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
404 "sub $rT, $rA, $rB">;
405 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
407 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
409 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
411 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
414 // A-Form instructions. Most of the instructions executed in the FPU are of
417 def FMADD : AForm_1<63, 29,
418 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
419 "fmadd $FRT, $FRA, $FRC, $FRB">;
420 def FMADDS : AForm_1<59, 29,
421 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
422 "fmadds $FRT, $FRA, $FRC, $FRB">;
423 def FMSUB : AForm_1<63, 28,
424 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
425 "fmsub $FRT, $FRA, $FRC, $FRB">;
426 def FMSUBS : AForm_1<59, 28,
427 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
428 "fmsubs $FRT, $FRA, $FRC, $FRB">;
429 def FNMADD : AForm_1<63, 31,
430 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
431 "fnmadd $FRT, $FRA, $FRC, $FRB">;
432 def FNMADDS : AForm_1<59, 31,
433 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
434 "fnmadds $FRT, $FRA, $FRC, $FRB">;
435 def FNMSUB : AForm_1<63, 30,
436 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
437 "fnmsub $FRT, $FRA, $FRC, $FRB">;
438 def FNMSUBS : AForm_1<59, 30,
439 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
440 "fnmsubs $FRT, $FRA, $FRC, $FRB">;
441 def FSEL : AForm_1<63, 23,
442 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
443 "fsel $FRT, $FRA, $FRC, $FRB">;
444 def FADD : AForm_2<63, 21,
445 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
446 "fadd $FRT, $FRA, $FRB">;
447 def FADDS : AForm_2<59, 21,
448 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
449 "fadds $FRT, $FRA, $FRB">;
450 def FDIV : AForm_2<63, 18,
451 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
452 "fdiv $FRT, $FRA, $FRB">;
453 def FDIVS : AForm_2<59, 18,
454 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
455 "fdivs $FRT, $FRA, $FRB">;
456 def FMUL : AForm_3<63, 25,
457 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
458 "fmul $FRT, $FRA, $FRB">;
459 def FMULS : AForm_3<59, 25,
460 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
461 "fmuls $FRT, $FRA, $FRB">;
462 def FSUB : AForm_2<63, 20,
463 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
464 "fsub $FRT, $FRA, $FRB">;
465 def FSUBS : AForm_2<59, 20,
466 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
467 "fsubs $FRT, $FRA, $FRB">;
469 // M-Form instructions. rotate and mask instructions.
471 let isTwoAddress = 1 in {
472 def RLWIMI : MForm_2<20,
473 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
474 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
476 def RLWINM : MForm_2<21,
477 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
478 "rlwinm $rA, $rS, $SH, $MB, $ME">;
479 def RLWINMo : MForm_2<21,
480 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
481 "rlwinm. $rA, $rS, $SH, $MB, $ME">, isDOT;
482 def RLWNM : MForm_2<23,
483 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
484 "rlwnm $rA, $rS, $rB, $MB, $ME">;
486 // MD-Form instructions. 64 bit rotate instructions.
488 def RLDICL : MDForm_1<30, 0,
489 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
490 "rldicl $rA, $rS, $SH, $MB">, isPPC64;
491 def RLDICR : MDForm_1<30, 1,
492 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
493 "rldicr $rA, $rS, $SH, $ME">, isPPC64;
495 def PowerPCInstrInfo : InstrInfo {
498 let TSFlagsFields = [ "VMX", "PPC64" ];
499 let TSFlagsShifts = [ 0, 1 ];
501 let isLittleEndianEncoding = 1;