1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific DAG Nodes.
21 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
22 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
23 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
26 //===----------------------------------------------------------------------===//
27 // PowerPC specific transformation functions and pattern fragments.
30 def SHL32 : SDNodeXForm<imm, [{
31 // Transformation function: 31 - imm
32 return getI32Imm(31 - N->getValue());
35 def SHL64 : SDNodeXForm<imm, [{
36 // Transformation function: 63 - imm
37 return getI32Imm(63 - N->getValue());
40 def SRL32 : SDNodeXForm<imm, [{
41 // Transformation function: 32 - imm
42 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
45 def SRL64 : SDNodeXForm<imm, [{
46 // Transformation function: 64 - imm
47 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
50 def LO16 : SDNodeXForm<imm, [{
51 // Transformation function: get the low 16 bits.
52 return getI32Imm((unsigned short)N->getValue());
55 def HI16 : SDNodeXForm<imm, [{
56 // Transformation function: shift the immediate value down into the low bits.
57 return getI32Imm((unsigned)N->getValue() >> 16);
60 def HA16 : SDNodeXForm<imm, [{
61 // Transformation function: shift the immediate value down into the low bits.
62 signed int Val = N->getValue();
63 return getI32Imm((Val - (signed short)Val) >> 16);
67 def immSExt16 : PatLeaf<(imm), [{
68 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
69 // field. Used by instructions like 'addi'.
70 return (int)N->getValue() == (short)N->getValue();
72 def immZExt16 : PatLeaf<(imm), [{
73 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
74 // field. Used by instructions like 'ori'.
75 return (unsigned)N->getValue() == (unsigned short)N->getValue();
78 def imm16Shifted : PatLeaf<(imm), [{
79 // imm16Shifted predicate - True if only bits in the top 16-bits of the
80 // immediate are set. Used by instructions like 'addis'.
81 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
85 // Example of a legalize expander: Only for PPC64.
86 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
87 [(set f64:$tmp , (FCTIDZ f64:$src)),
88 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
89 (store f64:$tmp, i32:$tmpFI),
90 (set i64:$dst, (load i32:$tmpFI))],
94 //===----------------------------------------------------------------------===//
95 // PowerPC Flag Definitions.
97 class isPPC64 { bit PPC64 = 1; }
98 class isVMX { bit VMX = 1; }
100 list<Register> Defs = [CR0];
106 //===----------------------------------------------------------------------===//
107 // PowerPC Operand Definitions.
109 def u5imm : Operand<i32> {
110 let PrintMethod = "printU5ImmOperand";
112 def u6imm : Operand<i32> {
113 let PrintMethod = "printU6ImmOperand";
115 def s16imm : Operand<i32> {
116 let PrintMethod = "printS16ImmOperand";
118 def u16imm : Operand<i32> {
119 let PrintMethod = "printU16ImmOperand";
121 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
122 let PrintMethod = "printS16X4ImmOperand";
124 def target : Operand<i32> {
125 let PrintMethod = "printBranchOperand";
127 def piclabel: Operand<i32> {
128 let PrintMethod = "printPICLabel";
130 def symbolHi: Operand<i32> {
131 let PrintMethod = "printSymbolHi";
133 def symbolLo: Operand<i32> {
134 let PrintMethod = "printSymbolLo";
136 def crbitm: Operand<i8> {
137 let PrintMethod = "printcrbitm";
142 //===----------------------------------------------------------------------===//
143 // PowerPC Instruction Definitions.
145 // Pseudo-instructions:
146 def PHI : Pseudo<(ops variable_ops), "; PHI">;
149 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN">;
150 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP">;
152 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
153 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8">;
154 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4">;
156 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
157 // scheduler into a branch sequence.
158 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
159 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
160 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
161 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
162 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
163 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
164 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
168 let isTerminator = 1 in {
170 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB>;
171 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB>;
175 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
177 let isBranch = 1, isTerminator = 1 in {
178 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
179 target:$true, target:$false),
181 def B : IForm<18, 0, 0, (ops target:$func), "b $func", BrB>;
182 //def BA : IForm<18, 1, 0, (ops target:$func), "ba $func", BrB>;
183 def BL : IForm<18, 0, 1, (ops target:$func), "bl $func", BrB>;
184 //def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func", BrB>;
186 // FIXME: 4*CR# needs to be added to the BI field!
187 // This will only work for CR0 as it stands now
188 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
189 "blt $crS, $block", BrB>;
190 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
191 "ble $crS, $block", BrB>;
192 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
193 "beq $crS, $block", BrB>;
194 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
195 "bge $crS, $block", BrB>;
196 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
197 "bgt $crS, $block", BrB>;
198 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
199 "bne $crS, $block", BrB>;
203 // All calls clobber the non-callee saved registers...
204 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
205 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
207 CR0,CR1,CR5,CR6,CR7] in {
208 // Convenient aliases for call instructions
209 def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops),
211 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1,
212 (ops variable_ops), "bctrl", BrB>;
215 // D-Form instructions. Most instructions that perform an operation on a
216 // register and an immediate are of this type.
219 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
220 "lbz $rD, $disp($rA)", LdStGeneral>;
221 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
222 "lha $rD, $disp($rA)", LdStLHA>;
223 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
224 "lhz $rD, $disp($rA)", LdStGeneral>;
225 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
226 "lmw $rD, $disp($rA)", LdStLMW>;
227 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
228 "lwz $rD, $disp($rA)", LdStGeneral>;
229 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
230 "lwzu $rD, $disp($rA)", LdStGeneral>;
232 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
233 "addi $rD, $rA, $imm", IntGeneral,
234 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
235 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
236 "addic $rD, $rA, $imm", IntGeneral,
238 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
239 "addic. $rD, $rA, $imm", IntGeneral,
241 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
242 "addis $rD, $rA, $imm", IntGeneral,
243 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
244 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
245 "la $rD, $sym($rA)", IntGeneral,
247 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
248 "mulli $rD, $rA, $imm", IntMulLI,
249 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
250 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
251 "subfic $rD, $rA, $imm", IntGeneral,
252 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
253 def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
254 "li $rD, $imm", IntGeneral,
255 [(set GPRC:$rD, immSExt16:$imm)]>;
256 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
257 "lis $rD, $imm", IntGeneral,
258 [(set GPRC:$rD, imm16Shifted:$imm)]>;
260 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
261 "stmw $rS, $disp($rA)", LdStLMW>;
262 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
263 "stb $rS, $disp($rA)", LdStGeneral>;
264 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
265 "sth $rS, $disp($rA)", LdStGeneral>;
266 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
267 "stw $rS, $disp($rA)", LdStGeneral>;
268 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
269 "stwu $rS, $disp($rA)", LdStGeneral>;
271 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
272 "andi. $dst, $src1, $src2", IntGeneral,
274 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
275 "andis. $dst, $src1, $src2", IntGeneral,
277 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
278 "ori $dst, $src1, $src2", IntGeneral,
279 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
280 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
281 "oris $dst, $src1, $src2", IntGeneral,
282 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
283 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
284 "xori $dst, $src1, $src2", IntGeneral,
285 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
286 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
287 "xoris $dst, $src1, $src2", IntGeneral,
288 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
289 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral>;
290 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
291 "cmpi $crD, $L, $rA, $imm", IntCompare>;
292 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
293 "cmpwi $crD, $rA, $imm", IntCompare>;
294 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
295 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
296 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
297 "cmpli $dst, $size, $src1, $src2", IntCompare>;
298 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
299 "cmplwi $dst, $src1, $src2", IntCompare>;
300 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
301 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
303 def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
304 "lfs $rD, $disp($rA)", LdStLFDU>;
305 def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
306 "lfd $rD, $disp($rA)", LdStLFD>;
309 def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
310 "stfs $rS, $disp($rA)", LdStUX>;
311 def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
312 "stfd $rS, $disp($rA)", LdStUX>;
315 // DS-Form instructions. Load/Store instructions available in PPC-64
318 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
319 "lwa $rT, $DS($rA)", LdStLWA>, isPPC64;
320 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
321 "ld $rT, $DS($rA)", LdStLD>, isPPC64;
324 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
325 "std $rT, $DS($rA)", LdStSTD>, isPPC64;
326 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
327 "stdu $rT, $DS($rA)", LdStSTD>, isPPC64;
330 // X-Form instructions. Most instructions that perform an operation on a
331 // register and another register are of this type.
334 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
335 "lbzx $dst, $base, $index", LdStGeneral>;
336 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
337 "lhax $dst, $base, $index", LdStLHA>;
338 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
339 "lhzx $dst, $base, $index", LdStGeneral>;
340 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
341 "lwax $dst, $base, $index", LdStLHA>, isPPC64;
342 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
343 "lwzx $dst, $base, $index", LdStGeneral>;
344 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
345 "ldx $dst, $base, $index", LdStLD>, isPPC64;
347 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
348 "nand $rA, $rS, $rB", IntGeneral,
349 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
350 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
351 "and $rA, $rS, $rB", IntGeneral,
352 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
353 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
354 "and. $rA, $rS, $rB", IntGeneral,
356 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
357 "andc $rA, $rS, $rB", IntGeneral,
358 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
359 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
360 "or $rA, $rS, $rB", IntGeneral,
361 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
362 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
363 "or $rA, $rS, $rB", IntGeneral,
364 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
365 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
366 "or $rA, $rS, $rB", IntGeneral,
368 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
369 "or $rA, $rS, $rB", IntGeneral,
371 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
372 "nor $rA, $rS, $rB", IntGeneral,
373 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
374 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
375 "or. $rA, $rS, $rB", IntGeneral,
377 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
378 "orc $rA, $rS, $rB", IntGeneral,
379 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
380 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
381 "eqv $rA, $rS, $rB", IntGeneral,
382 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
383 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
384 "xor $rA, $rS, $rB", IntGeneral,
385 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
386 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
387 "sld $rA, $rS, $rB", IntRotateD,
388 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
389 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
390 "slw $rA, $rS, $rB", IntGeneral,
391 [(set GPRC:$rA, (shl GPRC:$rS, GPRC:$rB))]>;
392 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
393 "srd $rA, $rS, $rB", IntRotateD,
394 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
395 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
396 "srw $rA, $rS, $rB", IntGeneral,
397 [(set GPRC:$rA, (srl GPRC:$rS, GPRC:$rB))]>;
398 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
399 "srad $rA, $rS, $rB", IntRotateD,
400 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
401 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
402 "sraw $rA, $rS, $rB", IntShift,
403 [(set GPRC:$rA, (sra GPRC:$rS, GPRC:$rB))]>;
405 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
406 "stbx $rS, $rA, $rB", LdStGeneral>;
407 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
408 "sthx $rS, $rA, $rB", LdStGeneral>;
409 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
410 "stwx $rS, $rA, $rB", LdStGeneral>;
411 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
412 "stwux $rS, $rA, $rB", LdStGeneral>;
413 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
414 "stdx $rS, $rA, $rB", LdStSTD>, isPPC64;
415 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
416 "stdux $rS, $rA, $rB", LdStSTD>, isPPC64;
418 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
419 "srawi $rA, $rS, $SH", IntShift,
420 [(set GPRC:$rA, (sra GPRC:$rS, imm:$SH))]>;
421 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
422 "cntlzw $rA, $rS", IntGeneral,
423 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
424 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
425 "extsb $rA, $rS", IntGeneral,
426 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
427 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
428 "extsh $rA, $rS", IntGeneral,
429 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
430 def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
431 "extsw $rA, $rS", IntRotateD,
433 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
434 "cmp $crD, $long, $rA, $rB", IntCompare>;
435 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
436 "cmpl $crD, $long, $rA, $rB", IntCompare>;
437 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
438 "cmpw $crD, $rA, $rB", IntCompare>;
439 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
440 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
441 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
442 "cmplw $crD, $rA, $rB", IntCompare>;
443 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
444 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
445 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
446 // "fcmpo $crD, $fA, $fB", FPCompare>;
447 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
448 "fcmpu $crD, $fA, $fB", FPCompare>;
449 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
450 "fcmpu $crD, $fA, $fB", FPCompare>;
453 def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
454 "lfsx $dst, $base, $index", LdStLFDU>;
455 def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
456 "lfdx $dst, $base, $index", LdStLFDU>;
458 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
459 "fcfid $frD, $frB", FPGeneral,
460 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
461 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
462 "fctidz $frD, $frB", FPGeneral,
463 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
464 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
465 "fctiwz $frD, $frB", FPGeneral,
466 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
467 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
468 "frsp $frD, $frB", FPGeneral,
469 [(set F4RC:$frD, (fround F8RC:$frB))]>;
470 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
471 "fsqrt $frD, $frB", FPSqrt,
472 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
473 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
474 "fsqrts $frD, $frB", FPSqrt,
475 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
477 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
478 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
479 "fmr $frD, $frB", FPGeneral,
480 []>; // (set F4RC:$frD, F4RC:$frB)
481 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
482 "fmr $frD, $frB", FPGeneral,
483 []>; // (set F8RC:$frD, F8RC:$frB)
484 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
485 "fmr $frD, $frB", FPGeneral,
486 [(set F8RC:$frD, (fextend F4RC:$frB))]>;
488 // These are artificially split into two different forms, for 4/8 byte FP.
489 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
490 "fabs $frD, $frB", FPGeneral,
491 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
492 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
493 "fabs $frD, $frB", FPGeneral,
494 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
495 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
496 "fnabs $frD, $frB", FPGeneral,
497 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
498 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
499 "fnabs $frD, $frB", FPGeneral,
500 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
501 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
502 "fneg $frD, $frB", FPGeneral,
503 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
504 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
505 "fneg $frD, $frB", FPGeneral,
506 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
510 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
511 "stfsx $frS, $rA, $rB", LdStUX>;
512 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
513 "stfdx $frS, $rA, $rB", LdStUX>;
516 // XL-Form instructions. condition register logical ops.
518 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
519 "mcrf $BF, $BFA", BrMCR>;
521 // XFX-Form instructions. Instructions that deal with SPRs
523 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
524 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
525 // which means the SPR value needs to be multiplied by a factor of 32.
526 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
527 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT", SprMFSPR>;
528 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>;
529 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
530 "mtcrf $FXM, $rS", BrMCRX>;
531 def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
532 "mfcr $rT, $FXM", SprMFCR>;
533 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
534 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
536 // XS-Form instructions. Just 'sradi'
538 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
539 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
541 // XO-Form instructions. Arithmetic instructions that can set overflow bit
543 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
544 "add $rT, $rA, $rB", IntGeneral,
545 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
546 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
547 "add $rT, $rA, $rB", IntGeneral,
548 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
549 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
550 "addc $rT, $rA, $rB", IntGeneral,
552 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
553 "adde $rT, $rA, $rB", IntGeneral,
555 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
556 "divd $rT, $rA, $rB", IntDivD,
557 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
558 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
559 "divdu $rT, $rA, $rB", IntDivD,
560 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
561 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
562 "divw $rT, $rA, $rB", IntDivW,
563 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
564 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
565 "divwu $rT, $rA, $rB", IntDivW,
566 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
567 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
568 "mulhd $rT, $rA, $rB", IntMulHW,
569 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
570 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
571 "mulhdu $rT, $rA, $rB", IntMulHWU,
572 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
573 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
574 "mulhw $rT, $rA, $rB", IntMulHW,
575 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
576 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
577 "mulhwu $rT, $rA, $rB", IntMulHWU,
578 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
579 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
580 "mulld $rT, $rA, $rB", IntMulHD,
581 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
582 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
583 "mullw $rT, $rA, $rB", IntMulHW,
584 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
585 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
586 "subf $rT, $rA, $rB", IntGeneral,
587 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
588 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
589 "subfc $rT, $rA, $rB", IntGeneral,
591 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
592 "subfe $rT, $rA, $rB", IntGeneral,
594 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
595 "addme $rT, $rA", IntGeneral,
597 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
598 "addze $rT, $rA", IntGeneral,
600 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
601 "neg $rT, $rA", IntGeneral,
602 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
603 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
604 "subfze $rT, $rA", IntGeneral,
607 // A-Form instructions. Most of the instructions executed in the FPU are of
610 def FMADD : AForm_1<63, 29,
611 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
612 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
613 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
615 def FMADDS : AForm_1<59, 29,
616 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
617 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
618 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
620 def FMSUB : AForm_1<63, 28,
621 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
622 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
623 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
625 def FMSUBS : AForm_1<59, 28,
626 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
627 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
628 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
630 def FNMADD : AForm_1<63, 31,
631 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
632 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
633 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
635 def FNMADDS : AForm_1<59, 31,
636 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
637 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
638 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
640 def FNMSUB : AForm_1<63, 30,
641 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
642 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
643 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
645 def FNMSUBS : AForm_1<59, 30,
646 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
647 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
648 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
650 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
651 // having 4 of these, force the comparison to always be an 8-byte double (code
652 // should use an FMRSD if the input comparison value really wants to be a float)
653 // and 4/8 byte forms for the result and operand type..
654 def FSELD : AForm_1<63, 23,
655 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
656 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
658 def FSELS : AForm_1<63, 23,
659 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
660 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
662 def FADD : AForm_2<63, 21,
663 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
664 "fadd $FRT, $FRA, $FRB", FPGeneral,
665 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
666 def FADDS : AForm_2<59, 21,
667 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
668 "fadds $FRT, $FRA, $FRB", FPGeneral,
669 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
670 def FDIV : AForm_2<63, 18,
671 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
672 "fdiv $FRT, $FRA, $FRB", FPDivD,
673 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
674 def FDIVS : AForm_2<59, 18,
675 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
676 "fdivs $FRT, $FRA, $FRB", FPDivS,
677 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
678 def FMUL : AForm_3<63, 25,
679 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
680 "fmul $FRT, $FRA, $FRB", FPFused,
681 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
682 def FMULS : AForm_3<59, 25,
683 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
684 "fmuls $FRT, $FRA, $FRB", FPGeneral,
685 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
686 def FSUB : AForm_2<63, 20,
687 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
688 "fsub $FRT, $FRA, $FRB", FPGeneral,
689 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
690 def FSUBS : AForm_2<59, 20,
691 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
692 "fsubs $FRT, $FRA, $FRB", FPGeneral,
693 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
695 // M-Form instructions. rotate and mask instructions.
697 let isTwoAddress = 1, isCommutable = 1 in {
698 // RLWIMI can be commuted if the rotate amount is zero.
699 def RLWIMI : MForm_2<20,
700 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
701 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
703 def RLDIMI : MDForm_1<30, 3,
704 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
705 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
708 def RLWINM : MForm_2<21,
709 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
710 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
712 def RLWINMo : MForm_2<21,
713 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
714 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
716 def RLWNM : MForm_2<23,
717 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
718 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
721 // MD-Form instructions. 64 bit rotate instructions.
723 def RLDICL : MDForm_1<30, 0,
724 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
725 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
727 def RLDICR : MDForm_1<30, 1,
728 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
729 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
732 //===----------------------------------------------------------------------===//
733 // PowerPC Instruction Patterns
736 // Arbitrary immediate support. Implement in terms of LIS/ORI.
737 def : Pat<(i32 imm:$imm),
738 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
740 // Implement the 'not' operation with the NOR instruction.
741 def NOT : Pat<(not GPRC:$in),
742 (NOR GPRC:$in, GPRC:$in)>;
744 // ADD an arbitrary immediate.
745 def : Pat<(add GPRC:$in, imm:$imm),
746 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
747 // OR an arbitrary immediate.
748 def : Pat<(or GPRC:$in, imm:$imm),
749 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
750 // XOR an arbitrary immediate.
751 def : Pat<(xor GPRC:$in, imm:$imm),
752 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
753 def : Pat<(or (shl GPRC:$rS, GPRC:$rB),
754 (srl GPRC:$rS, (sub 32, GPRC:$rB))),
755 (RLWNM GPRC:$rS, GPRC:$rB, 0, 31)>;
757 def : Pat<(zext GPRC:$in),
758 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
759 def : Pat<(anyext GPRC:$in),
760 (OR4To8 GPRC:$in, GPRC:$in)>;
761 def : Pat<(trunc G8RC:$in),
762 (OR8To4 G8RC:$in, G8RC:$in)>;
765 def : Pat<(shl GPRC:$in, imm:$imm),
766 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
767 def : Pat<(shl G8RC:$in, imm:$imm),
768 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
770 def : Pat<(srl GPRC:$in, imm:$imm),
771 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
772 def : Pat<(srl G8RC:$in, imm:$imm),
773 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
775 // Same as above, but using a temporary. FIXME: implement temporaries :)
777 def : Pattern<(xor GPRC:$in, imm:$imm),
778 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
779 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
782 //===----------------------------------------------------------------------===//
783 // PowerPCInstrInfo Definition
785 def PowerPCInstrInfo : InstrInfo {
788 let TSFlagsFields = [ "VMX", "PPC64" ];
789 let TSFlagsShifts = [ 0, 1 ];
791 let isLittleEndianEncoding = 1;