1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC specific transformation functions and pattern fragments.
21 def LO16 : SDNodeXForm<imm, [{
22 // Transformation function: get the low 16 bits.
23 return getI32Imm((unsigned short)N->getValue());
26 def HI16 : SDNodeXForm<imm, [{
27 // Transformation function: shift the immediate value down into the low bits.
28 return getI32Imm((unsigned)N->getValue() >> 16);
31 def HA16 : SDNodeXForm<imm, [{
32 // Transformation function: shift the immediate value down into the low bits.
33 signed int Val = N->getValue();
34 return getI32Imm((Val - (signed short)Val) >> 16);
38 def immSExt16 : PatLeaf<(imm), [{
39 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
40 // field. Used by instructions like 'addi'.
41 return (int)N->getValue() == (short)N->getValue();
43 def immZExt16 : PatLeaf<(imm), [{
44 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
45 // field. Used by instructions like 'ori'.
46 return (unsigned)N->getValue() == (unsigned short)N->getValue();
49 def imm16Shifted : PatLeaf<(imm), [{
50 // imm16Shifted predicate - True if only bits in the top 16-bits of the
51 // immediate are set. Used by instructions like 'addis'.
52 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
56 // Example of a legalize expander: Only for PPC64.
57 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
58 [(set f64:$tmp , (FCTIDZ f64:$src)),
59 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
60 (store f64:$tmp, i32:$tmpFI),
61 (set i64:$dst, (load i32:$tmpFI))],
65 //===----------------------------------------------------------------------===//
66 // PowerPC Flag Definitions.
68 class isPPC64 { bit PPC64 = 1; }
69 class isVMX { bit VMX = 1; }
71 list<Register> Defs = [CR0];
77 //===----------------------------------------------------------------------===//
78 // PowerPC Operand Definitions.
80 def u5imm : Operand<i32> {
81 let PrintMethod = "printU5ImmOperand";
83 def u6imm : Operand<i32> {
84 let PrintMethod = "printU6ImmOperand";
86 def s16imm : Operand<i32> {
87 let PrintMethod = "printS16ImmOperand";
89 def u16imm : Operand<i32> {
90 let PrintMethod = "printU16ImmOperand";
92 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
93 let PrintMethod = "printS16X4ImmOperand";
95 def target : Operand<i32> {
96 let PrintMethod = "printBranchOperand";
98 def piclabel: Operand<i32> {
99 let PrintMethod = "printPICLabel";
101 def symbolHi: Operand<i32> {
102 let PrintMethod = "printSymbolHi";
104 def symbolLo: Operand<i32> {
105 let PrintMethod = "printSymbolLo";
107 def crbitm: Operand<i8> {
108 let PrintMethod = "printcrbitm";
113 //===----------------------------------------------------------------------===//
114 // PowerPC Instruction Definitions.
116 // Pseudo-instructions:
117 def PHI : Pseudo<(ops variable_ops), "; PHI">;
120 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN">;
121 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP">;
123 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
124 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8">;
125 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4">;
127 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
128 // scheduler into a branch sequence.
129 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
130 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
131 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
132 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
133 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
134 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
135 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
139 let isTerminator = 1 in {
141 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">;
142 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">;
146 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
148 let isBranch = 1, isTerminator = 1 in {
149 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
150 target:$true, target:$false),
152 def B : IForm<18, 0, 0, (ops target:$func), "b $func">;
153 //def BA : IForm<18, 1, 0, (ops target:$func), "ba $func">;
154 def BL : IForm<18, 0, 1, (ops target:$func), "bl $func">;
155 //def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func">;
157 // FIXME: 4*CR# needs to be added to the BI field!
158 // This will only work for CR0 as it stands now
159 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
161 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
163 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
165 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
167 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
169 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
174 // All calls clobber the non-callee saved registers...
175 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
176 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
178 CR0,CR1,CR5,CR6,CR7] in {
179 // Convenient aliases for call instructions
180 def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops), "bl $func">;
181 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1,
182 (ops variable_ops), "bctrl">;
185 // D-Form instructions. Most instructions that perform an operation on a
186 // register and an immediate are of this type.
189 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
190 "lbz $rD, $disp($rA)">;
191 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
192 "lha $rD, $disp($rA)">;
193 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
194 "lhz $rD, $disp($rA)">;
195 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
196 "lmw $rD, $disp($rA)">;
197 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
198 "lwz $rD, $disp($rA)">;
199 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
200 "lwzu $rD, $disp($rA)">;
202 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
203 "addi $rD, $rA, $imm",
204 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
205 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
206 "addic $rD, $rA, $imm",
208 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
209 "addic. $rD, $rA, $imm",
211 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
212 "addis $rD, $rA, $imm",
213 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
214 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
217 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
218 "mulli $rD, $rA, $imm",
219 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
220 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
221 "subfic $rD, $rA, $imm",
222 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
223 def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
225 [(set GPRC:$rD, immSExt16:$imm)]>;
226 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
228 [(set GPRC:$rD, imm16Shifted:$imm)]>;
230 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
231 "stmw $rS, $disp($rA)">;
232 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
233 "stb $rS, $disp($rA)">;
234 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
235 "sth $rS, $disp($rA)">;
236 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
237 "stw $rS, $disp($rA)">;
238 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
239 "stwu $rS, $disp($rA)">;
241 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
242 "andi. $dst, $src1, $src2",
244 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
245 "andis. $dst, $src1, $src2",
247 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
248 "ori $dst, $src1, $src2",
249 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
250 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
251 "oris $dst, $src1, $src2",
252 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
253 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
254 "xori $dst, $src1, $src2",
255 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
256 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
257 "xoris $dst, $src1, $src2",
258 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
259 def NOP : DForm_4_zero<24, (ops), "nop">;
260 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
261 "cmpi $crD, $L, $rA, $imm">;
262 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
263 "cmpwi $crD, $rA, $imm">;
264 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
265 "cmpdi $crD, $rA, $imm">, isPPC64;
266 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
267 "cmpli $dst, $size, $src1, $src2">;
268 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
269 "cmplwi $dst, $src1, $src2">;
270 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
271 "cmpldi $dst, $src1, $src2">, isPPC64;
273 def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
274 "lfs $rD, $disp($rA)">;
275 def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
276 "lfd $rD, $disp($rA)">;
279 def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
280 "stfs $rS, $disp($rA)">;
281 def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
282 "stfd $rS, $disp($rA)">;
285 // DS-Form instructions. Load/Store instructions available in PPC-64
288 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
289 "lwa $rT, $DS($rA)">, isPPC64;
290 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
291 "ld $rT, $DS($rA)">, isPPC64;
294 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
295 "std $rT, $DS($rA)">, isPPC64;
296 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
297 "stdu $rT, $DS($rA)">, isPPC64;
300 // X-Form instructions. Most instructions that perform an operation on a
301 // register and another register are of this type.
304 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
305 "lbzx $dst, $base, $index">;
306 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
307 "lhax $dst, $base, $index">;
308 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
309 "lhzx $dst, $base, $index">;
310 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
311 "lwax $dst, $base, $index">, isPPC64;
312 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
313 "lwzx $dst, $base, $index">;
314 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
315 "ldx $dst, $base, $index">, isPPC64;
317 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
318 "nand $rA, $rS, $rB",
319 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
320 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
322 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
323 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
324 "and. $rA, $rS, $rB",
326 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
327 "andc $rA, $rS, $rB",
328 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
329 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
331 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
332 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
334 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
335 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
337 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
338 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
341 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
343 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
344 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
346 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
347 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
349 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
350 def SLD : XForm_6<31, 27, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
353 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
355 [(set GPRC:$rA, (shl GPRC:$rS, GPRC:$rB))]>;
356 def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
359 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
361 [(set GPRC:$rA, (srl GPRC:$rS, GPRC:$rB))]>;
362 def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
363 "srad $rA, $rS, $rB",
365 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
366 "sraw $rA, $rS, $rB",
367 [(set GPRC:$rA, (sra GPRC:$rS, GPRC:$rB))]>;
369 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
370 "stbx $rS, $rA, $rB">;
371 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
372 "sthx $rS, $rA, $rB">;
373 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
374 "stwx $rS, $rA, $rB">;
375 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
376 "stwux $rS, $rA, $rB">;
377 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
378 "stdx $rS, $rA, $rB">, isPPC64;
379 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
380 "stdux $rS, $rA, $rB">, isPPC64;
382 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
383 "srawi $rA, $rS, $SH",
384 [(set GPRC:$rA, (sra GPRC:$rS, imm:$SH))]>;
385 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
387 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
388 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
390 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
391 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
393 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
394 def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
397 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
398 "cmp $crD, $long, $rA, $rB">;
399 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
400 "cmpl $crD, $long, $rA, $rB">;
401 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
402 "cmpw $crD, $rA, $rB">;
403 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
404 "cmpd $crD, $rA, $rB">, isPPC64;
405 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
406 "cmplw $crD, $rA, $rB">;
407 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
408 "cmpld $crD, $rA, $rB">, isPPC64;
409 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
410 // "fcmpo $crD, $fA, $fB">;
411 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
412 "fcmpu $crD, $fA, $fB">;
413 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
414 "fcmpu $crD, $fA, $fB">;
417 def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
418 "lfsx $dst, $base, $index">;
419 def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
420 "lfdx $dst, $base, $index">;
422 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
425 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
428 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
431 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
433 [(set F4RC:$frD, (fround F8RC:$frB))]>;
434 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
436 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
437 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
439 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
441 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
442 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
444 []>; // (set F4RC:$frD, F4RC:$frB)
445 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
447 []>; // (set F8RC:$frD, F8RC:$frB)
448 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
450 [(set F8RC:$frD, (fextend F4RC:$frB))]>;
452 // These are artificially split into two different forms, for 4/8 byte FP.
453 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
455 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
456 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
458 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
459 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
461 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
462 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
464 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
465 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
467 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
468 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
470 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
474 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
475 "stfsx $frS, $rA, $rB">;
476 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
477 "stfdx $frS, $rA, $rB">;
480 // XL-Form instructions. condition register logical ops.
482 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
485 // XFX-Form instructions. Instructions that deal with SPRs
487 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
488 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
489 // which means the SPR value needs to be multiplied by a factor of 32.
490 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT">;
491 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT">;
492 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">;
493 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
495 def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
497 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">;
498 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;
500 // XS-Form instructions. Just 'sradi'
502 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
503 "sradi $rA, $rS, $SH">, isPPC64;
505 // XO-Form instructions. Arithmetic instructions that can set overflow bit
507 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
509 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
510 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
512 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
513 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
514 "addc $rT, $rA, $rB",
516 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
517 "adde $rT, $rA, $rB",
519 def DIVD : XOForm_1<31, 489, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
520 "divd $rT, $rA, $rB",
522 def DIVDU : XOForm_1<31, 457, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
523 "divdu $rT, $rA, $rB",
525 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
526 "divw $rT, $rA, $rB",
527 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
528 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
529 "divwu $rT, $rA, $rB",
530 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
531 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
532 "mulhw $rT, $rA, $rB",
533 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
534 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
535 "mulhwu $rT, $rA, $rB",
536 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
537 def MULLD : XOForm_1<31, 233, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
538 "mulld $rT, $rA, $rB",
540 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
541 "mullw $rT, $rA, $rB",
542 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
543 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
544 "subf $rT, $rA, $rB",
545 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
546 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
547 "subfc $rT, $rA, $rB",
549 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
550 "subfe $rT, $rA, $rB",
552 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
555 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
558 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
560 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
561 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
565 // A-Form instructions. Most of the instructions executed in the FPU are of
568 def FMADD : AForm_1<63, 29,
569 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
570 "fmadd $FRT, $FRA, $FRC, $FRB",
571 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
573 def FMADDS : AForm_1<59, 29,
574 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
575 "fmadds $FRT, $FRA, $FRC, $FRB",
576 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
578 def FMSUB : AForm_1<63, 28,
579 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
580 "fmsub $FRT, $FRA, $FRC, $FRB",
581 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
583 def FMSUBS : AForm_1<59, 28,
584 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
585 "fmsubs $FRT, $FRA, $FRC, $FRB",
586 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
588 def FNMADD : AForm_1<63, 31,
589 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
590 "fnmadd $FRT, $FRA, $FRC, $FRB",
591 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
593 def FNMADDS : AForm_1<59, 31,
594 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
595 "fnmadds $FRT, $FRA, $FRC, $FRB",
596 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
598 def FNMSUB : AForm_1<63, 30,
599 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
600 "fnmsub $FRT, $FRA, $FRC, $FRB",
601 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
603 def FNMSUBS : AForm_1<59, 30,
604 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
605 "fnmsubs $FRT, $FRA, $FRC, $FRB",
606 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
608 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
609 // having 4 of these, force the comparison to always be an 8-byte double (code
610 // should use an FMRSD if the input comparison value really wants to be a float)
611 // and 4/8 byte forms for the result and operand type..
612 def FSELD : AForm_1<63, 23,
613 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
614 "fsel $FRT, $FRA, $FRC, $FRB",
616 def FSELS : AForm_1<63, 23,
617 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
618 "fsel $FRT, $FRA, $FRC, $FRB",
620 def FADD : AForm_2<63, 21,
621 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
622 "fadd $FRT, $FRA, $FRB",
623 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
624 def FADDS : AForm_2<59, 21,
625 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
626 "fadds $FRT, $FRA, $FRB",
627 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
628 def FDIV : AForm_2<63, 18,
629 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
630 "fdiv $FRT, $FRA, $FRB",
631 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
632 def FDIVS : AForm_2<59, 18,
633 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
634 "fdivs $FRT, $FRA, $FRB",
635 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
636 def FMUL : AForm_3<63, 25,
637 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
638 "fmul $FRT, $FRA, $FRB",
639 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
640 def FMULS : AForm_3<59, 25,
641 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
642 "fmuls $FRT, $FRA, $FRB",
643 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
644 def FSUB : AForm_2<63, 20,
645 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
646 "fsub $FRT, $FRA, $FRB",
647 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
648 def FSUBS : AForm_2<59, 20,
649 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
650 "fsubs $FRT, $FRA, $FRB",
651 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
653 // M-Form instructions. rotate and mask instructions.
655 let isTwoAddress = 1, isCommutable = 1 in {
656 // RLWIMI can be commuted if the rotate amount is zero.
657 def RLWIMI : MForm_2<20,
658 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
659 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
660 def RLDIMI : MDForm_1<30, 3,
661 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
662 "rldimi $rA, $rS, $SH, $MB">, isPPC64;
664 def RLWINM : MForm_2<21,
665 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
666 "rlwinm $rA, $rS, $SH, $MB, $ME">;
667 def RLWINMo : MForm_2<21,
668 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
669 "rlwinm. $rA, $rS, $SH, $MB, $ME">, isDOT;
670 def RLWNM : MForm_2<23,
671 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
672 "rlwnm $rA, $rS, $rB, $MB, $ME">;
674 // MD-Form instructions. 64 bit rotate instructions.
676 def RLDICL : MDForm_1<30, 0,
677 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
678 "rldicl $rA, $rS, $SH, $MB">, isPPC64;
679 def RLDICR : MDForm_1<30, 1,
680 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
681 "rldicr $rA, $rS, $SH, $ME">, isPPC64;
683 //===----------------------------------------------------------------------===//
684 // PowerPC Instruction Patterns
687 // Arbitrary immediate support. Implement in terms of LIS/ORI.
688 def : Pat<(i32 imm:$imm),
689 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
691 // Implement the 'not' operation with the NOR instruction.
692 def NOT : Pat<(not GPRC:$in),
693 (NOR GPRC:$in, GPRC:$in)>;
695 // ADD an arbitrary immediate.
696 def : Pat<(add GPRC:$in, imm:$imm),
697 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
698 // OR an arbitrary immediate.
699 def : Pat<(or GPRC:$in, imm:$imm),
700 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
701 // XOR an arbitrary immediate.
702 def : Pat<(xor GPRC:$in, imm:$imm),
703 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
706 // Same as above, but using a temporary. FIXME: implement temporaries :)
708 def : Pattern<(xor GPRC:$in, imm:$imm),
709 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
710 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
714 //===----------------------------------------------------------------------===//
715 // PowerPCInstrInfo Definition
717 def PowerPCInstrInfo : InstrInfo {
720 let TSFlagsFields = [ "VMX", "PPC64" ];
721 let TSFlagsShifts = [ 0, 1 ];
723 let isLittleEndianEncoding = 1;