1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 2, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPClarx : SDTypeProfile<1, 1, [
46 SDTCisInt<0>, SDTCisPtrTy<1>
48 def SDT_PPCstcx : SDTypeProfile<0, 2, [
49 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
53 SDTCisPtrTy<0>, SDTCisVT<1, i32>
56 def SDT_PPCnop : SDTypeProfile<0, 0, []>;
58 //===----------------------------------------------------------------------===//
59 // PowerPC specific DAG Nodes.
62 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
63 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
64 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
65 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
66 [SDNPHasChain, SDNPMayStore]>;
68 // This sequence is used for long double->int conversions. It changes the
69 // bits in the FPSCR which is not modelled.
70 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
72 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
73 [SDNPInGlue, SDNPOutGlue]>;
74 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
75 [SDNPInGlue, SDNPOutGlue]>;
76 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
77 [SDNPInGlue, SDNPOutGlue]>;
78 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
83 def PPCfsel : SDNode<"PPCISD::FSEL",
84 // Type constraint for fsel.
85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
88 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
89 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
90 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
91 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
92 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
94 def PPCldGotTprel : SDNode<"PPCISD::LD_GOT_TPREL", SDTIntBinOp, [SDNPMayLoad]>;
95 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
97 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
99 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
100 // amounts. These nodes are generated by the multi-precision shift code.
101 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
102 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
103 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
105 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
106 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
107 [SDNPHasChain, SDNPMayStore]>;
109 // These are target-independent nodes, but have target-specific formats.
110 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
111 [SDNPHasChain, SDNPOutGlue]>;
112 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
113 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
115 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
116 def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall,
117 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall,
120 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
122 def PPCcall_nop_SVR4 : SDNode<"PPCISD::CALL_NOP_SVR4", SDT_PPCCall,
123 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
125 def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInGlue, SDNPOutGlue]>;
126 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
127 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
128 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
129 [SDNPHasChain, SDNPSideEffect,
130 SDNPInGlue, SDNPOutGlue]>;
131 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
132 [SDNPHasChain, SDNPSideEffect,
133 SDNPInGlue, SDNPOutGlue]>;
134 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
135 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
136 def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone,
137 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
140 def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone,
141 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
144 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
145 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
147 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
148 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
150 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
151 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
153 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
154 [SDNPHasChain, SDNPOptInGlue]>;
156 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
157 [SDNPHasChain, SDNPMayLoad]>;
158 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
159 [SDNPHasChain, SDNPMayStore]>;
161 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
162 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
163 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
164 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
165 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
167 // Instructions to support atomic operations
168 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
169 [SDNPHasChain, SDNPMayLoad]>;
170 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
171 [SDNPHasChain, SDNPMayStore]>;
173 // Instructions to support medium code model
174 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
175 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
176 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
179 // Instructions to support dynamic alloca.
180 def SDTDynOp : SDTypeProfile<1, 2, []>;
181 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
183 //===----------------------------------------------------------------------===//
184 // PowerPC specific transformation functions and pattern fragments.
187 def SHL32 : SDNodeXForm<imm, [{
188 // Transformation function: 31 - imm
189 return getI32Imm(31 - N->getZExtValue());
192 def SRL32 : SDNodeXForm<imm, [{
193 // Transformation function: 32 - imm
194 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
197 def LO16 : SDNodeXForm<imm, [{
198 // Transformation function: get the low 16 bits.
199 return getI32Imm((unsigned short)N->getZExtValue());
202 def HI16 : SDNodeXForm<imm, [{
203 // Transformation function: shift the immediate value down into the low bits.
204 return getI32Imm((unsigned)N->getZExtValue() >> 16);
207 def HA16 : SDNodeXForm<imm, [{
208 // Transformation function: shift the immediate value down into the low bits.
209 signed int Val = N->getZExtValue();
210 return getI32Imm((Val - (signed short)Val) >> 16);
212 def MB : SDNodeXForm<imm, [{
213 // Transformation function: get the start bit of a mask
215 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
216 return getI32Imm(mb);
219 def ME : SDNodeXForm<imm, [{
220 // Transformation function: get the end bit of a mask
222 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
223 return getI32Imm(me);
225 def maskimm32 : PatLeaf<(imm), [{
226 // maskImm predicate - True if immediate is a run of ones.
228 if (N->getValueType(0) == MVT::i32)
229 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
234 def immSExt16 : PatLeaf<(imm), [{
235 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
236 // field. Used by instructions like 'addi'.
237 if (N->getValueType(0) == MVT::i32)
238 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
240 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
242 def immZExt16 : PatLeaf<(imm), [{
243 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
244 // field. Used by instructions like 'ori'.
245 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
248 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
249 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
250 // identical in 32-bit mode, but in 64-bit mode, they return true if the
251 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
253 def imm16ShiftedZExt : PatLeaf<(imm), [{
254 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
255 // immediate are set. Used by instructions like 'xoris'.
256 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
259 def imm16ShiftedSExt : PatLeaf<(imm), [{
260 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
261 // immediate are set. Used by instructions like 'addis'. Identical to
262 // imm16ShiftedZExt in 32-bit mode.
263 if (N->getZExtValue() & 0xFFFF) return false;
264 if (N->getValueType(0) == MVT::i32)
266 // For 64-bit, make sure it is sext right.
267 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
271 //===----------------------------------------------------------------------===//
272 // PowerPC Flag Definitions.
274 class isPPC64 { bit PPC64 = 1; }
276 list<Register> Defs = [CR0];
280 class RegConstraint<string C> {
281 string Constraints = C;
283 class NoEncode<string E> {
284 string DisableEncoding = E;
288 //===----------------------------------------------------------------------===//
289 // PowerPC Operand Definitions.
291 def s5imm : Operand<i32> {
292 let PrintMethod = "printS5ImmOperand";
294 def u5imm : Operand<i32> {
295 let PrintMethod = "printU5ImmOperand";
297 def u6imm : Operand<i32> {
298 let PrintMethod = "printU6ImmOperand";
300 def s16imm : Operand<i32> {
301 let PrintMethod = "printS16ImmOperand";
303 def u16imm : Operand<i32> {
304 let PrintMethod = "printU16ImmOperand";
306 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
307 let PrintMethod = "printS16X4ImmOperand";
309 def directbrtarget : Operand<OtherVT> {
310 let PrintMethod = "printBranchOperand";
311 let EncoderMethod = "getDirectBrEncoding";
313 def condbrtarget : Operand<OtherVT> {
314 let PrintMethod = "printBranchOperand";
315 let EncoderMethod = "getCondBrEncoding";
317 def calltarget : Operand<iPTR> {
318 let EncoderMethod = "getDirectBrEncoding";
320 def aaddr : Operand<iPTR> {
321 let PrintMethod = "printAbsAddrOperand";
323 def symbolHi: Operand<i32> {
324 let PrintMethod = "printSymbolHi";
325 let EncoderMethod = "getHA16Encoding";
327 def symbolLo: Operand<i32> {
328 let PrintMethod = "printSymbolLo";
329 let EncoderMethod = "getLO16Encoding";
331 def crbitm: Operand<i8> {
332 let PrintMethod = "printcrbitm";
333 let EncoderMethod = "get_crbitm_encoding";
336 def memri : Operand<iPTR> {
337 let PrintMethod = "printMemRegImm";
338 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
339 let EncoderMethod = "getMemRIEncoding";
341 def memrr : Operand<iPTR> {
342 let PrintMethod = "printMemRegReg";
343 let MIOperandInfo = (ops ptr_rc:$offreg, ptr_rc:$ptrreg);
345 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
346 let PrintMethod = "printMemRegImmShifted";
347 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
348 let EncoderMethod = "getMemRIXEncoding";
351 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
352 // that doesn't matter.
353 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
354 (ops (i32 20), (i32 zero_reg))> {
355 let PrintMethod = "printPredicateOperand";
358 // Define PowerPC specific addressing mode.
359 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
360 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
361 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
362 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
364 /// This is just the offset part of iaddr, used for preinc.
365 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
366 def xaddroff : ComplexPattern<iPTR, 1, "SelectAddrIdxOffs", [], []>;
368 //===----------------------------------------------------------------------===//
369 // PowerPC Instruction Predicate Definitions.
370 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
371 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
372 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
374 //===----------------------------------------------------------------------===//
375 // PowerPC Instruction Definitions.
377 // Pseudo-instructions:
379 let hasCtrlDep = 1 in {
380 let Defs = [R1], Uses = [R1] in {
381 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
382 [(callseq_start timm:$amt)]>;
383 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
384 [(callseq_end timm:$amt1, timm:$amt2)]>;
387 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
388 "UPDATE_VRSAVE $rD, $rS", []>;
391 let Defs = [R1], Uses = [R1] in
392 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "#DYNALLOC",
394 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
396 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
397 // instruction selection into a branch sequence.
398 let usesCustomInserter = 1, // Expanded after instruction selection.
399 PPC970_Single = 1 in {
400 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
401 i32imm:$BROPC), "#SELECT_CC_I4",
403 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
404 i32imm:$BROPC), "#SELECT_CC_I8",
406 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
407 i32imm:$BROPC), "#SELECT_CC_F4",
409 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
410 i32imm:$BROPC), "#SELECT_CC_F8",
412 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
413 i32imm:$BROPC), "#SELECT_CC_VRRC",
417 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
418 // scavenge a register for it.
420 def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F),
423 // RESTORE_CR - Indicate that we're restoring the CR register (previously
424 // spilled), so we'll need to scavenge a register for it.
426 def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F),
429 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
430 let isCodeGenOnly = 1, isReturn = 1, Uses = [LR, RM] in
431 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
432 "b${p:cc}lr ${p:reg}", BrB,
434 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
435 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
439 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
442 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
443 let isBarrier = 1 in {
444 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
449 // BCC represents an arbitrary conditional branch on a predicate.
450 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
451 // a two-value operand where a dag node expects two operands. :(
452 let isCodeGenOnly = 1 in
453 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
454 "b${cond:cc} ${cond:reg}, $dst"
455 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
457 let Defs = [CTR], Uses = [CTR] in {
458 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
460 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
466 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
467 // Convenient aliases for call instructions
469 def BL_Darwin : IForm<18, 0, 1,
470 (outs), (ins calltarget:$func),
471 "bl $func", BrB, []>; // See Pat patterns below.
472 def BLA_Darwin : IForm<18, 1, 1,
473 (outs), (ins aaddr:$func),
474 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>;
476 let Uses = [CTR, RM] in {
477 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
480 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>;
485 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
486 // Convenient aliases for call instructions
488 def BL_SVR4 : IForm<18, 0, 1,
489 (outs), (ins calltarget:$func),
490 "bl $func", BrB, []>; // See Pat patterns below.
491 def BLA_SVR4 : IForm<18, 1, 1,
492 (outs), (ins aaddr:$func),
494 [(PPCcall_SVR4 (i32 imm:$func))]>;
496 let Uses = [CTR, RM] in {
497 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1,
500 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>;
505 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
506 def TCRETURNdi :Pseudo< (outs),
507 (ins calltarget:$dst, i32imm:$offset),
508 "#TC_RETURNd $dst $offset",
512 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
513 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
514 "#TC_RETURNa $func $offset",
515 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
517 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
518 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
519 "#TC_RETURNr $dst $offset",
523 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
524 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
525 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
526 Requires<[In32BitMode]>;
530 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
531 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
532 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
537 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
538 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
539 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
544 // DCB* instructions.
545 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
546 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
547 PPC970_DGroup_Single;
548 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
549 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
550 PPC970_DGroup_Single;
551 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
552 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
553 PPC970_DGroup_Single;
554 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
555 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
556 PPC970_DGroup_Single;
557 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
558 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
559 PPC970_DGroup_Single;
560 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
561 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
562 PPC970_DGroup_Single;
563 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
564 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
565 PPC970_DGroup_Single;
566 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
567 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
568 PPC970_DGroup_Single;
570 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
574 let usesCustomInserter = 1 in {
575 let Defs = [CR0] in {
576 def ATOMIC_LOAD_ADD_I8 : Pseudo<
577 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I8",
578 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>;
579 def ATOMIC_LOAD_SUB_I8 : Pseudo<
580 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I8",
581 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>;
582 def ATOMIC_LOAD_AND_I8 : Pseudo<
583 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I8",
584 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>;
585 def ATOMIC_LOAD_OR_I8 : Pseudo<
586 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I8",
587 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>;
588 def ATOMIC_LOAD_XOR_I8 : Pseudo<
589 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "ATOMIC_LOAD_XOR_I8",
590 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>;
591 def ATOMIC_LOAD_NAND_I8 : Pseudo<
592 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I8",
593 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>;
594 def ATOMIC_LOAD_ADD_I16 : Pseudo<
595 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I16",
596 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>;
597 def ATOMIC_LOAD_SUB_I16 : Pseudo<
598 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I16",
599 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>;
600 def ATOMIC_LOAD_AND_I16 : Pseudo<
601 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I16",
602 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>;
603 def ATOMIC_LOAD_OR_I16 : Pseudo<
604 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I16",
605 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>;
606 def ATOMIC_LOAD_XOR_I16 : Pseudo<
607 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I16",
608 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>;
609 def ATOMIC_LOAD_NAND_I16 : Pseudo<
610 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I16",
611 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>;
612 def ATOMIC_LOAD_ADD_I32 : Pseudo<
613 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I32",
614 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
615 def ATOMIC_LOAD_SUB_I32 : Pseudo<
616 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I32",
617 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>;
618 def ATOMIC_LOAD_AND_I32 : Pseudo<
619 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I32",
620 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>;
621 def ATOMIC_LOAD_OR_I32 : Pseudo<
622 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I32",
623 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>;
624 def ATOMIC_LOAD_XOR_I32 : Pseudo<
625 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I32",
626 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>;
627 def ATOMIC_LOAD_NAND_I32 : Pseudo<
628 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I32",
629 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>;
631 def ATOMIC_CMP_SWAP_I8 : Pseudo<
632 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I8",
634 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
635 def ATOMIC_CMP_SWAP_I16 : Pseudo<
636 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
638 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
639 def ATOMIC_CMP_SWAP_I32 : Pseudo<
640 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
642 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
644 def ATOMIC_SWAP_I8 : Pseudo<
645 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_i8",
646 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>;
647 def ATOMIC_SWAP_I16 : Pseudo<
648 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I16",
649 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>;
650 def ATOMIC_SWAP_I32 : Pseudo<
651 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I32",
652 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>;
656 // Instructions to support atomic operations
657 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
658 "lwarx $rD, $src", LdStLWARX,
659 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>;
662 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
663 "stwcx. $rS, $dst", LdStSTWCX,
664 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>,
667 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
668 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
670 //===----------------------------------------------------------------------===//
671 // PPC32 Load Instructions.
674 // Unindexed (r+i) Loads.
675 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
676 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
677 "lbz $rD, $src", LdStLoad,
678 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
679 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
680 "lha $rD, $src", LdStLHA,
681 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
682 PPC970_DGroup_Cracked;
683 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
684 "lhz $rD, $src", LdStLoad,
685 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
686 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
687 "lwz $rD, $src", LdStLoad,
688 [(set GPRC:$rD, (load iaddr:$src))]>;
690 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
691 "lfs $rD, $src", LdStLFD,
692 [(set F4RC:$rD, (load iaddr:$src))]>;
693 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
694 "lfd $rD, $src", LdStLFD,
695 [(set F8RC:$rD, (load iaddr:$src))]>;
698 // Unindexed (r+i) Loads with Update (preinc).
700 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
701 "lbzu $rD, $addr", LdStLoadUpd,
702 []>, RegConstraint<"$addr.reg = $ea_result">,
703 NoEncode<"$ea_result">;
705 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
706 "lhau $rD, $addr", LdStLHAU,
707 []>, RegConstraint<"$addr.reg = $ea_result">,
708 NoEncode<"$ea_result">;
710 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
711 "lhzu $rD, $addr", LdStLoadUpd,
712 []>, RegConstraint<"$addr.reg = $ea_result">,
713 NoEncode<"$ea_result">;
715 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
716 "lwzu $rD, $addr", LdStLoadUpd,
717 []>, RegConstraint<"$addr.reg = $ea_result">,
718 NoEncode<"$ea_result">;
720 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
721 "lfsu $rD, $addr", LdStLFDU,
722 []>, RegConstraint<"$addr.reg = $ea_result">,
723 NoEncode<"$ea_result">;
725 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
726 "lfdu $rD, $addr", LdStLFDU,
727 []>, RegConstraint<"$addr.reg = $ea_result">,
728 NoEncode<"$ea_result">;
731 // Indexed (r+r) Loads with Update (preinc).
732 def LBZUX : XForm_1<31, 119, (outs GPRC:$rD, ptr_rc:$ea_result),
734 "lbzux $rD, $addr", LdStLoadUpd,
735 []>, RegConstraint<"$addr.offreg = $ea_result">,
736 NoEncode<"$ea_result">;
738 def LHAUX : XForm_1<31, 375, (outs GPRC:$rD, ptr_rc:$ea_result),
740 "lhaux $rD, $addr", LdStLHAU,
741 []>, RegConstraint<"$addr.offreg = $ea_result">,
742 NoEncode<"$ea_result">;
744 def LHZUX : XForm_1<31, 311, (outs GPRC:$rD, ptr_rc:$ea_result),
746 "lhzux $rD, $addr", LdStLoadUpd,
747 []>, RegConstraint<"$addr.offreg = $ea_result">,
748 NoEncode<"$ea_result">;
750 def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc:$ea_result),
752 "lwzux $rD, $addr", LdStLoadUpd,
753 []>, RegConstraint<"$addr.offreg = $ea_result">,
754 NoEncode<"$ea_result">;
756 def LFSUX : XForm_1<31, 567, (outs F4RC:$rD, ptr_rc:$ea_result),
758 "lfsux $rD, $addr", LdStLFDU,
759 []>, RegConstraint<"$addr.offreg = $ea_result">,
760 NoEncode<"$ea_result">;
762 def LFDUX : XForm_1<31, 631, (outs F8RC:$rD, ptr_rc:$ea_result),
764 "lfdux $rD, $addr", LdStLFDU,
765 []>, RegConstraint<"$addr.offreg = $ea_result">,
766 NoEncode<"$ea_result">;
770 // Indexed (r+r) Loads.
772 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
773 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
774 "lbzx $rD, $src", LdStLoad,
775 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
776 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
777 "lhax $rD, $src", LdStLHA,
778 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
779 PPC970_DGroup_Cracked;
780 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
781 "lhzx $rD, $src", LdStLoad,
782 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
783 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
784 "lwzx $rD, $src", LdStLoad,
785 [(set GPRC:$rD, (load xaddr:$src))]>;
788 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
789 "lhbrx $rD, $src", LdStLoad,
790 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>;
791 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
792 "lwbrx $rD, $src", LdStLoad,
793 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>;
795 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
796 "lfsx $frD, $src", LdStLFD,
797 [(set F4RC:$frD, (load xaddr:$src))]>;
798 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
799 "lfdx $frD, $src", LdStLFD,
800 [(set F8RC:$frD, (load xaddr:$src))]>;
803 //===----------------------------------------------------------------------===//
804 // PPC32 Store Instructions.
807 // Unindexed (r+i) Stores.
808 let PPC970_Unit = 2 in {
809 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
810 "stb $rS, $src", LdStStore,
811 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
812 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
813 "sth $rS, $src", LdStStore,
814 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
815 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
816 "stw $rS, $src", LdStStore,
817 [(store GPRC:$rS, iaddr:$src)]>;
818 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
819 "stfs $rS, $dst", LdStSTFD,
820 [(store F4RC:$rS, iaddr:$dst)]>;
821 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
822 "stfd $rS, $dst", LdStSTFD,
823 [(store F8RC:$rS, iaddr:$dst)]>;
826 // Unindexed (r+i) Stores with Update (preinc).
827 let PPC970_Unit = 2 in {
828 def STBU : DForm_1a<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
829 symbolLo:$ptroff, ptr_rc:$ptrreg),
830 "stbu $rS, $ptroff($ptrreg)", LdStStoreUpd,
831 [(set ptr_rc:$ea_res,
832 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
833 iaddroff:$ptroff))]>,
834 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
835 def STHU : DForm_1a<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
836 symbolLo:$ptroff, ptr_rc:$ptrreg),
837 "sthu $rS, $ptroff($ptrreg)", LdStStoreUpd,
838 [(set ptr_rc:$ea_res,
839 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
840 iaddroff:$ptroff))]>,
841 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
842 def STWU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
843 symbolLo:$ptroff, ptr_rc:$ptrreg),
844 "stwu $rS, $ptroff($ptrreg)", LdStStoreUpd,
845 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
846 iaddroff:$ptroff))]>,
847 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
848 def STFSU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
849 symbolLo:$ptroff, ptr_rc:$ptrreg),
850 "stfsu $rS, $ptroff($ptrreg)", LdStSTFDU,
851 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
852 iaddroff:$ptroff))]>,
853 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
854 def STFDU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
855 symbolLo:$ptroff, ptr_rc:$ptrreg),
856 "stfdu $rS, $ptroff($ptrreg)", LdStSTFDU,
857 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
858 iaddroff:$ptroff))]>,
859 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
863 // Indexed (r+r) Stores.
865 let PPC970_Unit = 2 in {
866 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
867 "stbx $rS, $dst", LdStStore,
868 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
869 PPC970_DGroup_Cracked;
870 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
871 "sthx $rS, $dst", LdStStore,
872 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
873 PPC970_DGroup_Cracked;
874 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
875 "stwx $rS, $dst", LdStStore,
876 [(store GPRC:$rS, xaddr:$dst)]>,
877 PPC970_DGroup_Cracked;
879 def STBUX : XForm_8<31, 247, (outs ptr_rc:$ea_res),
880 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
881 "stbux $rS, $ptroff, $ptrreg", LdStStoreUpd,
882 [(set ptr_rc:$ea_res,
883 (pre_truncsti8 GPRC:$rS,
884 ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
885 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
886 PPC970_DGroup_Cracked;
888 def STHUX : XForm_8<31, 439, (outs ptr_rc:$ea_res),
889 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
890 "sthux $rS, $ptroff, $ptrreg", LdStStoreUpd,
891 [(set ptr_rc:$ea_res,
892 (pre_truncsti16 GPRC:$rS,
893 ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
894 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
895 PPC970_DGroup_Cracked;
897 def STWUX : XForm_8<31, 183, (outs ptr_rc:$ea_res),
898 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
899 "stwux $rS, $ptroff, $ptrreg", LdStStoreUpd,
900 [(set ptr_rc:$ea_res,
901 (pre_store GPRC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
902 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
903 PPC970_DGroup_Cracked;
905 def STFSUX : XForm_8<31, 695, (outs ptr_rc:$ea_res),
906 (ins F4RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
907 "stfsux $rS, $ptroff, $ptrreg", LdStSTFDU,
908 [(set ptr_rc:$ea_res,
909 (pre_store F4RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
910 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
911 PPC970_DGroup_Cracked;
913 def STFDUX : XForm_8<31, 759, (outs ptr_rc:$ea_res),
914 (ins F8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
915 "stfdux $rS, $ptroff, $ptrreg", LdStSTFDU,
916 [(set ptr_rc:$ea_res,
917 (pre_store F8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
918 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
919 PPC970_DGroup_Cracked;
921 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
922 "sthbrx $rS, $dst", LdStStore,
923 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>,
924 PPC970_DGroup_Cracked;
925 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
926 "stwbrx $rS, $dst", LdStStore,
927 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>,
928 PPC970_DGroup_Cracked;
930 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
931 "stfiwx $frS, $dst", LdStSTFD,
932 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
934 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
935 "stfsx $frS, $dst", LdStSTFD,
936 [(store F4RC:$frS, xaddr:$dst)]>;
937 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
938 "stfdx $frS, $dst", LdStSTFD,
939 [(store F8RC:$frS, xaddr:$dst)]>;
942 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
946 //===----------------------------------------------------------------------===//
947 // PPC32 Arithmetic Instructions.
950 let PPC970_Unit = 1 in { // FXU Operations.
951 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
952 "addi $rD, $rA, $imm", IntSimple,
953 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
954 def ADDIL : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$imm),
955 "addi $rD, $rA, $imm", IntSimple,
956 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
957 let Defs = [CARRY] in {
958 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
959 "addic $rD, $rA, $imm", IntGeneral,
960 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
961 PPC970_DGroup_Cracked;
962 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
963 "addic. $rD, $rA, $imm", IntGeneral,
966 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
967 "addis $rD, $rA, $imm", IntSimple,
968 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
969 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
970 "la $rD, $sym($rA)", IntGeneral,
971 [(set GPRC:$rD, (add GPRC:$rA,
972 (PPClo tglobaladdr:$sym, 0)))]>;
973 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
974 "mulli $rD, $rA, $imm", IntMulLI,
975 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
976 let Defs = [CARRY] in {
977 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
978 "subfic $rD, $rA, $imm", IntGeneral,
979 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
982 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
983 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
984 "li $rD, $imm", IntSimple,
985 [(set GPRC:$rD, immSExt16:$imm)]>;
986 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
987 "lis $rD, $imm", IntSimple,
988 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
992 let PPC970_Unit = 1 in { // FXU Operations.
993 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
994 "andi. $dst, $src1, $src2", IntGeneral,
995 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
997 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
998 "andis. $dst, $src1, $src2", IntGeneral,
999 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
1001 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1002 "ori $dst, $src1, $src2", IntSimple,
1003 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
1004 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1005 "oris $dst, $src1, $src2", IntSimple,
1006 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
1007 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1008 "xori $dst, $src1, $src2", IntSimple,
1009 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
1010 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1011 "xoris $dst, $src1, $src2", IntSimple,
1012 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
1013 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
1015 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
1016 "cmpwi $crD, $rA, $imm", IntCompare>;
1017 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1018 "cmplwi $dst, $src1, $src2", IntCompare>;
1022 let PPC970_Unit = 1 in { // FXU Operations.
1023 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1024 "nand $rA, $rS, $rB", IntSimple,
1025 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
1026 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1027 "and $rA, $rS, $rB", IntSimple,
1028 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
1029 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1030 "andc $rA, $rS, $rB", IntSimple,
1031 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
1032 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1033 "or $rA, $rS, $rB", IntSimple,
1034 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
1035 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1036 "nor $rA, $rS, $rB", IntSimple,
1037 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
1038 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1039 "orc $rA, $rS, $rB", IntSimple,
1040 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
1041 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1042 "eqv $rA, $rS, $rB", IntSimple,
1043 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
1044 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1045 "xor $rA, $rS, $rB", IntSimple,
1046 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
1047 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1048 "slw $rA, $rS, $rB", IntGeneral,
1049 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
1050 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1051 "srw $rA, $rS, $rB", IntGeneral,
1052 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
1053 let Defs = [CARRY] in {
1054 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1055 "sraw $rA, $rS, $rB", IntShift,
1056 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
1060 let PPC970_Unit = 1 in { // FXU Operations.
1061 let Defs = [CARRY] in {
1062 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
1063 "srawi $rA, $rS, $SH", IntShift,
1064 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
1066 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
1067 "cntlzw $rA, $rS", IntGeneral,
1068 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
1069 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
1070 "extsb $rA, $rS", IntSimple,
1071 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
1072 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
1073 "extsh $rA, $rS", IntSimple,
1074 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
1076 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1077 "cmpw $crD, $rA, $rB", IntCompare>;
1078 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1079 "cmplw $crD, $rA, $rB", IntCompare>;
1081 let PPC970_Unit = 3 in { // FPU Operations.
1082 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1083 // "fcmpo $crD, $fA, $fB", FPCompare>;
1084 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
1085 "fcmpu $crD, $fA, $fB", FPCompare>;
1086 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
1087 "fcmpu $crD, $fA, $fB", FPCompare>;
1089 let Uses = [RM] in {
1090 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
1091 "fctiwz $frD, $frB", FPGeneral,
1092 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
1093 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
1094 "frsp $frD, $frB", FPGeneral,
1095 [(set F4RC:$frD, (fround F8RC:$frB))]>;
1096 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
1097 "fsqrt $frD, $frB", FPSqrt,
1098 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
1099 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
1100 "fsqrts $frD, $frB", FPSqrt,
1101 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
1105 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1106 /// often coalesced away and we don't want the dispatch group builder to think
1107 /// that they will fill slots (which could cause the load of a LSU reject to
1108 /// sneak into a d-group with a store).
1109 def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1110 "fmr $frD, $frB", FPGeneral,
1111 []>, // (set F4RC:$frD, F4RC:$frB)
1114 let PPC970_Unit = 3 in { // FPU Operations.
1115 // These are artificially split into two different forms, for 4/8 byte FP.
1116 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1117 "fabs $frD, $frB", FPGeneral,
1118 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
1119 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1120 "fabs $frD, $frB", FPGeneral,
1121 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
1122 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1123 "fnabs $frD, $frB", FPGeneral,
1124 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
1125 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1126 "fnabs $frD, $frB", FPGeneral,
1127 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
1128 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1129 "fneg $frD, $frB", FPGeneral,
1130 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
1131 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1132 "fneg $frD, $frB", FPGeneral,
1133 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
1137 // XL-Form instructions. condition register logical ops.
1139 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1140 "mcrf $BF, $BFA", BrMCR>,
1141 PPC970_DGroup_First, PPC970_Unit_CRU;
1143 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1144 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1145 "creqv $CRD, $CRA, $CRB", BrCR,
1148 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1149 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1150 "cror $CRD, $CRA, $CRB", BrCR,
1153 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1154 "creqv $dst, $dst, $dst", BrCR,
1157 def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins),
1158 "crxor $dst, $dst, $dst", BrCR,
1161 let Defs = [CR1EQ], CRD = 6 in {
1162 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1163 "creqv 6, 6, 6", BrCR,
1166 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1167 "crxor 6, 6, 6", BrCR,
1171 // XFX-Form instructions. Instructions that deal with SPRs.
1173 let Uses = [CTR] in {
1174 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1175 "mfctr $rT", SprMFSPR>,
1176 PPC970_DGroup_First, PPC970_Unit_FXU;
1178 let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in {
1179 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1180 "mtctr $rS", SprMTSPR>,
1181 PPC970_DGroup_First, PPC970_Unit_FXU;
1184 let Defs = [LR] in {
1185 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1186 "mtlr $rS", SprMTSPR>,
1187 PPC970_DGroup_First, PPC970_Unit_FXU;
1189 let Uses = [LR] in {
1190 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1191 "mflr $rT", SprMFSPR>,
1192 PPC970_DGroup_First, PPC970_Unit_FXU;
1195 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1196 // a GPR on the PPC970. As such, copies in and out have the same performance
1197 // characteristics as an OR instruction.
1198 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1199 "mtspr 256, $rS", IntGeneral>,
1200 PPC970_DGroup_Single, PPC970_Unit_FXU;
1201 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1202 "mfspr $rT, 256", IntGeneral>,
1203 PPC970_DGroup_First, PPC970_Unit_FXU;
1205 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS),
1206 "mtcrf $FXM, $rS", BrMCRX>,
1207 PPC970_MicroCode, PPC970_Unit_CRU;
1209 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1210 // declaring that here gives the local register allocator problems with this:
1212 // MFCR <kill of whatever preg got assigned to vreg>
1213 // while not declaring it breaks DeadMachineInstructionElimination.
1214 // As it turns out, in all cases where we currently use this,
1215 // we're only interested in one subregister of it. Represent this in the
1216 // instruction to keep the register allocator from becoming confused.
1218 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1219 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1220 "#MFCRpseud", SprMFCR>,
1221 PPC970_MicroCode, PPC970_Unit_CRU;
1223 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
1224 "mfcr $rT", SprMFCR>,
1225 PPC970_MicroCode, PPC970_Unit_CRU;
1227 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1228 "mfocrf $rT, $FXM", SprMFCR>,
1229 PPC970_DGroup_First, PPC970_Unit_CRU;
1231 // Instructions to manipulate FPSCR. Only long double handling uses these.
1232 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1234 let Uses = [RM], Defs = [RM] in {
1235 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1236 "mtfsb0 $FM", IntMTFSB0,
1237 [(PPCmtfsb0 (i32 imm:$FM))]>,
1238 PPC970_DGroup_Single, PPC970_Unit_FPU;
1239 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1240 "mtfsb1 $FM", IntMTFSB0,
1241 [(PPCmtfsb1 (i32 imm:$FM))]>,
1242 PPC970_DGroup_Single, PPC970_Unit_FPU;
1243 // MTFSF does not actually produce an FP result. We pretend it copies
1244 // input reg B to the output. If we didn't do this it would look like the
1245 // instruction had no outputs (because we aren't modelling the FPSCR) and
1246 // it would be deleted.
1247 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
1248 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
1249 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
1250 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
1251 F8RC:$rT, F8RC:$FRB))]>,
1252 PPC970_DGroup_Single, PPC970_Unit_FPU;
1254 let Uses = [RM] in {
1255 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1256 "mffs $rT", IntMFFS,
1257 [(set F8RC:$rT, (PPCmffs))]>,
1258 PPC970_DGroup_Single, PPC970_Unit_FPU;
1259 def FADDrtz: AForm_2<63, 21,
1260 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1261 "fadd $FRT, $FRA, $FRB", FPAddSub,
1262 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
1263 PPC970_DGroup_Single, PPC970_Unit_FPU;
1267 let PPC970_Unit = 1 in { // FXU Operations.
1269 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1271 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1272 "add $rT, $rA, $rB", IntSimple,
1273 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
1274 let Defs = [CARRY] in {
1275 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1276 "addc $rT, $rA, $rB", IntGeneral,
1277 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
1278 PPC970_DGroup_Cracked;
1280 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1281 "divw $rT, $rA, $rB", IntDivW,
1282 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
1283 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1284 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1285 "divwu $rT, $rA, $rB", IntDivW,
1286 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
1287 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1288 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1289 "mulhw $rT, $rA, $rB", IntMulHW,
1290 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
1291 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1292 "mulhwu $rT, $rA, $rB", IntMulHWU,
1293 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
1294 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1295 "mullw $rT, $rA, $rB", IntMulHW,
1296 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
1297 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1298 "subf $rT, $rA, $rB", IntGeneral,
1299 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
1300 let Defs = [CARRY] in {
1301 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1302 "subfc $rT, $rA, $rB", IntGeneral,
1303 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
1304 PPC970_DGroup_Cracked;
1306 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1307 "neg $rT, $rA", IntSimple,
1308 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
1309 let Uses = [CARRY], Defs = [CARRY] in {
1310 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1311 "adde $rT, $rA, $rB", IntGeneral,
1312 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
1313 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1314 "addme $rT, $rA", IntGeneral,
1315 [(set GPRC:$rT, (adde GPRC:$rA, -1))]>;
1316 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1317 "addze $rT, $rA", IntGeneral,
1318 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
1319 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1320 "subfe $rT, $rA, $rB", IntGeneral,
1321 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
1322 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1323 "subfme $rT, $rA", IntGeneral,
1324 [(set GPRC:$rT, (sube -1, GPRC:$rA))]>;
1325 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1326 "subfze $rT, $rA", IntGeneral,
1327 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
1331 // A-Form instructions. Most of the instructions executed in the FPU are of
1334 let PPC970_Unit = 3 in { // FPU Operations.
1335 let Uses = [RM] in {
1336 def FMADD : AForm_1<63, 29,
1337 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1338 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1340 (fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB))]>;
1341 def FMADDS : AForm_1<59, 29,
1342 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1343 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1345 (fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB))]>;
1346 def FMSUB : AForm_1<63, 28,
1347 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1348 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1350 (fma F8RC:$FRA, F8RC:$FRC, (fneg F8RC:$FRB)))]>;
1351 def FMSUBS : AForm_1<59, 28,
1352 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1353 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1355 (fma F4RC:$FRA, F4RC:$FRC, (fneg F4RC:$FRB)))]>;
1356 def FNMADD : AForm_1<63, 31,
1357 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1358 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1360 (fneg (fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB)))]>;
1361 def FNMADDS : AForm_1<59, 31,
1362 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1363 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1365 (fneg (fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB)))]>;
1366 def FNMSUB : AForm_1<63, 30,
1367 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1368 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1369 [(set F8RC:$FRT, (fneg (fma F8RC:$FRA, F8RC:$FRC,
1370 (fneg F8RC:$FRB))))]>;
1371 def FNMSUBS : AForm_1<59, 30,
1372 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1373 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1374 [(set F4RC:$FRT, (fneg (fma F4RC:$FRA, F4RC:$FRC,
1375 (fneg F4RC:$FRB))))]>;
1377 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1378 // having 4 of these, force the comparison to always be an 8-byte double (code
1379 // should use an FMRSD if the input comparison value really wants to be a float)
1380 // and 4/8 byte forms for the result and operand type..
1381 def FSELD : AForm_1<63, 23,
1382 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1383 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1384 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1385 def FSELS : AForm_1<63, 23,
1386 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1387 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1388 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1389 let Uses = [RM] in {
1390 def FADD : AForm_2<63, 21,
1391 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1392 "fadd $FRT, $FRA, $FRB", FPAddSub,
1393 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1394 def FADDS : AForm_2<59, 21,
1395 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1396 "fadds $FRT, $FRA, $FRB", FPGeneral,
1397 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1398 def FDIV : AForm_2<63, 18,
1399 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1400 "fdiv $FRT, $FRA, $FRB", FPDivD,
1401 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1402 def FDIVS : AForm_2<59, 18,
1403 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1404 "fdivs $FRT, $FRA, $FRB", FPDivS,
1405 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1406 def FMUL : AForm_3<63, 25,
1407 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC),
1408 "fmul $FRT, $FRA, $FRC", FPFused,
1409 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRC))]>;
1410 def FMULS : AForm_3<59, 25,
1411 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC),
1412 "fmuls $FRT, $FRA, $FRC", FPGeneral,
1413 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRC))]>;
1414 def FSUB : AForm_2<63, 20,
1415 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1416 "fsub $FRT, $FRA, $FRB", FPAddSub,
1417 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1418 def FSUBS : AForm_2<59, 20,
1419 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1420 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1421 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1425 let PPC970_Unit = 1 in { // FXU Operations.
1426 def ISEL : AForm_4<31, 15,
1427 (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB, pred:$cond),
1428 "isel $rT, $rA, $rB, $cond", IntGeneral,
1432 let PPC970_Unit = 1 in { // FXU Operations.
1433 // M-Form instructions. rotate and mask instructions.
1435 let isCommutable = 1 in {
1436 // RLWIMI can be commuted if the rotate amount is zero.
1437 def RLWIMI : MForm_2<20,
1438 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1439 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1440 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1443 def RLWINM : MForm_2<21,
1444 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1445 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1447 def RLWINMo : MForm_2<21,
1448 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1449 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1450 []>, isDOT, PPC970_DGroup_Cracked;
1451 def RLWNM : MForm_2<23,
1452 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1453 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1458 //===----------------------------------------------------------------------===//
1459 // PowerPC Instruction Patterns
1462 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1463 def : Pat<(i32 imm:$imm),
1464 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1466 // Implement the 'not' operation with the NOR instruction.
1467 def NOT : Pat<(not GPRC:$in),
1468 (NOR GPRC:$in, GPRC:$in)>;
1470 // ADD an arbitrary immediate.
1471 def : Pat<(add GPRC:$in, imm:$imm),
1472 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1473 // OR an arbitrary immediate.
1474 def : Pat<(or GPRC:$in, imm:$imm),
1475 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1476 // XOR an arbitrary immediate.
1477 def : Pat<(xor GPRC:$in, imm:$imm),
1478 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1480 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1481 (SUBFIC GPRC:$in, imm:$imm)>;
1484 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1485 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1486 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1487 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1490 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1491 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1492 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1493 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1496 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1497 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1500 def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)),
1501 (BL_Darwin tglobaladdr:$dst)>;
1502 def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)),
1503 (BL_Darwin texternalsym:$dst)>;
1504 def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)),
1505 (BL_SVR4 tglobaladdr:$dst)>;
1506 def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)),
1507 (BL_SVR4 texternalsym:$dst)>;
1510 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1511 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1513 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1514 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1516 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1517 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1521 // Hi and Lo for Darwin Global Addresses.
1522 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1523 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1524 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1525 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1526 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1527 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1528 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
1529 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
1530 def : Pat<(PPChi tglobaltlsaddr:$g, GPRC:$in),
1531 (ADDIS GPRC:$in, tglobaltlsaddr:$g)>;
1532 def : Pat<(PPClo tglobaltlsaddr:$g, GPRC:$in),
1533 (ADDIL GPRC:$in, tglobaltlsaddr:$g)>;
1534 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1535 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1536 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1537 (ADDIS GPRC:$in, tconstpool:$g)>;
1538 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1539 (ADDIS GPRC:$in, tjumptable:$g)>;
1540 def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)),
1541 (ADDIS GPRC:$in, tblockaddress:$g)>;
1543 // Standard shifts. These are represented separately from the real shifts above
1544 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1546 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1547 (SRAW GPRC:$rS, GPRC:$rB)>;
1548 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1549 (SRW GPRC:$rS, GPRC:$rB)>;
1550 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1551 (SLW GPRC:$rS, GPRC:$rB)>;
1553 def : Pat<(zextloadi1 iaddr:$src),
1555 def : Pat<(zextloadi1 xaddr:$src),
1557 def : Pat<(extloadi1 iaddr:$src),
1559 def : Pat<(extloadi1 xaddr:$src),
1561 def : Pat<(extloadi8 iaddr:$src),
1563 def : Pat<(extloadi8 xaddr:$src),
1565 def : Pat<(extloadi16 iaddr:$src),
1567 def : Pat<(extloadi16 xaddr:$src),
1569 def : Pat<(f64 (extloadf32 iaddr:$src)),
1570 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1571 def : Pat<(f64 (extloadf32 xaddr:$src)),
1572 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1574 def : Pat<(f64 (fextend F4RC:$src)),
1575 (COPY_TO_REGCLASS F4RC:$src, F8RC)>;
1578 def : Pat<(membarrier (i32 imm /*ll*/),
1582 (i32 imm /*device*/)),
1585 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
1587 include "PPCInstrAltivec.td"
1588 include "PPCInstr64Bit.td"