1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 2, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPClarx : SDTypeProfile<1, 1, [
46 SDTCisInt<0>, SDTCisPtrTy<1>
48 def SDT_PPCstcx : SDTypeProfile<0, 2, [
49 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
53 SDTCisPtrTy<0>, SDTCisVT<1, i32>
56 def SDT_PPCnop : SDTypeProfile<0, 0, []>;
58 //===----------------------------------------------------------------------===//
59 // PowerPC specific DAG Nodes.
62 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
63 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
64 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
65 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
66 [SDNPHasChain, SDNPMayStore]>;
68 // This sequence is used for long double->int conversions. It changes the
69 // bits in the FPSCR which is not modelled.
70 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
72 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
73 [SDNPInGlue, SDNPOutGlue]>;
74 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
75 [SDNPInGlue, SDNPOutGlue]>;
76 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
77 [SDNPInGlue, SDNPOutGlue]>;
78 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
83 def PPCfsel : SDNode<"PPCISD::FSEL",
84 // Type constraint for fsel.
85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
88 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
89 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
90 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
91 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
92 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
94 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
96 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
97 // amounts. These nodes are generated by the multi-precision shift code.
98 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
99 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
100 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
102 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
103 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
104 [SDNPHasChain, SDNPMayStore]>;
106 // These are target-independent nodes, but have target-specific formats.
107 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
108 [SDNPHasChain, SDNPOutGlue]>;
109 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
112 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
113 def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall,
114 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
116 def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall,
117 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInGlue, SDNPOutGlue]>;
120 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
121 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
122 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
123 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
124 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
125 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
126 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
127 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
128 def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone,
129 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
132 def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone,
133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
136 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
137 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
139 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
140 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
143 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
145 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
146 [SDNPHasChain, SDNPOptInGlue]>;
148 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
149 [SDNPHasChain, SDNPMayLoad]>;
150 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
151 [SDNPHasChain, SDNPMayStore]>;
153 // Instructions to support atomic operations
154 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
155 [SDNPHasChain, SDNPMayLoad]>;
156 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
157 [SDNPHasChain, SDNPMayStore]>;
159 // Instructions to support dynamic alloca.
160 def SDTDynOp : SDTypeProfile<1, 2, []>;
161 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
163 //===----------------------------------------------------------------------===//
164 // PowerPC specific transformation functions and pattern fragments.
167 def SHL32 : SDNodeXForm<imm, [{
168 // Transformation function: 31 - imm
169 return getI32Imm(31 - N->getZExtValue());
172 def SRL32 : SDNodeXForm<imm, [{
173 // Transformation function: 32 - imm
174 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
177 def LO16 : SDNodeXForm<imm, [{
178 // Transformation function: get the low 16 bits.
179 return getI32Imm((unsigned short)N->getZExtValue());
182 def HI16 : SDNodeXForm<imm, [{
183 // Transformation function: shift the immediate value down into the low bits.
184 return getI32Imm((unsigned)N->getZExtValue() >> 16);
187 def HA16 : SDNodeXForm<imm, [{
188 // Transformation function: shift the immediate value down into the low bits.
189 signed int Val = N->getZExtValue();
190 return getI32Imm((Val - (signed short)Val) >> 16);
192 def MB : SDNodeXForm<imm, [{
193 // Transformation function: get the start bit of a mask
195 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
196 return getI32Imm(mb);
199 def ME : SDNodeXForm<imm, [{
200 // Transformation function: get the end bit of a mask
202 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
203 return getI32Imm(me);
205 def maskimm32 : PatLeaf<(imm), [{
206 // maskImm predicate - True if immediate is a run of ones.
208 if (N->getValueType(0) == MVT::i32)
209 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
214 def immSExt16 : PatLeaf<(imm), [{
215 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
216 // field. Used by instructions like 'addi'.
217 if (N->getValueType(0) == MVT::i32)
218 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
220 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
222 def immZExt16 : PatLeaf<(imm), [{
223 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
224 // field. Used by instructions like 'ori'.
225 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
228 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
229 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
230 // identical in 32-bit mode, but in 64-bit mode, they return true if the
231 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
233 def imm16ShiftedZExt : PatLeaf<(imm), [{
234 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
235 // immediate are set. Used by instructions like 'xoris'.
236 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
239 def imm16ShiftedSExt : PatLeaf<(imm), [{
240 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
241 // immediate are set. Used by instructions like 'addis'. Identical to
242 // imm16ShiftedZExt in 32-bit mode.
243 if (N->getZExtValue() & 0xFFFF) return false;
244 if (N->getValueType(0) == MVT::i32)
246 // For 64-bit, make sure it is sext right.
247 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
251 //===----------------------------------------------------------------------===//
252 // PowerPC Flag Definitions.
254 class isPPC64 { bit PPC64 = 1; }
256 list<Register> Defs = [CR0];
260 class RegConstraint<string C> {
261 string Constraints = C;
263 class NoEncode<string E> {
264 string DisableEncoding = E;
268 //===----------------------------------------------------------------------===//
269 // PowerPC Operand Definitions.
271 def s5imm : Operand<i32> {
272 let PrintMethod = "printS5ImmOperand";
274 def u5imm : Operand<i32> {
275 let PrintMethod = "printU5ImmOperand";
277 def u6imm : Operand<i32> {
278 let PrintMethod = "printU6ImmOperand";
280 def s16imm : Operand<i32> {
281 let PrintMethod = "printS16ImmOperand";
283 def u16imm : Operand<i32> {
284 let PrintMethod = "printU16ImmOperand";
286 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
287 let PrintMethod = "printS16X4ImmOperand";
289 def directbrtarget : Operand<OtherVT> {
290 let PrintMethod = "printBranchOperand";
291 let EncoderMethod = "getDirectBrEncoding";
293 def condbrtarget : Operand<OtherVT> {
294 let PrintMethod = "printBranchOperand";
295 let EncoderMethod = "getCondBrEncoding";
297 def calltarget : Operand<iPTR> {
298 let EncoderMethod = "getDirectBrEncoding";
300 def aaddr : Operand<iPTR> {
301 let PrintMethod = "printAbsAddrOperand";
303 def symbolHi: Operand<i32> {
304 let PrintMethod = "printSymbolHi";
305 let EncoderMethod = "getHA16Encoding";
307 def symbolLo: Operand<i32> {
308 let PrintMethod = "printSymbolLo";
309 let EncoderMethod = "getLO16Encoding";
311 def crbitm: Operand<i8> {
312 let PrintMethod = "printcrbitm";
313 let EncoderMethod = "get_crbitm_encoding";
316 def memri : Operand<iPTR> {
317 let PrintMethod = "printMemRegImm";
318 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
319 let EncoderMethod = "getMemRIEncoding";
321 def memrr : Operand<iPTR> {
322 let PrintMethod = "printMemRegReg";
323 let MIOperandInfo = (ops ptr_rc, ptr_rc);
325 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
326 let PrintMethod = "printMemRegImmShifted";
327 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
328 let EncoderMethod = "getMemRIXEncoding";
330 def tocentry : Operand<iPTR> {
331 let MIOperandInfo = (ops i32imm:$imm);
334 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
335 // that doesn't matter.
336 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
337 (ops (i32 20), (i32 zero_reg))> {
338 let PrintMethod = "printPredicateOperand";
341 // Define PowerPC specific addressing mode.
342 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
343 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
344 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
345 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
347 /// This is just the offset part of iaddr, used for preinc.
348 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
350 //===----------------------------------------------------------------------===//
351 // PowerPC Instruction Predicate Definitions.
352 def FPContractions : Predicate<"!TM.Options.NoExcessFPPrecision">;
353 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
354 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
355 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
357 //===----------------------------------------------------------------------===//
358 // PowerPC Instruction Definitions.
360 // Pseudo-instructions:
362 let hasCtrlDep = 1 in {
363 let Defs = [R1], Uses = [R1] in {
364 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "",
365 [(callseq_start timm:$amt)]>;
366 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "",
367 [(callseq_end timm:$amt1, timm:$amt2)]>;
370 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
371 "UPDATE_VRSAVE $rD, $rS", []>;
374 let Defs = [R1], Uses = [R1] in
375 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "",
377 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
379 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
380 // instruction selection into a branch sequence.
381 let usesCustomInserter = 1, // Expanded after instruction selection.
382 PPC970_Single = 1 in {
383 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
386 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
389 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
392 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
395 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
400 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
401 // scavenge a register for it.
402 def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F),
405 // RESTORE_CR - Indicate that we're restoring the CR register (previously
406 // spilled), so we'll need to scavenge a register for it.
407 def RESTORE_CR : Pseudo<(outs GPRC:$cond), (ins memri:$F),
410 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
411 let isReturn = 1, Uses = [LR, RM] in
412 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
413 "b${p:cc}lr ${p:reg}", BrB,
415 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
416 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
420 def MovePCtoLR : Pseudo<(outs), (ins), "", []>,
423 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
424 let isBarrier = 1 in {
425 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
430 // BCC represents an arbitrary conditional branch on a predicate.
431 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
432 // a two-value operand where a dag node expects two operands. :(
433 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
434 "b${cond:cc} ${cond:reg}, $dst"
435 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
439 let isCall = 1, PPC970_Unit = 7,
440 // All calls clobber the non-callee saved registers...
441 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
442 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
443 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
445 CR0,CR1,CR5,CR6,CR7,CARRY] in {
446 // Convenient aliases for call instructions
448 def BL_Darwin : IForm<18, 0, 1,
449 (outs), (ins calltarget:$func, variable_ops),
450 "bl $func", BrB, []>; // See Pat patterns below.
451 def BLA_Darwin : IForm<18, 1, 1,
452 (outs), (ins aaddr:$func, variable_ops),
453 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>;
455 let Uses = [CTR, RM] in {
456 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
457 (outs), (ins variable_ops),
459 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>;
464 let isCall = 1, PPC970_Unit = 7,
465 // All calls clobber the non-callee saved registers...
466 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
467 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
468 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
470 CR0,CR1,CR5,CR6,CR7,CARRY] in {
471 // Convenient aliases for call instructions
473 def BL_SVR4 : IForm<18, 0, 1,
474 (outs), (ins calltarget:$func, variable_ops),
475 "bl $func", BrB, []>; // See Pat patterns below.
476 def BLA_SVR4 : IForm<18, 1, 1,
477 (outs), (ins aaddr:$func, variable_ops),
479 [(PPCcall_SVR4 (i32 imm:$func))]>;
481 let Uses = [CTR, RM] in {
482 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1,
483 (outs), (ins variable_ops),
485 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>;
490 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
491 def TCRETURNdi :Pseudo< (outs),
492 (ins calltarget:$dst, i32imm:$offset, variable_ops),
493 "#TC_RETURNd $dst $offset",
497 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
498 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops),
499 "#TC_RETURNa $func $offset",
500 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
502 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
503 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset, variable_ops),
504 "#TC_RETURNr $dst $offset",
508 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
509 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
510 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
511 Requires<[In32BitMode]>;
515 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
516 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
517 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
522 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
523 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
524 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
529 // DCB* instructions.
530 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
531 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
532 PPC970_DGroup_Single;
533 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
534 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
535 PPC970_DGroup_Single;
536 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
537 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
538 PPC970_DGroup_Single;
539 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
540 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
541 PPC970_DGroup_Single;
542 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
543 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
544 PPC970_DGroup_Single;
545 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
546 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
547 PPC970_DGroup_Single;
548 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
549 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
550 PPC970_DGroup_Single;
551 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
552 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
553 PPC970_DGroup_Single;
556 let usesCustomInserter = 1 in {
557 let Defs = [CR0] in {
558 def ATOMIC_LOAD_ADD_I8 : Pseudo<
559 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
560 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>;
561 def ATOMIC_LOAD_SUB_I8 : Pseudo<
562 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
563 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>;
564 def ATOMIC_LOAD_AND_I8 : Pseudo<
565 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
566 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>;
567 def ATOMIC_LOAD_OR_I8 : Pseudo<
568 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
569 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>;
570 def ATOMIC_LOAD_XOR_I8 : Pseudo<
571 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
572 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>;
573 def ATOMIC_LOAD_NAND_I8 : Pseudo<
574 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
575 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>;
576 def ATOMIC_LOAD_ADD_I16 : Pseudo<
577 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
578 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>;
579 def ATOMIC_LOAD_SUB_I16 : Pseudo<
580 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
581 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>;
582 def ATOMIC_LOAD_AND_I16 : Pseudo<
583 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
584 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>;
585 def ATOMIC_LOAD_OR_I16 : Pseudo<
586 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
587 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>;
588 def ATOMIC_LOAD_XOR_I16 : Pseudo<
589 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
590 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>;
591 def ATOMIC_LOAD_NAND_I16 : Pseudo<
592 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
593 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>;
594 def ATOMIC_LOAD_ADD_I32 : Pseudo<
595 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
596 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
597 def ATOMIC_LOAD_SUB_I32 : Pseudo<
598 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
599 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>;
600 def ATOMIC_LOAD_AND_I32 : Pseudo<
601 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
602 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>;
603 def ATOMIC_LOAD_OR_I32 : Pseudo<
604 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
605 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>;
606 def ATOMIC_LOAD_XOR_I32 : Pseudo<
607 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
608 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>;
609 def ATOMIC_LOAD_NAND_I32 : Pseudo<
610 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
611 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>;
613 def ATOMIC_CMP_SWAP_I8 : Pseudo<
614 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
616 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
617 def ATOMIC_CMP_SWAP_I16 : Pseudo<
618 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
620 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
621 def ATOMIC_CMP_SWAP_I32 : Pseudo<
622 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
624 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
626 def ATOMIC_SWAP_I8 : Pseudo<
627 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
628 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>;
629 def ATOMIC_SWAP_I16 : Pseudo<
630 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
631 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>;
632 def ATOMIC_SWAP_I32 : Pseudo<
633 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
634 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>;
638 // Instructions to support atomic operations
639 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
640 "lwarx $rD, $src", LdStLWARX,
641 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>;
644 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
645 "stwcx. $rS, $dst", LdStSTWCX,
646 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>,
649 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
650 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStGeneral, [(trap)]>;
652 //===----------------------------------------------------------------------===//
653 // PPC32 Load Instructions.
656 // Unindexed (r+i) Loads.
657 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
658 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
659 "lbz $rD, $src", LdStGeneral,
660 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
661 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
662 "lha $rD, $src", LdStLHA,
663 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
664 PPC970_DGroup_Cracked;
665 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
666 "lhz $rD, $src", LdStGeneral,
667 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
668 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
669 "lwz $rD, $src", LdStGeneral,
670 [(set GPRC:$rD, (load iaddr:$src))]>;
672 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
673 "lfs $rD, $src", LdStLFDU,
674 [(set F4RC:$rD, (load iaddr:$src))]>;
675 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
676 "lfd $rD, $src", LdStLFD,
677 [(set F8RC:$rD, (load iaddr:$src))]>;
680 // Unindexed (r+i) Loads with Update (preinc).
682 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
683 "lbzu $rD, $addr", LdStGeneral,
684 []>, RegConstraint<"$addr.reg = $ea_result">,
685 NoEncode<"$ea_result">;
687 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
688 "lhau $rD, $addr", LdStGeneral,
689 []>, RegConstraint<"$addr.reg = $ea_result">,
690 NoEncode<"$ea_result">;
692 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
693 "lhzu $rD, $addr", LdStGeneral,
694 []>, RegConstraint<"$addr.reg = $ea_result">,
695 NoEncode<"$ea_result">;
697 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
698 "lwzu $rD, $addr", LdStGeneral,
699 []>, RegConstraint<"$addr.reg = $ea_result">,
700 NoEncode<"$ea_result">;
702 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
703 "lfs $rD, $addr", LdStLFDU,
704 []>, RegConstraint<"$addr.reg = $ea_result">,
705 NoEncode<"$ea_result">;
707 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
708 "lfd $rD, $addr", LdStLFD,
709 []>, RegConstraint<"$addr.reg = $ea_result">,
710 NoEncode<"$ea_result">;
714 // Indexed (r+r) Loads.
716 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
717 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
718 "lbzx $rD, $src", LdStGeneral,
719 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
720 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
721 "lhax $rD, $src", LdStLHA,
722 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
723 PPC970_DGroup_Cracked;
724 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
725 "lhzx $rD, $src", LdStGeneral,
726 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
727 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
728 "lwzx $rD, $src", LdStGeneral,
729 [(set GPRC:$rD, (load xaddr:$src))]>;
732 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
733 "lhbrx $rD, $src", LdStGeneral,
734 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>;
735 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
736 "lwbrx $rD, $src", LdStGeneral,
737 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>;
739 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
740 "lfsx $frD, $src", LdStLFDU,
741 [(set F4RC:$frD, (load xaddr:$src))]>;
742 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
743 "lfdx $frD, $src", LdStLFDU,
744 [(set F8RC:$frD, (load xaddr:$src))]>;
747 //===----------------------------------------------------------------------===//
748 // PPC32 Store Instructions.
751 // Unindexed (r+i) Stores.
752 let PPC970_Unit = 2 in {
753 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
754 "stb $rS, $src", LdStGeneral,
755 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
756 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
757 "sth $rS, $src", LdStGeneral,
758 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
759 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
760 "stw $rS, $src", LdStGeneral,
761 [(store GPRC:$rS, iaddr:$src)]>;
762 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
763 "stfs $rS, $dst", LdStUX,
764 [(store F4RC:$rS, iaddr:$dst)]>;
765 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
766 "stfd $rS, $dst", LdStUX,
767 [(store F8RC:$rS, iaddr:$dst)]>;
770 // Unindexed (r+i) Stores with Update (preinc).
771 let PPC970_Unit = 2 in {
772 def STBU : DForm_1a<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
773 symbolLo:$ptroff, ptr_rc:$ptrreg),
774 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
775 [(set ptr_rc:$ea_res,
776 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
777 iaddroff:$ptroff))]>,
778 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
779 def STHU : DForm_1a<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
780 symbolLo:$ptroff, ptr_rc:$ptrreg),
781 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
782 [(set ptr_rc:$ea_res,
783 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
784 iaddroff:$ptroff))]>,
785 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
786 def STWU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
787 symbolLo:$ptroff, ptr_rc:$ptrreg),
788 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
789 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
790 iaddroff:$ptroff))]>,
791 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
792 def STFSU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
793 symbolLo:$ptroff, ptr_rc:$ptrreg),
794 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
795 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
796 iaddroff:$ptroff))]>,
797 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
798 def STFDU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
799 symbolLo:$ptroff, ptr_rc:$ptrreg),
800 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
801 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
802 iaddroff:$ptroff))]>,
803 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
807 // Indexed (r+r) Stores.
809 let PPC970_Unit = 2 in {
810 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
811 "stbx $rS, $dst", LdStGeneral,
812 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
813 PPC970_DGroup_Cracked;
814 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
815 "sthx $rS, $dst", LdStGeneral,
816 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
817 PPC970_DGroup_Cracked;
818 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
819 "stwx $rS, $dst", LdStGeneral,
820 [(store GPRC:$rS, xaddr:$dst)]>,
821 PPC970_DGroup_Cracked;
823 let mayStore = 1 in {
824 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
825 "stwux $rS, $rA, $rB", LdStGeneral,
828 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
829 "sthbrx $rS, $dst", LdStGeneral,
830 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>,
831 PPC970_DGroup_Cracked;
832 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
833 "stwbrx $rS, $dst", LdStGeneral,
834 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>,
835 PPC970_DGroup_Cracked;
837 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
838 "stfiwx $frS, $dst", LdStUX,
839 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
841 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
842 "stfsx $frS, $dst", LdStUX,
843 [(store F4RC:$frS, xaddr:$dst)]>;
844 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
845 "stfdx $frS, $dst", LdStUX,
846 [(store F8RC:$frS, xaddr:$dst)]>;
849 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
853 //===----------------------------------------------------------------------===//
854 // PPC32 Arithmetic Instructions.
857 let PPC970_Unit = 1 in { // FXU Operations.
858 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
859 "addi $rD, $rA, $imm", IntGeneral,
860 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
861 let Defs = [CARRY] in {
862 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
863 "addic $rD, $rA, $imm", IntGeneral,
864 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
865 PPC970_DGroup_Cracked;
866 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
867 "addic. $rD, $rA, $imm", IntGeneral,
870 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
871 "addis $rD, $rA, $imm", IntGeneral,
872 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
873 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
874 "la $rD, $sym($rA)", IntGeneral,
875 [(set GPRC:$rD, (add GPRC:$rA,
876 (PPClo tglobaladdr:$sym, 0)))]>;
877 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
878 "mulli $rD, $rA, $imm", IntMulLI,
879 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
880 let Defs = [CARRY] in {
881 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
882 "subfic $rD, $rA, $imm", IntGeneral,
883 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
886 let isReMaterializable = 1 in {
887 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
888 "li $rD, $imm", IntGeneral,
889 [(set GPRC:$rD, immSExt16:$imm)]>;
890 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
891 "lis $rD, $imm", IntGeneral,
892 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
896 let PPC970_Unit = 1 in { // FXU Operations.
897 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
898 "andi. $dst, $src1, $src2", IntGeneral,
899 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
901 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
902 "andis. $dst, $src1, $src2", IntGeneral,
903 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
905 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
906 "ori $dst, $src1, $src2", IntGeneral,
907 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
908 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
909 "oris $dst, $src1, $src2", IntGeneral,
910 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
911 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
912 "xori $dst, $src1, $src2", IntGeneral,
913 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
914 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
915 "xoris $dst, $src1, $src2", IntGeneral,
916 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
917 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral,
919 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
920 "cmpwi $crD, $rA, $imm", IntCompare>;
921 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
922 "cmplwi $dst, $src1, $src2", IntCompare>;
926 let PPC970_Unit = 1 in { // FXU Operations.
927 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
928 "nand $rA, $rS, $rB", IntGeneral,
929 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
930 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
931 "and $rA, $rS, $rB", IntGeneral,
932 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
933 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
934 "andc $rA, $rS, $rB", IntGeneral,
935 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
936 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
937 "or $rA, $rS, $rB", IntGeneral,
938 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
939 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
940 "nor $rA, $rS, $rB", IntGeneral,
941 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
942 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
943 "orc $rA, $rS, $rB", IntGeneral,
944 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
945 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
946 "eqv $rA, $rS, $rB", IntGeneral,
947 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
948 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
949 "xor $rA, $rS, $rB", IntGeneral,
950 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
951 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
952 "slw $rA, $rS, $rB", IntGeneral,
953 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
954 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
955 "srw $rA, $rS, $rB", IntGeneral,
956 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
957 let Defs = [CARRY] in {
958 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
959 "sraw $rA, $rS, $rB", IntShift,
960 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
964 let PPC970_Unit = 1 in { // FXU Operations.
965 let Defs = [CARRY] in {
966 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
967 "srawi $rA, $rS, $SH", IntShift,
968 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
970 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
971 "cntlzw $rA, $rS", IntGeneral,
972 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
973 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
974 "extsb $rA, $rS", IntGeneral,
975 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
976 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
977 "extsh $rA, $rS", IntGeneral,
978 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
980 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
981 "cmpw $crD, $rA, $rB", IntCompare>;
982 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
983 "cmplw $crD, $rA, $rB", IntCompare>;
985 let PPC970_Unit = 3 in { // FPU Operations.
986 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
987 // "fcmpo $crD, $fA, $fB", FPCompare>;
988 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
989 "fcmpu $crD, $fA, $fB", FPCompare>;
990 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
991 "fcmpu $crD, $fA, $fB", FPCompare>;
994 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
995 "fctiwz $frD, $frB", FPGeneral,
996 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
997 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
998 "frsp $frD, $frB", FPGeneral,
999 [(set F4RC:$frD, (fround F8RC:$frB))]>;
1000 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
1001 "fsqrt $frD, $frB", FPSqrt,
1002 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
1003 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
1004 "fsqrts $frD, $frB", FPSqrt,
1005 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
1009 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1010 /// often coalesced away and we don't want the dispatch group builder to think
1011 /// that they will fill slots (which could cause the load of a LSU reject to
1012 /// sneak into a d-group with a store).
1013 def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1014 "fmr $frD, $frB", FPGeneral,
1015 []>, // (set F4RC:$frD, F4RC:$frB)
1018 let PPC970_Unit = 3 in { // FPU Operations.
1019 // These are artificially split into two different forms, for 4/8 byte FP.
1020 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1021 "fabs $frD, $frB", FPGeneral,
1022 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
1023 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1024 "fabs $frD, $frB", FPGeneral,
1025 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
1026 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1027 "fnabs $frD, $frB", FPGeneral,
1028 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
1029 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1030 "fnabs $frD, $frB", FPGeneral,
1031 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
1032 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1033 "fneg $frD, $frB", FPGeneral,
1034 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
1035 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1036 "fneg $frD, $frB", FPGeneral,
1037 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
1041 // XL-Form instructions. condition register logical ops.
1043 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1044 "mcrf $BF, $BFA", BrMCR>,
1045 PPC970_DGroup_First, PPC970_Unit_CRU;
1047 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1048 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1049 "creqv $CRD, $CRA, $CRB", BrCR,
1052 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1053 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1054 "cror $CRD, $CRA, $CRB", BrCR,
1057 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1058 "creqv $dst, $dst, $dst", BrCR,
1061 def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins),
1062 "crxor $dst, $dst, $dst", BrCR,
1065 // XFX-Form instructions. Instructions that deal with SPRs.
1067 let Uses = [CTR] in {
1068 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1069 "mfctr $rT", SprMFSPR>,
1070 PPC970_DGroup_First, PPC970_Unit_FXU;
1072 let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in {
1073 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1074 "mtctr $rS", SprMTSPR>,
1075 PPC970_DGroup_First, PPC970_Unit_FXU;
1078 let Defs = [LR] in {
1079 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1080 "mtlr $rS", SprMTSPR>,
1081 PPC970_DGroup_First, PPC970_Unit_FXU;
1083 let Uses = [LR] in {
1084 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1085 "mflr $rT", SprMFSPR>,
1086 PPC970_DGroup_First, PPC970_Unit_FXU;
1089 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1090 // a GPR on the PPC970. As such, copies in and out have the same performance
1091 // characteristics as an OR instruction.
1092 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1093 "mtspr 256, $rS", IntGeneral>,
1094 PPC970_DGroup_Single, PPC970_Unit_FXU;
1095 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1096 "mfspr $rT, 256", IntGeneral>,
1097 PPC970_DGroup_First, PPC970_Unit_FXU;
1099 def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
1100 "mtcrf $FXM, $rS", BrMCRX>,
1101 PPC970_MicroCode, PPC970_Unit_CRU;
1103 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1104 // declaring that here gives the local register allocator problems with this:
1106 // MFCR <kill of whatever preg got assigned to vreg>
1107 // while not declaring it breaks DeadMachineInstructionElimination.
1108 // As it turns out, in all cases where we currently use this,
1109 // we're only interested in one subregister of it. Represent this in the
1110 // instruction to keep the register allocator from becoming confused.
1112 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1113 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1115 PPC970_MicroCode, PPC970_Unit_CRU;
1117 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
1118 "mfcr $rT", SprMFCR>,
1119 PPC970_MicroCode, PPC970_Unit_CRU;
1121 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1122 "mfcr $rT, $FXM", SprMFCR>,
1123 PPC970_DGroup_First, PPC970_Unit_CRU;
1125 // Instructions to manipulate FPSCR. Only long double handling uses these.
1126 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1128 let Uses = [RM], Defs = [RM] in {
1129 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1130 "mtfsb0 $FM", IntMTFSB0,
1131 [(PPCmtfsb0 (i32 imm:$FM))]>,
1132 PPC970_DGroup_Single, PPC970_Unit_FPU;
1133 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1134 "mtfsb1 $FM", IntMTFSB0,
1135 [(PPCmtfsb1 (i32 imm:$FM))]>,
1136 PPC970_DGroup_Single, PPC970_Unit_FPU;
1137 // MTFSF does not actually produce an FP result. We pretend it copies
1138 // input reg B to the output. If we didn't do this it would look like the
1139 // instruction had no outputs (because we aren't modelling the FPSCR) and
1140 // it would be deleted.
1141 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
1142 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
1143 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
1144 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
1145 F8RC:$rT, F8RC:$FRB))]>,
1146 PPC970_DGroup_Single, PPC970_Unit_FPU;
1148 let Uses = [RM] in {
1149 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1150 "mffs $rT", IntMFFS,
1151 [(set F8RC:$rT, (PPCmffs))]>,
1152 PPC970_DGroup_Single, PPC970_Unit_FPU;
1153 def FADDrtz: AForm_2<63, 21,
1154 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1155 "fadd $FRT, $FRA, $FRB", FPGeneral,
1156 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
1157 PPC970_DGroup_Single, PPC970_Unit_FPU;
1161 let PPC970_Unit = 1 in { // FXU Operations.
1163 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1165 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1166 "add $rT, $rA, $rB", IntGeneral,
1167 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
1168 let Defs = [CARRY] in {
1169 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1170 "addc $rT, $rA, $rB", IntGeneral,
1171 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
1172 PPC970_DGroup_Cracked;
1174 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1175 "divw $rT, $rA, $rB", IntDivW,
1176 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
1177 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1178 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1179 "divwu $rT, $rA, $rB", IntDivW,
1180 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
1181 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1182 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1183 "mulhw $rT, $rA, $rB", IntMulHW,
1184 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
1185 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1186 "mulhwu $rT, $rA, $rB", IntMulHWU,
1187 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
1188 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1189 "mullw $rT, $rA, $rB", IntMulHW,
1190 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
1191 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1192 "subf $rT, $rA, $rB", IntGeneral,
1193 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
1194 let Defs = [CARRY] in {
1195 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1196 "subfc $rT, $rA, $rB", IntGeneral,
1197 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
1198 PPC970_DGroup_Cracked;
1200 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1201 "neg $rT, $rA", IntGeneral,
1202 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
1203 let Uses = [CARRY], Defs = [CARRY] in {
1204 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1205 "adde $rT, $rA, $rB", IntGeneral,
1206 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
1207 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1208 "addme $rT, $rA", IntGeneral,
1209 [(set GPRC:$rT, (adde GPRC:$rA, -1))]>;
1210 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1211 "addze $rT, $rA", IntGeneral,
1212 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
1213 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1214 "subfe $rT, $rA, $rB", IntGeneral,
1215 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
1216 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1217 "subfme $rT, $rA", IntGeneral,
1218 [(set GPRC:$rT, (sube -1, GPRC:$rA))]>;
1219 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1220 "subfze $rT, $rA", IntGeneral,
1221 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
1225 // A-Form instructions. Most of the instructions executed in the FPU are of
1228 let PPC970_Unit = 3 in { // FPU Operations.
1229 let Uses = [RM] in {
1230 def FMADD : AForm_1<63, 29,
1231 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1232 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1233 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1235 Requires<[FPContractions]>;
1236 def FMADDS : AForm_1<59, 29,
1237 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1238 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1239 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1241 Requires<[FPContractions]>;
1242 def FMSUB : AForm_1<63, 28,
1243 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1244 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1245 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1247 Requires<[FPContractions]>;
1248 def FMSUBS : AForm_1<59, 28,
1249 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1250 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1251 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1253 Requires<[FPContractions]>;
1254 def FNMADD : AForm_1<63, 31,
1255 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1256 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1257 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1259 Requires<[FPContractions]>;
1260 def FNMADDS : AForm_1<59, 31,
1261 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1262 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1263 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1265 Requires<[FPContractions]>;
1266 def FNMSUB : AForm_1<63, 30,
1267 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1268 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1269 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1271 Requires<[FPContractions]>;
1272 def FNMSUBS : AForm_1<59, 30,
1273 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1274 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1275 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1277 Requires<[FPContractions]>;
1279 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1280 // having 4 of these, force the comparison to always be an 8-byte double (code
1281 // should use an FMRSD if the input comparison value really wants to be a float)
1282 // and 4/8 byte forms for the result and operand type..
1283 def FSELD : AForm_1<63, 23,
1284 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1285 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1286 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1287 def FSELS : AForm_1<63, 23,
1288 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1289 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1290 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1291 let Uses = [RM] in {
1292 def FADD : AForm_2<63, 21,
1293 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1294 "fadd $FRT, $FRA, $FRB", FPGeneral,
1295 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1296 def FADDS : AForm_2<59, 21,
1297 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1298 "fadds $FRT, $FRA, $FRB", FPGeneral,
1299 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1300 def FDIV : AForm_2<63, 18,
1301 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1302 "fdiv $FRT, $FRA, $FRB", FPDivD,
1303 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1304 def FDIVS : AForm_2<59, 18,
1305 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1306 "fdivs $FRT, $FRA, $FRB", FPDivS,
1307 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1308 def FMUL : AForm_3<63, 25,
1309 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1310 "fmul $FRT, $FRA, $FRB", FPFused,
1311 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1312 def FMULS : AForm_3<59, 25,
1313 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1314 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1315 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1316 def FSUB : AForm_2<63, 20,
1317 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1318 "fsub $FRT, $FRA, $FRB", FPGeneral,
1319 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1320 def FSUBS : AForm_2<59, 20,
1321 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1322 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1323 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1327 let PPC970_Unit = 1 in { // FXU Operations.
1328 // M-Form instructions. rotate and mask instructions.
1330 let isCommutable = 1 in {
1331 // RLWIMI can be commuted if the rotate amount is zero.
1332 def RLWIMI : MForm_2<20,
1333 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1334 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1335 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1338 def RLWINM : MForm_2<21,
1339 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1340 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1342 def RLWINMo : MForm_2<21,
1343 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1344 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1345 []>, isDOT, PPC970_DGroup_Cracked;
1346 def RLWNM : MForm_2<23,
1347 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1348 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1353 //===----------------------------------------------------------------------===//
1354 // PowerPC Instruction Patterns
1357 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1358 def : Pat<(i32 imm:$imm),
1359 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1361 // Implement the 'not' operation with the NOR instruction.
1362 def NOT : Pat<(not GPRC:$in),
1363 (NOR GPRC:$in, GPRC:$in)>;
1365 // ADD an arbitrary immediate.
1366 def : Pat<(add GPRC:$in, imm:$imm),
1367 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1368 // OR an arbitrary immediate.
1369 def : Pat<(or GPRC:$in, imm:$imm),
1370 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1371 // XOR an arbitrary immediate.
1372 def : Pat<(xor GPRC:$in, imm:$imm),
1373 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1375 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1376 (SUBFIC GPRC:$in, imm:$imm)>;
1379 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1380 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1381 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1382 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1385 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1386 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1387 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1388 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1391 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1392 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1395 def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)),
1396 (BL_Darwin tglobaladdr:$dst)>;
1397 def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)),
1398 (BL_Darwin texternalsym:$dst)>;
1399 def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)),
1400 (BL_SVR4 tglobaladdr:$dst)>;
1401 def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)),
1402 (BL_SVR4 texternalsym:$dst)>;
1405 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1406 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1408 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1409 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1411 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1412 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1416 // Hi and Lo for Darwin Global Addresses.
1417 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1418 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1419 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1420 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1421 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1422 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1423 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
1424 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
1425 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1426 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1427 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1428 (ADDIS GPRC:$in, tconstpool:$g)>;
1429 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1430 (ADDIS GPRC:$in, tjumptable:$g)>;
1431 def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)),
1432 (ADDIS GPRC:$in, tblockaddress:$g)>;
1434 // Fused negative multiply subtract, alternate pattern
1435 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1436 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1437 Requires<[FPContractions]>;
1438 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1439 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1440 Requires<[FPContractions]>;
1442 // Standard shifts. These are represented separately from the real shifts above
1443 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1445 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1446 (SRAW GPRC:$rS, GPRC:$rB)>;
1447 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1448 (SRW GPRC:$rS, GPRC:$rB)>;
1449 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1450 (SLW GPRC:$rS, GPRC:$rB)>;
1452 def : Pat<(zextloadi1 iaddr:$src),
1454 def : Pat<(zextloadi1 xaddr:$src),
1456 def : Pat<(extloadi1 iaddr:$src),
1458 def : Pat<(extloadi1 xaddr:$src),
1460 def : Pat<(extloadi8 iaddr:$src),
1462 def : Pat<(extloadi8 xaddr:$src),
1464 def : Pat<(extloadi16 iaddr:$src),
1466 def : Pat<(extloadi16 xaddr:$src),
1468 def : Pat<(f64 (extloadf32 iaddr:$src)),
1469 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1470 def : Pat<(f64 (extloadf32 xaddr:$src)),
1471 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1473 def : Pat<(f64 (fextend F4RC:$src)),
1474 (COPY_TO_REGCLASS F4RC:$src, F8RC)>;
1477 def : Pat<(membarrier (i32 imm /*ll*/),
1481 (i32 imm /*device*/)),
1484 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
1486 include "PPCInstrAltivec.td"
1487 include "PPCInstr64Bit.td"