1 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PowerPCInstrFormats.td"
17 let isTerminator = 1, isReturn = 1 in
18 def BLR : XLForm_2_ext<"blr", 19, 16, 20, 31, 1, 0, 0>;
20 def u5imm : Operand<i8> {
21 let PrintMethod = "printU5ImmOperand";
23 def u6imm : Operand<i8> {
24 let PrintMethod = "printU6ImmOperand";
26 def u16imm : Operand<i16> {
27 let PrintMethod = "printU16ImmOperand";
30 // Pseudo-instructions:
31 def PHI : Pseudo<"PHI">;
32 def ADJCALLSTACKDOWN : Pseudo<"ADJCALLSTACKDOWN">;
33 def ADJCALLSTACKUP : Pseudo<"ADJCALLSTACKUP">;
35 def MovePCtoLR : Pseudo<"MovePCtoLR">;
36 def IMPLICIT_DEF : Pseudo<"IMPLICIT_DEF">;
38 let isBranch = 1, isTerminator = 1 in {
39 def COND_BRANCH : Pseudo<"COND_BRANCH">;
40 def B : IForm<"b", 18, 0, 0, 0, 0>;
41 // FIXME: 4*CR# needs to be added to the BI field!
42 // This will only work for CR0 as it stands now
43 def BLT : BForm_ext<"blt", 16, 0, 0, 12, 0, 0, 0>;
44 def BLE : BForm_ext<"ble", 16, 0, 0, 4, 1, 0, 0>;
45 def BEQ : BForm_ext<"beq", 16, 0, 0, 12, 2, 0, 0>;
46 def BGE : BForm_ext<"bge", 16, 0, 0, 4, 0, 0, 0>;
47 def BGT : BForm_ext<"bgt", 16, 0, 0, 12, 1, 0, 0>;
48 def BNE : BForm_ext<"bne", 16, 0, 0, 4, 2, 0, 0>;
51 let isBranch = 1, isTerminator = 1, isCall = 1,
52 // All calls clobber the non-callee saved registers...
53 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
54 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
56 CR0,CR1,CR5,CR6,CR7] in {
57 // Convenient aliases for call instructions
58 def CALLpcrel : IForm<"bl", 18, 0, 1, 0, 0>;
59 def CALLindirect : XLForm_2_ext<"bctrl", 19, 528, 20, 31, 1, 0, 0>;
62 def LA : DForm_2<"la", 14, 0, 0>;
63 def LOADHiAddr : DForm_2_r0<"addis", 15, 0, 0>;
65 def LBZ : DForm_1<"lbz", 35, 0, 0>;
66 def LHA : DForm_1<"lha", 42, 0, 0>;
67 def LHZ : DForm_1<"lhz", 40, 0, 0>;
68 def LMW : DForm_1<"lmw", 46, 0, 0>;
69 def LWZ : DForm_1<"lwz", 32, 0, 0>;
70 def ADDI : DForm_2<"addi", 14, 0, 0>;
71 def ADDIC : DForm_2<"addic", 12, 0, 0>;
72 def ADDICo : DForm_2<"addic.", 13, 0, 0>;
73 def ADDIS : DForm_2<"addis", 15, 0, 0>;
74 def MULLI : DForm_2<"mulli", 7, 0, 0>;
75 def SUBFIC : DForm_2<"subfic", 8, 0, 0>;
76 def SUBI : DForm_2<"subi", 14, 0, 0>;
77 def LI : DForm_2_r0<"li", 14, 0, 0>;
78 def LIS : DForm_2_r0<"lis", 15, 0, 0>;
79 def STMW : DForm_3<"stmw", 47, 0, 0>;
80 def STB : DForm_3<"stb", 38, 0, 0>;
81 def STBU : DForm_3<"stbu", 39, 0, 0>;
82 def STH : DForm_3<"sth", 44, 0, 0>;
83 def STHU : DForm_3<"sthu", 45, 0, 0>;
84 def STW : DForm_3<"stw", 36, 0, 0>;
85 def STWU : DForm_3<"stwu", 37, 0, 0>;
86 def CMPI : DForm_5<"cmpi", 11, 0, 0>;
87 def CMPWI : DForm_5_ext<"cmpwi", 11, 0, 0>;
88 def CMPDI : DForm_5_ext<"cmpdi", 11, 1, 0>;
89 def LFS : DForm_8<"lfs", 48, 0, 0>;
90 def LFD : DForm_8<"lfd", 50, 0, 0>;
91 def STFS : DForm_9<"stfs", 52, 0, 0>;
92 def STFD : DForm_9<"stfd", 54, 0, 0>;
94 def LWA : DSForm_1<"lwa", 58, 2, 1, 0>;
95 def LD : DSForm_2<"ld", 58, 0, 1, 0>;
96 def STD : DSForm_2<"std", 62, 0, 1, 0>;
97 def STDU : DSForm_2<"stdu", 62, 1, 1, 0>;
99 def CMP : XForm_16<"cmp", 31, 0, 0, 0>;
100 def CMPL : XForm_16<"cmpl", 31, 32, 0, 0>;
101 def CMPW : XForm_16_ext<"cmpw", 31, 0, 0, 0>;
102 def CMPD : XForm_16_ext<"cmpd", 31, 0, 1, 0>;
103 def CMPLW : XForm_16_ext<"cmplw", 31, 32, 0, 0>;
104 def CMPLD : XForm_16_ext<"cmpld", 31, 32, 1, 0>;
106 // D-Form instructions. Most instructions that perform an operation on a
107 // register and an immediate are of this type.
109 def ANDIo : DForm_4<28, 0, 0,
110 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
111 "andi. $dst, $src1, $src2">;
112 def ORI : DForm_4<24, 0, 0,
113 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
114 "ori $dst, $src1, $src2">;
115 def ORIS : DForm_4<25, 0, 0,
116 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
117 "oris $dst, $src1, $src2">;
118 def XORI : DForm_4<26, 0, 0,
119 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
120 "xori $dst, $src1, $src2">;
121 def XORIS : DForm_4<27, 0, 0,
122 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
123 "xoris $dst, $src1, $src2">;
124 def NOP : DForm_4_zero<"nop", 24, 0, 0, (ops), "nop">;
125 def CMPLI : DForm_6<10, 0, 0,
126 (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
127 "cmpli $dst, $size, $src1, $src2">;
128 def CMPLWI : DForm_6_ext<10, 0, 0,
129 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
130 "cmplwi $dst, $src1, $src2">;
131 def CMPLDI : DForm_6_ext<10, 1, 0,
132 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
133 "cmpldi $dst, $src1, $src2">;
135 // X-Form instructions. Most instructions that perform an operation on a
136 // register and another register are of this type.
138 def LBZX : XForm_1<31, 87, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
139 "lbzx $dst, $base, $index">;
140 def LHAX : XForm_1<31, 343, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
141 "lhax $dst, $base, $index">;
142 def LHZX : XForm_1<31, 279, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
143 "lhzx $dst, $base, $index">;
144 def LWAX : XForm_1<31, 341, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
145 "lwax $dst, $base, $index">;
146 def LWZX : XForm_1<31, 23, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
147 "lwzx $dst, $base, $index">;
148 def LDX : XForm_1<31, 21, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
149 "ldx $dst, $base, $index">;
150 def MFCR : XForm_5<31, 19, 0, 0, (ops GPRC:$dst), "mfcr $dst">;
151 def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
152 "and $rA, $rS, $rB">;
153 def ANDC : XForm_6<31, 60, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
154 "andc $rA, $rS, $rB">;
155 def EQV : XForm_6<31, 284, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
156 "eqv $rA, $rS, $rB">;
157 def NAND : XForm_6<31, 476, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
158 "nand $rA, $rS, $rB">;
159 def NOR : XForm_6<31, 124, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
160 "nor $rA, $rS, $rB">;
161 def OR : XForm_6<31, 444, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
163 def ORo : XForm_6<31, 444, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
164 "or. $rA, $rS, $rB">;
165 def ORC : XForm_6<31, 412, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
166 "orc $rA, $rS, $rB">;
167 def SLD : XForm_6<31, 27, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
168 "sld $rA, $rS, $rB">;
169 def SLW : XForm_6<31, 24, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
170 "slw $rA, $rS, $rB">;
171 def SRD : XForm_6<31, 539, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
172 "srd $rA, $rS, $rB">;
173 def SRW : XForm_6<31, 536, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
174 "srw $rA, $rS, $rB">;
175 def SRAD : XForm_6<31, 794, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
176 "srad $rA, $rS, $rB">;
177 def SRAW : XForm_6<31, 792, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
178 "sraw $rA, $rS, $rB">;
179 def XOR : XForm_6<31, 316, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
180 "xor $rA, $rS, $rB">;
181 def STBX : XForm_8<31, 215, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
182 "stbx $rS, $rA, $rB">;
183 def STHX : XForm_8<31, 407, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
184 "sthx $rS, $rA, $rB">;
185 def STWX : XForm_8<31, 151, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
186 "stwx $rS, $rA, $rB">;
187 def STWUX : XForm_8<31, 183, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
188 "stwux $rS, $rA, $rB">;
189 def STDX : XForm_8<31, 149, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
190 "stdx $rS, $rA, $rB">;
191 def STDUX : XForm_8<31, 181, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
192 "stdux $rS, $rA, $rB">;
193 def SRAWI : XForm_10<31, 824, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
194 "srawi $rA, $rS, $SH">;
195 def CNTLZW : XForm_11<31, 26, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
197 def EXTSB : XForm_11<31, 954, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
199 def EXTSH : XForm_11<31, 922, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
201 def EXTSW : XForm_11<31, 986, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS),
203 def FCMPU : XForm_17<63, 0, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
204 "fcmpu $crD, $fA, $fB">;
205 def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
206 "lfsx $dst, $base, $index">;
207 def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
208 "lfdx $dst, $base, $index">;
209 def FCFID : XForm_26<63, 846, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
211 def FCTIDZ : XForm_26<63, 815, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
212 "fctidz $frD, $frB">;
213 def FCTIWZ : XForm_26<63, 15, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
214 "fctiwz $frD, $frB">;
215 def FMR : XForm_26<63, 72, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
217 def FNEG : XForm_26<63, 80, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
219 def FRSP : XForm_26<63, 12, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
221 def STFSX : XForm_28<31, 663, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
222 "stfsx $frS, $rA, $rB">;
223 def STFDX : XForm_28<31, 727, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
224 "stfdx $frS, $rA, $rB">;
226 // XL-Form instructions. condition register logical ops.
228 def CRAND : XLForm_1<19, 257, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
230 def CRANDC : XLForm_1<19, 129, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
231 "crandc $D, $A, $B">;
232 def CRNOR : XLForm_1<19, 33, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
234 def CROR : XLForm_1<19, 449, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
237 // XFX-Form instructions. Instructions that deal with SPRs
239 def MFCTR : XFXForm_1_ext<31, 399, 9, 0, 0, (ops GPRC:$rT), "mfctr $rT">;
240 def MFLR : XFXForm_1_ext<31, 399, 8, 0, 0, (ops GPRC:$rT), "mflr $rT">;
241 def MTCTR : XFXForm_7_ext<31, 467, 9, 0, 0, (ops GPRC:$rS), "mtctr $rS">;
242 def MTLR : XFXForm_7_ext<31, 467, 8, 0, 0, (ops GPRC:$rS), "mtlr $rS">;
245 // XS-Form instructions. Just 'sradi'
247 def SRADI : XSForm_1<31, 413, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
248 "sradi $rA, $rS, $SH">;
250 // XO-Form instructions. Arithmetic instructions that can set overflow bit
252 def ADD : XOForm_1<31, 266, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
253 "add $rT, $rA, $rB">;
254 def ADDC : XOForm_1<31, 10, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
255 "addc $rT, $rA, $rB">;
256 def ADDE : XOForm_1<31, 138, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
257 "adde $rT, $rA, $rB">;
258 def DIVW : XOForm_1<31, 491, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
259 "divw $rT, $rA, $rB">;
260 def DIVWU : XOForm_1<31, 459, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
261 "divwu $rT, $rA, $rB">;
262 def MULHWU : XOForm_1<31, 11, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
263 "mulhwu $rT, $rA, $rB">;
264 def MULLD : XOForm_1<31, 233, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
265 "mulld $rT, $rA, $rB">;
266 def MULLW : XOForm_1<31, 235, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
267 "mullw $rT, $rA, $rB">;
268 def SUBF : XOForm_1<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
269 "subf $rT, $rA, $rB">;
270 def SUBFC : XOForm_1<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
271 "subfc $rT, $rA, $rB">;
272 def SUBFE : XOForm_1<31, 136, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
273 "subfe $rT, $rA, $rB">;
274 def SUB : XOForm_1r<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
275 "sub $rT, $rA, $rB">;
276 def SUBC : XOForm_1r<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
277 "subc $rT, $rA, $rB">;
278 def ADDZE : XOForm_3<31, 202, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
280 def NEG : XOForm_3<31, 104, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
282 def SUBFZE : XOForm_3<31, 200, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
285 // A-Form instructions. Most of the instructions executed in the FPU are of
288 def FMADD : AForm_1<63, 29, 0, 0, 0,
289 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
290 "fmadd $FRT, $FRA, $FRC, $FRB">;
291 def FSEL : AForm_1<63, 23, 0, 0, 0,
292 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
293 "fsel $FRT, $FRA, $FRC, $FRB">;
294 def FADD : AForm_2<63, 21, 0, 0, 0,
295 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
296 "fadd $FRT, $FRA, $FRB">;
297 def FADDS : AForm_2<59, 21, 0, 0, 0,
298 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
299 "fadds $FRT, $FRA, $FRB">;
300 def FDIV : AForm_2<63, 18, 0, 0, 0,
301 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
302 "fdiv $FRT, $FRA, $FRB">;
303 def FDIVS : AForm_2<59, 18, 0, 0, 0,
304 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
305 "fdivs $FRT, $FRA, $FRB">;
306 def FMUL : AForm_3<63, 25, 0, 0, 0,
307 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
308 "fmul $FRT, $FRA, $FRB">;
309 def FMULS : AForm_3<59, 25, 0, 0, 0,
310 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
311 "fmuls $FRT, $FRA, $FRB">;
312 def FSUB : AForm_2<63, 20, 0, 0, 0,
313 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
314 "fsub $FRT, $FRA, $FRB">;
315 def FSUBS : AForm_2<59, 20, 0, 0, 0,
316 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
317 "fsubs $FRT, $FRA, $FRB">;
319 // M-Form instructions. rotate and mask instructions.
321 def RLWIMI : MForm_2<20, 0, 0, 0,
322 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
323 "rlwimi $rA, $rS, $SH, $MB, $ME">;
324 def RLWINM : MForm_2<21, 0, 0, 0,
325 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
326 "rlwinm $rA, $rS, $SH, $MB, $ME">;
329 // MD-Form instructions. 64 bit rotate instructions.
331 def RLDICL : MDForm_1<30, 0, 0, 1, 0,
332 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
333 "rldicl $rA, $rS, $SH, $MB">;
334 def RLDICR : MDForm_1<30, 1, 0, 1, 0,
335 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
336 "rldicr $rA, $rS, $SH, $ME">;