1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 3, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 4, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
45 def SDT_PPClarx : SDTypeProfile<1, 1, [
46 SDTCisInt<0>, SDTCisPtrTy<1>
48 def SDT_PPCstcx : SDTypeProfile<0, 2, [
49 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
53 SDTCisPtrTy<0>, SDTCisVT<1, i32>
56 //===----------------------------------------------------------------------===//
57 // PowerPC specific DAG Nodes.
60 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
61 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
62 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
63 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
64 [SDNPHasChain, SDNPMayStore]>;
66 // This sequence is used for long double->int conversions. It changes the
67 // bits in the FPSCR which is not modelled.
68 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
70 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
71 [SDNPInFlag, SDNPOutFlag]>;
72 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
73 [SDNPInFlag, SDNPOutFlag]>;
74 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
75 [SDNPInFlag, SDNPOutFlag]>;
76 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
77 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
81 def PPCfsel : SDNode<"PPCISD::FSEL",
82 // Type constraint for fsel.
83 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
84 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
86 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
87 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
88 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
89 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
91 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
93 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
94 // amounts. These nodes are generated by the multi-precision shift code.
95 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
96 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
97 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
99 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
100 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
101 [SDNPHasChain, SDNPMayStore]>;
103 // These are target-independent nodes, but have target-specific formats.
104 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
105 [SDNPHasChain, SDNPOutFlag]>;
106 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
107 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
109 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
110 def PPCcall_Macho : SDNode<"PPCISD::CALL_Macho", SDT_PPCCall,
111 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
112 def PPCcall_ELF : SDNode<"PPCISD::CALL_ELF", SDT_PPCCall,
113 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
114 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
115 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
116 def PPCbctrl_Macho : SDNode<"PPCISD::BCTRL_Macho", SDTNone,
117 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
119 def PPCbctrl_ELF : SDNode<"PPCISD::BCTRL_ELF", SDTNone,
120 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
122 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
123 [SDNPHasChain, SDNPOptInFlag]>;
125 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
126 [SDNPHasChain, SDNPOptInFlag]>;
128 def PPCtailcall : SDNode<"PPCISD::TAILCALL", SDT_PPCCall,
129 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
131 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
132 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
134 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
135 [SDNPHasChain, SDNPOptInFlag]>;
137 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
138 [SDNPHasChain, SDNPMayLoad]>;
139 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
140 [SDNPHasChain, SDNPMayStore]>;
142 // Instructions to support atomic operations
143 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
144 [SDNPHasChain, SDNPMayLoad]>;
145 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
146 [SDNPHasChain, SDNPMayStore]>;
148 // Instructions to support dynamic alloca.
149 def SDTDynOp : SDTypeProfile<1, 2, []>;
150 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
152 //===----------------------------------------------------------------------===//
153 // PowerPC specific transformation functions and pattern fragments.
156 def SHL32 : SDNodeXForm<imm, [{
157 // Transformation function: 31 - imm
158 return getI32Imm(31 - N->getValue());
161 def SRL32 : SDNodeXForm<imm, [{
162 // Transformation function: 32 - imm
163 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
166 def LO16 : SDNodeXForm<imm, [{
167 // Transformation function: get the low 16 bits.
168 return getI32Imm((unsigned short)N->getValue());
171 def HI16 : SDNodeXForm<imm, [{
172 // Transformation function: shift the immediate value down into the low bits.
173 return getI32Imm((unsigned)N->getValue() >> 16);
176 def HA16 : SDNodeXForm<imm, [{
177 // Transformation function: shift the immediate value down into the low bits.
178 signed int Val = N->getValue();
179 return getI32Imm((Val - (signed short)Val) >> 16);
181 def MB : SDNodeXForm<imm, [{
182 // Transformation function: get the start bit of a mask
184 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
185 return getI32Imm(mb);
188 def ME : SDNodeXForm<imm, [{
189 // Transformation function: get the end bit of a mask
191 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
192 return getI32Imm(me);
194 def maskimm32 : PatLeaf<(imm), [{
195 // maskImm predicate - True if immediate is a run of ones.
197 if (N->getValueType(0) == MVT::i32)
198 return isRunOfOnes((unsigned)N->getValue(), mb, me);
203 def immSExt16 : PatLeaf<(imm), [{
204 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
205 // field. Used by instructions like 'addi'.
206 if (N->getValueType(0) == MVT::i32)
207 return (int32_t)N->getValue() == (short)N->getValue();
209 return (int64_t)N->getValue() == (short)N->getValue();
211 def immZExt16 : PatLeaf<(imm), [{
212 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
213 // field. Used by instructions like 'ori'.
214 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
217 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
218 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
219 // identical in 32-bit mode, but in 64-bit mode, they return true if the
220 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
222 def imm16ShiftedZExt : PatLeaf<(imm), [{
223 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
224 // immediate are set. Used by instructions like 'xoris'.
225 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
228 def imm16ShiftedSExt : PatLeaf<(imm), [{
229 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
230 // immediate are set. Used by instructions like 'addis'. Identical to
231 // imm16ShiftedZExt in 32-bit mode.
232 if (N->getValue() & 0xFFFF) return false;
233 if (N->getValueType(0) == MVT::i32)
235 // For 64-bit, make sure it is sext right.
236 return N->getValue() == (uint64_t)(int)N->getValue();
240 //===----------------------------------------------------------------------===//
241 // PowerPC Flag Definitions.
243 class isPPC64 { bit PPC64 = 1; }
245 list<Register> Defs = [CR0];
249 class RegConstraint<string C> {
250 string Constraints = C;
252 class NoEncode<string E> {
253 string DisableEncoding = E;
257 //===----------------------------------------------------------------------===//
258 // PowerPC Operand Definitions.
260 def s5imm : Operand<i32> {
261 let PrintMethod = "printS5ImmOperand";
263 def u5imm : Operand<i32> {
264 let PrintMethod = "printU5ImmOperand";
266 def u6imm : Operand<i32> {
267 let PrintMethod = "printU6ImmOperand";
269 def s16imm : Operand<i32> {
270 let PrintMethod = "printS16ImmOperand";
272 def u16imm : Operand<i32> {
273 let PrintMethod = "printU16ImmOperand";
275 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
276 let PrintMethod = "printS16X4ImmOperand";
278 def target : Operand<OtherVT> {
279 let PrintMethod = "printBranchOperand";
281 def calltarget : Operand<iPTR> {
282 let PrintMethod = "printCallOperand";
284 def aaddr : Operand<iPTR> {
285 let PrintMethod = "printAbsAddrOperand";
287 def piclabel: Operand<iPTR> {
288 let PrintMethod = "printPICLabel";
290 def symbolHi: Operand<i32> {
291 let PrintMethod = "printSymbolHi";
293 def symbolLo: Operand<i32> {
294 let PrintMethod = "printSymbolLo";
296 def crbitm: Operand<i8> {
297 let PrintMethod = "printcrbitm";
300 def memri : Operand<iPTR> {
301 let PrintMethod = "printMemRegImm";
302 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
304 def memrr : Operand<iPTR> {
305 let PrintMethod = "printMemRegReg";
306 let MIOperandInfo = (ops ptr_rc, ptr_rc);
308 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
309 let PrintMethod = "printMemRegImmShifted";
310 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
313 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
314 // that doesn't matter.
315 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
316 (ops (i32 20), (i32 zero_reg))> {
317 let PrintMethod = "printPredicateOperand";
320 // Define PowerPC specific addressing mode.
321 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
322 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
323 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
324 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
326 /// This is just the offset part of iaddr, used for preinc.
327 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
329 //===----------------------------------------------------------------------===//
330 // PowerPC Instruction Predicate Definitions.
331 def FPContractions : Predicate<"!NoExcessFPPrecision">;
332 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
333 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
336 //===----------------------------------------------------------------------===//
337 // PowerPC Instruction Definitions.
339 // Pseudo-instructions:
341 let hasCtrlDep = 1 in {
342 let Defs = [R1], Uses = [R1] in {
343 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
344 "${:comment} ADJCALLSTACKDOWN",
345 [(callseq_start imm:$amt)]>;
346 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
347 "${:comment} ADJCALLSTACKUP",
348 [(callseq_end imm:$amt1, imm:$amt2)]>;
351 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
352 "UPDATE_VRSAVE $rD, $rS", []>;
355 let Defs = [R1], Uses = [R1] in
356 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi),
357 "${:comment} DYNALLOC $result, $negsize, $fpsi",
359 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
361 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
362 // scheduler into a branch sequence.
363 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
364 PPC970_Single = 1 in {
365 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
366 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
368 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
369 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
371 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
372 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
374 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
375 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
377 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
378 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
382 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
383 // scavenge a register for it.
384 def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F),
385 "${:comment} SPILL_CR $cond $F", []>;
387 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
389 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
390 "b${p:cc}lr ${p:reg}", BrB,
392 let isBranch = 1, isIndirectBranch = 1 in
393 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
397 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
400 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
401 let isBarrier = 1 in {
402 def B : IForm<18, 0, 0, (outs), (ins target:$dst),
407 // BCC represents an arbitrary conditional branch on a predicate.
408 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
409 // a two-value operand where a dag node expects two operands. :(
410 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst),
411 "b${cond:cc} ${cond:reg}, $dst"
412 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
416 let isCall = 1, PPC970_Unit = 7,
417 // All calls clobber the non-callee saved registers...
418 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
419 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
420 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
423 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
424 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
425 // Convenient aliases for call instructions
426 def BL_Macho : IForm<18, 0, 1,
427 (outs), (ins calltarget:$func, variable_ops),
428 "bl $func", BrB, []>; // See Pat patterns below.
429 def BLA_Macho : IForm<18, 1, 1,
430 (outs), (ins aaddr:$func, variable_ops),
431 "bla $func", BrB, [(PPCcall_Macho (i32 imm:$func))]>;
432 def BCTRL_Macho : XLForm_2_ext<19, 528, 20, 0, 1,
433 (outs), (ins variable_ops),
435 [(PPCbctrl_Macho)]>, Requires<[In32BitMode]>;
439 let isCall = 1, PPC970_Unit = 7,
440 // All calls clobber the non-callee saved registers...
441 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
442 F0,F1,F2,F3,F4,F5,F6,F7,F8,
443 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
446 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
447 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
448 // Convenient aliases for call instructions
449 def BL_ELF : IForm<18, 0, 1,
450 (outs), (ins calltarget:$func, variable_ops),
451 "bl $func", BrB, []>; // See Pat patterns below.
452 def BLA_ELF : IForm<18, 1, 1,
453 (outs), (ins aaddr:$func, variable_ops),
455 [(PPCcall_ELF (i32 imm:$func))]>;
456 def BCTRL_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
457 (outs), (ins variable_ops),
459 [(PPCbctrl_ELF)]>, Requires<[In32BitMode]>;
463 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
464 def TCRETURNdi :Pseudo< (outs),
465 (ins calltarget:$dst, i32imm:$offset, variable_ops),
466 "#TC_RETURNd $dst $offset",
470 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
471 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops),
472 "#TC_RETURNa $func $offset",
473 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
475 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
476 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset, variable_ops),
477 "#TC_RETURNr $dst $offset",
481 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
482 isIndirectBranch = 1, isCall = 1, isReturn = 1 in
483 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
484 Requires<[In32BitMode]>;
488 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
489 isBarrier = 1, isCall = 1, isReturn = 1 in
490 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
495 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
496 isBarrier = 1, isCall = 1, isReturn = 1 in
497 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
502 // DCB* instructions.
503 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
504 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
505 PPC970_DGroup_Single;
506 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
507 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
508 PPC970_DGroup_Single;
509 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
510 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
511 PPC970_DGroup_Single;
512 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
513 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
514 PPC970_DGroup_Single;
515 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
516 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
517 PPC970_DGroup_Single;
518 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
519 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
520 PPC970_DGroup_Single;
521 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
522 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
523 PPC970_DGroup_Single;
524 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
525 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
526 PPC970_DGroup_Single;
529 let usesCustomDAGSchedInserter = 1 in {
530 let Uses = [CR0] in {
531 def ATOMIC_LOAD_ADD_I32 : Pseudo<
532 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
533 "${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!",
534 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
535 def ATOMIC_LOAD_SUB_I32 : Pseudo<
536 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
537 "${:comment} ATOMIC_LOAD_SUB_I32 PSEUDO!",
538 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>;
539 def ATOMIC_LOAD_AND_I32 : Pseudo<
540 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
541 "${:comment} ATOMIC_LOAD_AND_I32 PSEUDO!",
542 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>;
543 def ATOMIC_LOAD_OR_I32 : Pseudo<
544 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
545 "${:comment} ATOMIC_LOAD_OR_I32 PSEUDO!",
546 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>;
547 def ATOMIC_LOAD_XOR_I32 : Pseudo<
548 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
549 "${:comment} ATOMIC_LOAD_XOR_I32 PSEUDO!",
550 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>;
551 def ATOMIC_LOAD_NAND_I32 : Pseudo<
552 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
553 "${:comment} ATOMIC_LOAD_NAND_I32 PSEUDO!",
554 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>;
556 def ATOMIC_CMP_SWAP_I32 : Pseudo<
557 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
558 "${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
560 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
562 def ATOMIC_SWAP_I32 : Pseudo<
563 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
564 "${:comment} ATOMIC_SWAP_I32 PSEUDO!",
565 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>;
569 // Instructions to support atomic operations
570 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
571 "lwarx $rD, $src", LdStLWARX,
572 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>;
575 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
576 "stwcx. $rS, $dst", LdStSTWCX,
577 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>,
580 let isBarrier = 1, hasCtrlDep = 1 in
581 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStGeneral, [(trap)]>;
583 //===----------------------------------------------------------------------===//
584 // PPC32 Load Instructions.
587 // Unindexed (r+i) Loads.
588 let isSimpleLoad = 1, PPC970_Unit = 2 in {
589 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
590 "lbz $rD, $src", LdStGeneral,
591 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
592 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
593 "lha $rD, $src", LdStLHA,
594 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
595 PPC970_DGroup_Cracked;
596 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
597 "lhz $rD, $src", LdStGeneral,
598 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
599 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
600 "lwz $rD, $src", LdStGeneral,
601 [(set GPRC:$rD, (load iaddr:$src))]>;
603 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
604 "lfs $rD, $src", LdStLFDU,
605 [(set F4RC:$rD, (load iaddr:$src))]>;
606 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
607 "lfd $rD, $src", LdStLFD,
608 [(set F8RC:$rD, (load iaddr:$src))]>;
611 // Unindexed (r+i) Loads with Update (preinc).
612 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
613 "lbzu $rD, $addr", LdStGeneral,
614 []>, RegConstraint<"$addr.reg = $ea_result">,
615 NoEncode<"$ea_result">;
617 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
618 "lhau $rD, $addr", LdStGeneral,
619 []>, RegConstraint<"$addr.reg = $ea_result">,
620 NoEncode<"$ea_result">;
622 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
623 "lhzu $rD, $addr", LdStGeneral,
624 []>, RegConstraint<"$addr.reg = $ea_result">,
625 NoEncode<"$ea_result">;
627 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
628 "lwzu $rD, $addr", LdStGeneral,
629 []>, RegConstraint<"$addr.reg = $ea_result">,
630 NoEncode<"$ea_result">;
632 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
633 "lfs $rD, $addr", LdStLFDU,
634 []>, RegConstraint<"$addr.reg = $ea_result">,
635 NoEncode<"$ea_result">;
637 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
638 "lfd $rD, $addr", LdStLFD,
639 []>, RegConstraint<"$addr.reg = $ea_result">,
640 NoEncode<"$ea_result">;
643 // Indexed (r+r) Loads.
645 let isSimpleLoad = 1, PPC970_Unit = 2 in {
646 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
647 "lbzx $rD, $src", LdStGeneral,
648 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
649 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
650 "lhax $rD, $src", LdStLHA,
651 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
652 PPC970_DGroup_Cracked;
653 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
654 "lhzx $rD, $src", LdStGeneral,
655 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
656 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
657 "lwzx $rD, $src", LdStGeneral,
658 [(set GPRC:$rD, (load xaddr:$src))]>;
661 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
662 "lhbrx $rD, $src", LdStGeneral,
663 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
664 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
665 "lwbrx $rD, $src", LdStGeneral,
666 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
668 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
669 "lfsx $frD, $src", LdStLFDU,
670 [(set F4RC:$frD, (load xaddr:$src))]>;
671 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
672 "lfdx $frD, $src", LdStLFDU,
673 [(set F8RC:$frD, (load xaddr:$src))]>;
676 //===----------------------------------------------------------------------===//
677 // PPC32 Store Instructions.
680 // Unindexed (r+i) Stores.
681 let PPC970_Unit = 2 in {
682 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
683 "stb $rS, $src", LdStGeneral,
684 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
685 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
686 "sth $rS, $src", LdStGeneral,
687 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
688 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
689 "stw $rS, $src", LdStGeneral,
690 [(store GPRC:$rS, iaddr:$src)]>;
691 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
692 "stfs $rS, $dst", LdStUX,
693 [(store F4RC:$rS, iaddr:$dst)]>;
694 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
695 "stfd $rS, $dst", LdStUX,
696 [(store F8RC:$rS, iaddr:$dst)]>;
699 // Unindexed (r+i) Stores with Update (preinc).
700 let PPC970_Unit = 2 in {
701 def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
702 symbolLo:$ptroff, ptr_rc:$ptrreg),
703 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
704 [(set ptr_rc:$ea_res,
705 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
706 iaddroff:$ptroff))]>,
707 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
708 def STHU : DForm_1<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
709 symbolLo:$ptroff, ptr_rc:$ptrreg),
710 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
711 [(set ptr_rc:$ea_res,
712 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
713 iaddroff:$ptroff))]>,
714 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
715 def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
716 symbolLo:$ptroff, ptr_rc:$ptrreg),
717 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
718 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
719 iaddroff:$ptroff))]>,
720 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
721 def STFSU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
722 symbolLo:$ptroff, ptr_rc:$ptrreg),
723 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
724 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
725 iaddroff:$ptroff))]>,
726 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
727 def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
728 symbolLo:$ptroff, ptr_rc:$ptrreg),
729 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
730 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
731 iaddroff:$ptroff))]>,
732 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
736 // Indexed (r+r) Stores.
738 let PPC970_Unit = 2 in {
739 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
740 "stbx $rS, $dst", LdStGeneral,
741 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
742 PPC970_DGroup_Cracked;
743 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
744 "sthx $rS, $dst", LdStGeneral,
745 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
746 PPC970_DGroup_Cracked;
747 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
748 "stwx $rS, $dst", LdStGeneral,
749 [(store GPRC:$rS, xaddr:$dst)]>,
750 PPC970_DGroup_Cracked;
752 let mayStore = 1 in {
753 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
754 "stwux $rS, $rA, $rB", LdStGeneral,
757 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
758 "sthbrx $rS, $dst", LdStGeneral,
759 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
760 PPC970_DGroup_Cracked;
761 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
762 "stwbrx $rS, $dst", LdStGeneral,
763 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>,
764 PPC970_DGroup_Cracked;
766 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
767 "stfiwx $frS, $dst", LdStUX,
768 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
770 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
771 "stfsx $frS, $dst", LdStUX,
772 [(store F4RC:$frS, xaddr:$dst)]>;
773 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
774 "stfdx $frS, $dst", LdStUX,
775 [(store F8RC:$frS, xaddr:$dst)]>;
779 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
783 //===----------------------------------------------------------------------===//
784 // PPC32 Arithmetic Instructions.
787 let PPC970_Unit = 1 in { // FXU Operations.
788 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
789 "addi $rD, $rA, $imm", IntGeneral,
790 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
791 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
792 "addic $rD, $rA, $imm", IntGeneral,
793 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
794 PPC970_DGroup_Cracked;
795 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
796 "addic. $rD, $rA, $imm", IntGeneral,
798 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
799 "addis $rD, $rA, $imm", IntGeneral,
800 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
801 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
802 "la $rD, $sym($rA)", IntGeneral,
803 [(set GPRC:$rD, (add GPRC:$rA,
804 (PPClo tglobaladdr:$sym, 0)))]>;
805 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
806 "mulli $rD, $rA, $imm", IntMulLI,
807 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
808 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
809 "subfic $rD, $rA, $imm", IntGeneral,
810 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
812 let isReMaterializable = 1 in {
813 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
814 "li $rD, $imm", IntGeneral,
815 [(set GPRC:$rD, immSExt16:$imm)]>;
816 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
817 "lis $rD, $imm", IntGeneral,
818 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
822 let PPC970_Unit = 1 in { // FXU Operations.
823 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
824 "andi. $dst, $src1, $src2", IntGeneral,
825 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
827 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
828 "andis. $dst, $src1, $src2", IntGeneral,
829 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
831 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
832 "ori $dst, $src1, $src2", IntGeneral,
833 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
834 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
835 "oris $dst, $src1, $src2", IntGeneral,
836 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
837 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
838 "xori $dst, $src1, $src2", IntGeneral,
839 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
840 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
841 "xoris $dst, $src1, $src2", IntGeneral,
842 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
843 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral,
845 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
846 "cmpwi $crD, $rA, $imm", IntCompare>;
847 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
848 "cmplwi $dst, $src1, $src2", IntCompare>;
852 let PPC970_Unit = 1 in { // FXU Operations.
853 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
854 "nand $rA, $rS, $rB", IntGeneral,
855 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
856 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
857 "and $rA, $rS, $rB", IntGeneral,
858 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
859 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
860 "andc $rA, $rS, $rB", IntGeneral,
861 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
862 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
863 "or $rA, $rS, $rB", IntGeneral,
864 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
865 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
866 "nor $rA, $rS, $rB", IntGeneral,
867 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
868 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
869 "orc $rA, $rS, $rB", IntGeneral,
870 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
871 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
872 "eqv $rA, $rS, $rB", IntGeneral,
873 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
874 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
875 "xor $rA, $rS, $rB", IntGeneral,
876 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
877 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
878 "slw $rA, $rS, $rB", IntGeneral,
879 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
880 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
881 "srw $rA, $rS, $rB", IntGeneral,
882 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
883 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
884 "sraw $rA, $rS, $rB", IntShift,
885 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
888 let PPC970_Unit = 1 in { // FXU Operations.
889 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
890 "srawi $rA, $rS, $SH", IntShift,
891 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
892 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
893 "cntlzw $rA, $rS", IntGeneral,
894 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
895 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
896 "extsb $rA, $rS", IntGeneral,
897 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
898 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
899 "extsh $rA, $rS", IntGeneral,
900 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
902 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
903 "cmpw $crD, $rA, $rB", IntCompare>;
904 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
905 "cmplw $crD, $rA, $rB", IntCompare>;
907 let PPC970_Unit = 3 in { // FPU Operations.
908 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
909 // "fcmpo $crD, $fA, $fB", FPCompare>;
910 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
911 "fcmpu $crD, $fA, $fB", FPCompare>;
912 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
913 "fcmpu $crD, $fA, $fB", FPCompare>;
915 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
916 "fctiwz $frD, $frB", FPGeneral,
917 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
918 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
919 "frsp $frD, $frB", FPGeneral,
920 [(set F4RC:$frD, (fround F8RC:$frB))]>;
921 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
922 "fsqrt $frD, $frB", FPSqrt,
923 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
924 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
925 "fsqrts $frD, $frB", FPSqrt,
926 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
929 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
931 /// Note that these are defined as pseudo-ops on the PPC970 because they are
932 /// often coalesced away and we don't want the dispatch group builder to think
933 /// that they will fill slots (which could cause the load of a LSU reject to
934 /// sneak into a d-group with a store).
935 def FMRS : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
936 "fmr $frD, $frB", FPGeneral,
937 []>, // (set F4RC:$frD, F4RC:$frB)
939 def FMRD : XForm_26<63, 72, (outs F8RC:$frD), (ins F8RC:$frB),
940 "fmr $frD, $frB", FPGeneral,
941 []>, // (set F8RC:$frD, F8RC:$frB)
943 def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB),
944 "fmr $frD, $frB", FPGeneral,
945 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
948 let PPC970_Unit = 3 in { // FPU Operations.
949 // These are artificially split into two different forms, for 4/8 byte FP.
950 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
951 "fabs $frD, $frB", FPGeneral,
952 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
953 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
954 "fabs $frD, $frB", FPGeneral,
955 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
956 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
957 "fnabs $frD, $frB", FPGeneral,
958 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
959 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
960 "fnabs $frD, $frB", FPGeneral,
961 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
962 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
963 "fneg $frD, $frB", FPGeneral,
964 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
965 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
966 "fneg $frD, $frB", FPGeneral,
967 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
971 // XL-Form instructions. condition register logical ops.
973 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
974 "mcrf $BF, $BFA", BrMCR>,
975 PPC970_DGroup_First, PPC970_Unit_CRU;
977 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
978 (ins CRBITRC:$CRA, CRBITRC:$CRB),
979 "creqv $CRD, $CRA, $CRB", BrCR,
982 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
983 (ins CRBITRC:$CRA, CRBITRC:$CRB),
984 "cror $CRD, $CRA, $CRB", BrCR,
987 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
988 "creqv $dst, $dst, $dst", BrCR,
991 // XFX-Form instructions. Instructions that deal with SPRs.
993 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
994 "mfctr $rT", SprMFSPR>,
995 PPC970_DGroup_First, PPC970_Unit_FXU;
996 let Pattern = [(PPCmtctr GPRC:$rS)] in {
997 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
998 "mtctr $rS", SprMTSPR>,
999 PPC970_DGroup_First, PPC970_Unit_FXU;
1002 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1003 "mtlr $rS", SprMTSPR>,
1004 PPC970_DGroup_First, PPC970_Unit_FXU;
1005 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1006 "mflr $rT", SprMFSPR>,
1007 PPC970_DGroup_First, PPC970_Unit_FXU;
1009 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1010 // a GPR on the PPC970. As such, copies in and out have the same performance
1011 // characteristics as an OR instruction.
1012 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1013 "mtspr 256, $rS", IntGeneral>,
1014 PPC970_DGroup_Single, PPC970_Unit_FXU;
1015 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1016 "mfspr $rT, 256", IntGeneral>,
1017 PPC970_DGroup_First, PPC970_Unit_FXU;
1019 def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
1020 "mtcrf $FXM, $rS", BrMCRX>,
1021 PPC970_MicroCode, PPC970_Unit_CRU;
1022 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), "mfcr $rT", SprMFCR>,
1023 PPC970_MicroCode, PPC970_Unit_CRU;
1024 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1025 "mfcr $rT, $FXM", SprMFCR>,
1026 PPC970_DGroup_First, PPC970_Unit_CRU;
1028 // Instructions to manipulate FPSCR. Only long double handling uses these.
1029 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1031 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1032 "mffs $rT", IntMFFS,
1033 [(set F8RC:$rT, (PPCmffs))]>,
1034 PPC970_DGroup_Single, PPC970_Unit_FPU;
1035 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1036 "mtfsb0 $FM", IntMTFSB0,
1037 [(PPCmtfsb0 (i32 imm:$FM))]>,
1038 PPC970_DGroup_Single, PPC970_Unit_FPU;
1039 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1040 "mtfsb1 $FM", IntMTFSB0,
1041 [(PPCmtfsb1 (i32 imm:$FM))]>,
1042 PPC970_DGroup_Single, PPC970_Unit_FPU;
1043 def FADDrtz: AForm_2<63, 21,
1044 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1045 "fadd $FRT, $FRA, $FRB", FPGeneral,
1046 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
1047 PPC970_DGroup_Single, PPC970_Unit_FPU;
1048 // MTFSF does not actually produce an FP result. We pretend it copies
1049 // input reg B to the output. If we didn't do this it would look like the
1050 // instruction had no outputs (because we aren't modelling the FPSCR) and
1051 // it would be deleted.
1052 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
1053 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
1054 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
1055 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
1056 F8RC:$rT, F8RC:$FRB))]>,
1057 PPC970_DGroup_Single, PPC970_Unit_FPU;
1059 let PPC970_Unit = 1 in { // FXU Operations.
1061 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1063 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1064 "add $rT, $rA, $rB", IntGeneral,
1065 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
1066 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1067 "addc $rT, $rA, $rB", IntGeneral,
1068 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
1069 PPC970_DGroup_Cracked;
1070 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1071 "adde $rT, $rA, $rB", IntGeneral,
1072 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
1073 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1074 "divw $rT, $rA, $rB", IntDivW,
1075 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
1076 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1077 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1078 "divwu $rT, $rA, $rB", IntDivW,
1079 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
1080 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1081 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1082 "mulhw $rT, $rA, $rB", IntMulHW,
1083 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
1084 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1085 "mulhwu $rT, $rA, $rB", IntMulHWU,
1086 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
1087 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1088 "mullw $rT, $rA, $rB", IntMulHW,
1089 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
1090 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1091 "subf $rT, $rA, $rB", IntGeneral,
1092 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
1093 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1094 "subfc $rT, $rA, $rB", IntGeneral,
1095 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
1096 PPC970_DGroup_Cracked;
1097 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1098 "subfe $rT, $rA, $rB", IntGeneral,
1099 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
1100 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1101 "addme $rT, $rA", IntGeneral,
1102 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
1103 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1104 "addze $rT, $rA", IntGeneral,
1105 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
1106 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1107 "neg $rT, $rA", IntGeneral,
1108 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
1109 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1110 "subfme $rT, $rA", IntGeneral,
1111 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
1112 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1113 "subfze $rT, $rA", IntGeneral,
1114 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
1117 // A-Form instructions. Most of the instructions executed in the FPU are of
1120 let PPC970_Unit = 3 in { // FPU Operations.
1121 def FMADD : AForm_1<63, 29,
1122 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1123 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1124 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1126 Requires<[FPContractions]>;
1127 def FMADDS : AForm_1<59, 29,
1128 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1129 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1130 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1132 Requires<[FPContractions]>;
1133 def FMSUB : AForm_1<63, 28,
1134 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1135 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1136 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1138 Requires<[FPContractions]>;
1139 def FMSUBS : AForm_1<59, 28,
1140 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1141 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1142 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1144 Requires<[FPContractions]>;
1145 def FNMADD : AForm_1<63, 31,
1146 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1147 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1148 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1150 Requires<[FPContractions]>;
1151 def FNMADDS : AForm_1<59, 31,
1152 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1153 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1154 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1156 Requires<[FPContractions]>;
1157 def FNMSUB : AForm_1<63, 30,
1158 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1159 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1160 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1162 Requires<[FPContractions]>;
1163 def FNMSUBS : AForm_1<59, 30,
1164 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1165 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1166 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1168 Requires<[FPContractions]>;
1169 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1170 // having 4 of these, force the comparison to always be an 8-byte double (code
1171 // should use an FMRSD if the input comparison value really wants to be a float)
1172 // and 4/8 byte forms for the result and operand type..
1173 def FSELD : AForm_1<63, 23,
1174 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1175 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1176 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1177 def FSELS : AForm_1<63, 23,
1178 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1179 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1180 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1181 def FADD : AForm_2<63, 21,
1182 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1183 "fadd $FRT, $FRA, $FRB", FPGeneral,
1184 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1185 def FADDS : AForm_2<59, 21,
1186 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1187 "fadds $FRT, $FRA, $FRB", FPGeneral,
1188 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1189 def FDIV : AForm_2<63, 18,
1190 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1191 "fdiv $FRT, $FRA, $FRB", FPDivD,
1192 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1193 def FDIVS : AForm_2<59, 18,
1194 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1195 "fdivs $FRT, $FRA, $FRB", FPDivS,
1196 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1197 def FMUL : AForm_3<63, 25,
1198 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1199 "fmul $FRT, $FRA, $FRB", FPFused,
1200 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1201 def FMULS : AForm_3<59, 25,
1202 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1203 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1204 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1205 def FSUB : AForm_2<63, 20,
1206 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1207 "fsub $FRT, $FRA, $FRB", FPGeneral,
1208 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1209 def FSUBS : AForm_2<59, 20,
1210 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1211 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1212 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1215 let PPC970_Unit = 1 in { // FXU Operations.
1216 // M-Form instructions. rotate and mask instructions.
1218 let isCommutable = 1 in {
1219 // RLWIMI can be commuted if the rotate amount is zero.
1220 def RLWIMI : MForm_2<20,
1221 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1222 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1223 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1226 def RLWINM : MForm_2<21,
1227 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1228 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1230 def RLWINMo : MForm_2<21,
1231 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1232 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1233 []>, isDOT, PPC970_DGroup_Cracked;
1234 def RLWNM : MForm_2<23,
1235 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1236 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1241 //===----------------------------------------------------------------------===//
1242 // DWARF Pseudo Instructions
1245 def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
1246 "${:comment} .loc $file, $line, $col",
1247 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
1250 //===----------------------------------------------------------------------===//
1251 // PowerPC Instruction Patterns
1254 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1255 def : Pat<(i32 imm:$imm),
1256 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1258 // Implement the 'not' operation with the NOR instruction.
1259 def NOT : Pat<(not GPRC:$in),
1260 (NOR GPRC:$in, GPRC:$in)>;
1262 // ADD an arbitrary immediate.
1263 def : Pat<(add GPRC:$in, imm:$imm),
1264 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1265 // OR an arbitrary immediate.
1266 def : Pat<(or GPRC:$in, imm:$imm),
1267 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1268 // XOR an arbitrary immediate.
1269 def : Pat<(xor GPRC:$in, imm:$imm),
1270 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1272 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1273 (SUBFIC GPRC:$in, imm:$imm)>;
1276 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1277 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1278 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1279 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1282 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1283 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1284 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1285 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1288 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1289 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1292 def : Pat<(PPCcall_Macho (i32 tglobaladdr:$dst)),
1293 (BL_Macho tglobaladdr:$dst)>;
1294 def : Pat<(PPCcall_Macho (i32 texternalsym:$dst)),
1295 (BL_Macho texternalsym:$dst)>;
1296 def : Pat<(PPCcall_ELF (i32 tglobaladdr:$dst)),
1297 (BL_ELF tglobaladdr:$dst)>;
1298 def : Pat<(PPCcall_ELF (i32 texternalsym:$dst)),
1299 (BL_ELF texternalsym:$dst)>;
1302 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1303 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1305 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1306 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1308 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1309 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1313 // Hi and Lo for Darwin Global Addresses.
1314 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1315 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1316 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1317 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1318 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1319 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1320 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1321 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1322 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1323 (ADDIS GPRC:$in, tconstpool:$g)>;
1324 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1325 (ADDIS GPRC:$in, tjumptable:$g)>;
1327 // Fused negative multiply subtract, alternate pattern
1328 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1329 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1330 Requires<[FPContractions]>;
1331 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1332 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1333 Requires<[FPContractions]>;
1335 // Standard shifts. These are represented separately from the real shifts above
1336 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1338 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1339 (SRAW GPRC:$rS, GPRC:$rB)>;
1340 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1341 (SRW GPRC:$rS, GPRC:$rB)>;
1342 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1343 (SLW GPRC:$rS, GPRC:$rB)>;
1345 def : Pat<(zextloadi1 iaddr:$src),
1347 def : Pat<(zextloadi1 xaddr:$src),
1349 def : Pat<(extloadi1 iaddr:$src),
1351 def : Pat<(extloadi1 xaddr:$src),
1353 def : Pat<(extloadi8 iaddr:$src),
1355 def : Pat<(extloadi8 xaddr:$src),
1357 def : Pat<(extloadi16 iaddr:$src),
1359 def : Pat<(extloadi16 xaddr:$src),
1361 def : Pat<(extloadf32 iaddr:$src),
1362 (FMRSD (LFS iaddr:$src))>;
1363 def : Pat<(extloadf32 xaddr:$src),
1364 (FMRSD (LFSX xaddr:$src))>;
1367 def : Pat<(membarrier (i32 imm:$ll),
1374 include "PPCInstrAltivec.td"
1375 include "PPCInstr64Bit.td"