1 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PowerPCInstrFormats.td"
17 let isTerminator = 1, isReturn = 1 in
18 def BLR : XLForm_2_ext<19, 16, 20, 31, 1, 0, 0, (ops), "blr">;
20 def u5imm : Operand<i8> {
21 let PrintMethod = "printU5ImmOperand";
23 def u6imm : Operand<i8> {
24 let PrintMethod = "printU6ImmOperand";
26 def s16imm : Operand<i16> {
27 let PrintMethod = "printS16ImmOperand";
29 def u16imm : Operand<i16> {
30 let PrintMethod = "printU16ImmOperand";
32 def target : Operand<i32> {
33 let PrintMethod = "printBranchOperand";
35 def piclabel: Operand<i32> {
36 let PrintMethod = "printPICLabel";
38 def symbolHi: Operand<i32> {
39 let PrintMethod = "printSymbolHi";
41 def symbolLo: Operand<i32> {
42 let PrintMethod = "printSymbolLo";
45 // Pseudo-instructions:
46 def PHI : Pseudo<(ops), "; PHI">;
48 def ADJCALLSTACKDOWN : Pseudo<(ops), "; ADJCALLSTACKDOWN">;
49 def ADJCALLSTACKUP : Pseudo<(ops), "; ADJCALLSTACKUP">;
51 def IMPLICIT_DEF : Pseudo<(ops), "; IMPLICIT_DEF">;
52 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
54 let isBranch = 1, isTerminator = 1 in {
55 def COND_BRANCH : Pseudo<(ops), "; COND_BRANCH">;
56 def B : IForm<18, 0, 0, 0, 0, (ops target:$func), "b $func">;
57 // FIXME: 4*CR# needs to be added to the BI field!
58 // This will only work for CR0 as it stands now
59 def BLT : BForm_ext<16, 0, 0, 12, 0, 0, 0, (ops CRRC:$crS, target:$block),
61 def BLE : BForm_ext<16, 0, 0, 4, 1, 0, 0, (ops CRRC:$crS, target:$block),
63 def BEQ : BForm_ext<16, 0, 0, 12, 2, 0, 0, (ops CRRC:$crS, target:$block),
65 def BGE : BForm_ext<16, 0, 0, 4, 0, 0, 0, (ops CRRC:$crS, target:$block),
67 def BGT : BForm_ext<16, 0, 0, 12, 1, 0, 0, (ops CRRC:$crS, target:$block),
69 def BNE : BForm_ext<16, 0, 0, 4, 2, 0, 0, (ops CRRC:$crS, target:$block),
73 let isBranch = 1, isTerminator = 1, isCall = 1,
74 // All calls clobber the non-callee saved registers...
75 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
76 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
78 CR0,CR1,CR5,CR6,CR7] in {
79 // Convenient aliases for call instructions
80 def CALLpcrel : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
81 def CALLindirect : XLForm_2_ext<19, 528, 20, 31, 1, 0, 0, (ops), "bctrl">;
84 // D-Form instructions. Most instructions that perform an operation on a
85 // register and an immediate are of this type.
88 def LBZ : DForm_1<35, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
89 "lbz $rD, $disp($rA)">;
90 def LHA : DForm_1<42, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
91 "lha $rD, $disp($rA)">;
92 def LHZ : DForm_1<40, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
93 "lhz $rD, $disp($rA)">;
94 def LMW : DForm_1<46, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
95 "lmw $rD, $disp($rA)">;
96 def LWZ : DForm_1<32, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
97 "lwz $rD, $disp($rA)">;
99 def ADDI : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
100 "addi $rD, $rA, $imm">;
101 def ADDIC : DForm_2<12, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
102 "addic $rD, $rA, $imm">;
103 def ADDICo : DForm_2<13, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
104 "addic. $rD, $rA, $imm">;
105 def ADDIS : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
106 "addis $rD, $rA, $imm">;
107 def LA : DForm_2<14, 0, 0, (ops GPRC:$rD, symbolLo:$sym, GPRC:$rA),
108 "la $rD, $sym($rA)">;
109 def LOADHiAddr : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolHi:$sym),
110 "addis $rD, $rA, $sym">;
111 def MULLI : DForm_2< 7, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
112 "mulli $rD, $rA, $imm">;
113 def SUBFIC : DForm_2< 8, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
114 "subfic $rD, $rA, $imm">;
115 def LI : DForm_2_r0<14, 0, 0, (ops GPRC:$rD, s16imm:$imm),
117 def LIS : DForm_2_r0<15, 0, 0, (ops GPRC:$rD, s16imm:$imm),
120 def STMW : DForm_3<47, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
121 "stmw $rS, $disp($rA)">;
122 def STB : DForm_3<38, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
123 "stb $rS, $disp($rA)">;
124 def STBU : DForm_3<39, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
125 "stbu $rS, $disp($rA)">;
126 def STH : DForm_3<44, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
127 "sth $rS, $disp($rA)">;
128 def STHU : DForm_3<45, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
129 "sthu $rS, $disp($rA)">;
130 def STW : DForm_3<36, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
131 "stw $rS, $disp($rA)">;
132 def STWU : DForm_3<37, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
133 "stwu $rS, $disp($rA)">;
135 def ANDIo : DForm_4<28, 0, 0,
136 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
137 "andi. $dst, $src1, $src2">;
138 def ANDISo : DForm_4<29, 0, 0,
139 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
140 "andis. $dst, $src1, $src2">;
141 def ORI : DForm_4<24, 0, 0,
142 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
143 "ori $dst, $src1, $src2">;
144 def ORIS : DForm_4<25, 0, 0,
145 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
146 "oris $dst, $src1, $src2">;
147 def XORI : DForm_4<26, 0, 0,
148 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
149 "xori $dst, $src1, $src2">;
150 def XORIS : DForm_4<27, 0, 0,
151 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
152 "xoris $dst, $src1, $src2">;
153 def NOP : DForm_4_zero<24, 0, 0, (ops), "nop">;
154 def CMPI : DForm_5<11, 0, 0, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
155 "cmpi $crD, $L, $rA, $imm">;
156 def CMPWI : DForm_5_ext<11, 0, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
157 "cmpwi $crD, $rA, $imm">;
158 def CMPDI : DForm_5_ext<11, 1, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
159 "cmpdi $crD, $rA, $imm">;
160 def CMPLI : DForm_6<10, 0, 0,
161 (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
162 "cmpli $dst, $size, $src1, $src2">;
163 def CMPLWI : DForm_6_ext<10, 0, 0,
164 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
165 "cmplwi $dst, $src1, $src2">;
166 def CMPLDI : DForm_6_ext<10, 1, 0,
167 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
168 "cmpldi $dst, $src1, $src2">;
170 def LFS : DForm_8<48, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
171 "lfs $rD, $disp($rA)">;
172 def LFD : DForm_8<50, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
173 "lfd $rD, $disp($rA)">;
176 def STFS : DForm_9<52, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
177 "stfs $rS, $disp($rA)">;
178 def STFD : DForm_9<54, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
179 "stfd $rS, $disp($rA)">;
182 // DS-Form instructions. Load/Store instructions available in PPC-64
185 def LWA : DSForm_1<58, 2, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
186 "lwa $rT, $DS($rA)">;
187 def LD : DSForm_2<58, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
191 def STD : DSForm_2<62, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
192 "std $rT, $DS($rA)">;
193 def STDU : DSForm_2<62, 1, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
194 "stdu $rT, $DS($rA)">;
197 // X-Form instructions. Most instructions that perform an operation on a
198 // register and another register are of this type.
201 def LBZX : XForm_1<31, 87, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
202 "lbzx $dst, $base, $index">;
203 def LHAX : XForm_1<31, 343, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
204 "lhax $dst, $base, $index">;
205 def LHZX : XForm_1<31, 279, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
206 "lhzx $dst, $base, $index">;
207 def LWAX : XForm_1<31, 341, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
208 "lwax $dst, $base, $index">;
209 def LWZX : XForm_1<31, 23, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
210 "lwzx $dst, $base, $index">;
211 def LDX : XForm_1<31, 21, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
212 "ldx $dst, $base, $index">;
214 def MFCR : XForm_5<31, 19, 0, 0, (ops GPRC:$dst), "mfcr $dst">;
215 def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
216 "and $rA, $rS, $rB">;
217 def ANDC : XForm_6<31, 60, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
218 "andc $rA, $rS, $rB">;
219 def EQV : XForm_6<31, 284, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
220 "eqv $rA, $rS, $rB">;
221 def NAND : XForm_6<31, 476, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
222 "nand $rA, $rS, $rB">;
223 def NOR : XForm_6<31, 124, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
224 "nor $rA, $rS, $rB">;
225 def OR : XForm_6<31, 444, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
227 def ORo : XForm_6<31, 444, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
228 "or. $rA, $rS, $rB">;
229 def ORC : XForm_6<31, 412, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
230 "orc $rA, $rS, $rB">;
231 def SLD : XForm_6<31, 27, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
232 "sld $rA, $rS, $rB">;
233 def SLW : XForm_6<31, 24, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
234 "slw $rA, $rS, $rB">;
235 def SRD : XForm_6<31, 539, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
236 "srd $rA, $rS, $rB">;
237 def SRW : XForm_6<31, 536, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
238 "srw $rA, $rS, $rB">;
239 def SRAD : XForm_6<31, 794, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
240 "srad $rA, $rS, $rB">;
241 def SRAW : XForm_6<31, 792, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
242 "sraw $rA, $rS, $rB">;
243 def XOR : XForm_6<31, 316, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
244 "xor $rA, $rS, $rB">;
246 def STBX : XForm_8<31, 215, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
247 "stbx $rS, $rA, $rB">;
248 def STHX : XForm_8<31, 407, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
249 "sthx $rS, $rA, $rB">;
250 def STWX : XForm_8<31, 151, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
251 "stwx $rS, $rA, $rB">;
252 def STWUX : XForm_8<31, 183, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
253 "stwux $rS, $rA, $rB">;
254 def STDX : XForm_8<31, 149, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
255 "stdx $rS, $rA, $rB">;
256 def STDUX : XForm_8<31, 181, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
257 "stdux $rS, $rA, $rB">;
259 def SRAWI : XForm_10<31, 824, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
260 "srawi $rA, $rS, $SH">;
261 def CNTLZW : XForm_11<31, 26, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
263 def EXTSB : XForm_11<31, 954, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
265 def EXTSH : XForm_11<31, 922, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
267 def EXTSW : XForm_11<31, 986, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS),
269 def CMP : XForm_16<31, 0, 0, 0,
270 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
271 "cmp $crD, $long, $rA, $rB">;
272 def CMPL : XForm_16<31, 32, 0, 0,
273 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
274 "cmpl $crD, $long, $rA, $rB">;
275 def CMPW : XForm_16_ext<31, 0, 0, 0,
276 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
277 "cmpw $crD, $rA, $rB">;
278 def CMPD : XForm_16_ext<31, 0, 1, 0,
279 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
280 "cmpd $crD, $rA, $rB">;
281 def CMPLW : XForm_16_ext<31, 32, 0, 0,
282 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
283 "cmplw $crD, $rA, $rB">;
284 def CMPLD : XForm_16_ext<31, 32, 1, 0,
285 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
286 "cmpld $crD, $rA, $rB">;
287 def FCMPU : XForm_17<63, 0, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
288 "fcmpu $crD, $fA, $fB">;
290 def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
291 "lfsx $dst, $base, $index">;
292 def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
293 "lfdx $dst, $base, $index">;
295 def FCFID : XForm_26<63, 846, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
297 def FCTIDZ : XForm_26<63, 815, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
298 "fctidz $frD, $frB">;
299 def FCTIWZ : XForm_26<63, 15, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
300 "fctiwz $frD, $frB">;
301 def FMR : XForm_26<63, 72, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
303 def FNEG : XForm_26<63, 80, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
305 def FRSP : XForm_26<63, 12, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
308 def STFSX : XForm_28<31, 663, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
309 "stfsx $frS, $rA, $rB">;
310 def STFDX : XForm_28<31, 727, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
311 "stfdx $frS, $rA, $rB">;
314 // XL-Form instructions. condition register logical ops.
316 def CRAND : XLForm_1<19, 257, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
318 def CRANDC : XLForm_1<19, 129, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
319 "crandc $D, $A, $B">;
320 def CRNOR : XLForm_1<19, 33, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
322 def CROR : XLForm_1<19, 449, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
325 // XFX-Form instructions. Instructions that deal with SPRs
327 def MFCTR : XFXForm_1_ext<31, 399, 9, 0, 0, (ops GPRC:$rT), "mfctr $rT">;
328 def MFLR : XFXForm_1_ext<31, 399, 8, 0, 0, (ops GPRC:$rT), "mflr $rT">;
329 def MTCTR : XFXForm_7_ext<31, 467, 9, 0, 0, (ops GPRC:$rS), "mtctr $rS">;
330 def MTLR : XFXForm_7_ext<31, 467, 8, 0, 0, (ops GPRC:$rS), "mtlr $rS">;
333 // XS-Form instructions. Just 'sradi'
335 def SRADI : XSForm_1<31, 413, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
336 "sradi $rA, $rS, $SH">;
338 // XO-Form instructions. Arithmetic instructions that can set overflow bit
340 def ADD : XOForm_1<31, 266, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
341 "add $rT, $rA, $rB">;
342 def ADDC : XOForm_1<31, 10, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
343 "addc $rT, $rA, $rB">;
344 def ADDE : XOForm_1<31, 138, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
345 "adde $rT, $rA, $rB">;
346 def DIVD : XOForm_1<31, 489, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
347 "divd $rT, $rA, $rB">;
348 def DIVDU : XOForm_1<31, 457, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
349 "divdu $rT, $rA, $rB">;
350 def DIVW : XOForm_1<31, 491, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
351 "divw $rT, $rA, $rB">;
352 def DIVWU : XOForm_1<31, 459, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
353 "divwu $rT, $rA, $rB">;
354 def MULHWU : XOForm_1<31, 11, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
355 "mulhwu $rT, $rA, $rB">;
356 def MULLD : XOForm_1<31, 233, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
357 "mulld $rT, $rA, $rB">;
358 def MULLW : XOForm_1<31, 235, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
359 "mullw $rT, $rA, $rB">;
360 def SUBF : XOForm_1<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
361 "subf $rT, $rA, $rB">;
362 def SUBFC : XOForm_1<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
363 "subfc $rT, $rA, $rB">;
364 def SUBFE : XOForm_1<31, 136, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
365 "subfe $rT, $rA, $rB">;
366 def SUB : XOForm_1r<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
367 "sub $rT, $rA, $rB">;
368 def SUBC : XOForm_1r<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
369 "subc $rT, $rA, $rB">;
370 def ADDME : XOForm_3<31, 234, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
372 def ADDZE : XOForm_3<31, 202, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
374 def NEG : XOForm_3<31, 104, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
376 def SUBFZE : XOForm_3<31, 200, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
379 // A-Form instructions. Most of the instructions executed in the FPU are of
382 def FMADD : AForm_1<63, 29, 0, 0, 0,
383 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
384 "fmadd $FRT, $FRA, $FRC, $FRB">;
385 def FSEL : AForm_1<63, 23, 0, 0, 0,
386 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
387 "fsel $FRT, $FRA, $FRC, $FRB">;
388 def FADD : AForm_2<63, 21, 0, 0, 0,
389 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
390 "fadd $FRT, $FRA, $FRB">;
391 def FADDS : AForm_2<59, 21, 0, 0, 0,
392 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
393 "fadds $FRT, $FRA, $FRB">;
394 def FDIV : AForm_2<63, 18, 0, 0, 0,
395 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
396 "fdiv $FRT, $FRA, $FRB">;
397 def FDIVS : AForm_2<59, 18, 0, 0, 0,
398 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
399 "fdivs $FRT, $FRA, $FRB">;
400 def FMUL : AForm_3<63, 25, 0, 0, 0,
401 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
402 "fmul $FRT, $FRA, $FRB">;
403 def FMULS : AForm_3<59, 25, 0, 0, 0,
404 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
405 "fmuls $FRT, $FRA, $FRB">;
406 def FSUB : AForm_2<63, 20, 0, 0, 0,
407 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
408 "fsub $FRT, $FRA, $FRB">;
409 def FSUBS : AForm_2<59, 20, 0, 0, 0,
410 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
411 "fsubs $FRT, $FRA, $FRB">;
413 // M-Form instructions. rotate and mask instructions.
415 def RLWIMI : MForm_2<20, 0, 0, 0,
416 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
417 "rlwimi $rA, $rS, $SH, $MB, $ME">;
418 def RLWINM : MForm_2<21, 0, 0, 0,
419 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
420 "rlwinm $rA, $rS, $SH, $MB, $ME">;
423 // MD-Form instructions. 64 bit rotate instructions.
425 def RLDICL : MDForm_1<30, 0, 0, 1, 0,
426 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
427 "rldicl $rA, $rS, $SH, $MB">;
428 def RLDICR : MDForm_1<30, 1, 0, 1, 0,
429 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
430 "rldicr $rA, $rS, $SH, $ME">;