1 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PowerPCInstrFormats.td"
17 let isTerminator = 1, isReturn = 1 in
18 def BLR : XLForm_2_ext<19, 16, 20, 31, 1, 0, 0, (ops), "blr">;
20 def u5imm : Operand<i8> {
21 let PrintMethod = "printU5ImmOperand";
23 def u6imm : Operand<i8> {
24 let PrintMethod = "printU6ImmOperand";
26 def u16imm : Operand<i16> {
27 let PrintMethod = "printU16ImmOperand";
29 def target : Operand<i32> {
30 let PrintMethod = "printBranchOperand";
32 def piclabel: Operand<i32> {
33 let PrintMethod = "printPICLabel";
36 // Pseudo-instructions:
37 def PHI : Pseudo<(ops), "; PHI">;
38 def ADJCALLSTACKDOWN : Pseudo<(ops), "; ADJCALLSTACKDOWN">;
39 def ADJCALLSTACKUP : Pseudo<(ops), "; ADJCALLSTACKUP">;
40 def IMPLICIT_DEF : Pseudo<(ops), "; IMPLICIT_DEF">;
41 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
43 let isBranch = 1, isTerminator = 1 in {
44 def COND_BRANCH : Pseudo<(ops), "; COND_BRANCH">;
45 def B : IForm<18, 0, 0, 0, 0, (ops target:$func), "b $func">;
46 // FIXME: 4*CR# needs to be added to the BI field!
47 // This will only work for CR0 as it stands now
48 def BLT : BForm_ext<"blt", 16, 0, 0, 12, 0, 0, 0>;
49 def BLE : BForm_ext<"ble", 16, 0, 0, 4, 1, 0, 0>;
50 def BEQ : BForm_ext<"beq", 16, 0, 0, 12, 2, 0, 0>;
51 def BGE : BForm_ext<"bge", 16, 0, 0, 4, 0, 0, 0>;
52 def BGT : BForm_ext<"bgt", 16, 0, 0, 12, 1, 0, 0>;
53 def BNE : BForm_ext<"bne", 16, 0, 0, 4, 2, 0, 0>;
56 let isBranch = 1, isTerminator = 1, isCall = 1,
57 // All calls clobber the non-callee saved registers...
58 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
59 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
61 CR0,CR1,CR5,CR6,CR7] in {
62 // Convenient aliases for call instructions
63 def CALLpcrel : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
64 def CALLindirect : XLForm_2_ext<19, 528, 20, 31, 1, 0, 0, (ops), "bctrl">;
67 def LA : DForm_2<"la", 14, 0, 0>;
68 def LOADHiAddr : DForm_2_r0<"addis", 15, 0, 0>;
70 def LBZ : DForm_1<"lbz", 35, 0, 0>;
71 def LHA : DForm_1<"lha", 42, 0, 0>;
72 def LHZ : DForm_1<"lhz", 40, 0, 0>;
73 def LMW : DForm_1<"lmw", 46, 0, 0>;
74 def LWZ : DForm_1<"lwz", 32, 0, 0>;
75 def ADDI : DForm_2<"addi", 14, 0, 0>;
76 def ADDIC : DForm_2<"addic", 12, 0, 0>;
77 def ADDICo : DForm_2<"addic.", 13, 0, 0>;
78 def ADDIS : DForm_2<"addis", 15, 0, 0>;
79 def MULLI : DForm_2<"mulli", 7, 0, 0>;
80 def SUBFIC : DForm_2<"subfic", 8, 0, 0>;
81 def SUBI : DForm_2<"subi", 14, 0, 0>;
82 def LI : DForm_2_r0<"li", 14, 0, 0>;
83 def LIS : DForm_2_r0<"lis", 15, 0, 0>;
84 def STMW : DForm_3<"stmw", 47, 0, 0>;
85 def STB : DForm_3<"stb", 38, 0, 0>;
86 def STBU : DForm_3<"stbu", 39, 0, 0>;
87 def STH : DForm_3<"sth", 44, 0, 0>;
88 def STHU : DForm_3<"sthu", 45, 0, 0>;
89 def STW : DForm_3<"stw", 36, 0, 0>;
90 def STWU : DForm_3<"stwu", 37, 0, 0>;
91 def CMPI : DForm_5<"cmpi", 11, 0, 0>;
92 def CMPWI : DForm_5_ext<"cmpwi", 11, 0, 0>;
93 def CMPDI : DForm_5_ext<"cmpdi", 11, 1, 0>;
94 def LFS : DForm_8<"lfs", 48, 0, 0>;
95 def LFD : DForm_8<"lfd", 50, 0, 0>;
96 def STFS : DForm_9<"stfs", 52, 0, 0>;
97 def STFD : DForm_9<"stfd", 54, 0, 0>;
99 def LWA : DSForm_1<"lwa", 58, 2, 1, 0>;
100 def LD : DSForm_2<"ld", 58, 0, 1, 0>;
101 def STD : DSForm_2<"std", 62, 0, 1, 0>;
102 def STDU : DSForm_2<"stdu", 62, 1, 1, 0>;
104 // D-Form instructions. Most instructions that perform an operation on a
105 // register and an immediate are of this type.
107 def ANDIo : DForm_4<28, 0, 0,
108 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
109 "andi. $dst, $src1, $src2">;
110 def ORI : DForm_4<24, 0, 0,
111 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
112 "ori $dst, $src1, $src2">;
113 def ORIS : DForm_4<25, 0, 0,
114 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
115 "oris $dst, $src1, $src2">;
116 def XORI : DForm_4<26, 0, 0,
117 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
118 "xori $dst, $src1, $src2">;
119 def XORIS : DForm_4<27, 0, 0,
120 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
121 "xoris $dst, $src1, $src2">;
122 def NOP : DForm_4_zero<"nop", 24, 0, 0, (ops), "nop">;
123 def CMPLI : DForm_6<10, 0, 0,
124 (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
125 "cmpli $dst, $size, $src1, $src2">;
126 def CMPLWI : DForm_6_ext<10, 0, 0,
127 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
128 "cmplwi $dst, $src1, $src2">;
129 def CMPLDI : DForm_6_ext<10, 1, 0,
130 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
131 "cmpldi $dst, $src1, $src2">;
133 // X-Form instructions. Most instructions that perform an operation on a
134 // register and another register are of this type.
136 def LBZX : XForm_1<31, 87, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
137 "lbzx $dst, $base, $index">;
138 def LHAX : XForm_1<31, 343, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
139 "lhax $dst, $base, $index">;
140 def LHZX : XForm_1<31, 279, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
141 "lhzx $dst, $base, $index">;
142 def LWAX : XForm_1<31, 341, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
143 "lwax $dst, $base, $index">;
144 def LWZX : XForm_1<31, 23, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
145 "lwzx $dst, $base, $index">;
146 def LDX : XForm_1<31, 21, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
147 "ldx $dst, $base, $index">;
148 def MFCR : XForm_5<31, 19, 0, 0, (ops GPRC:$dst), "mfcr $dst">;
149 def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
150 "and $rA, $rS, $rB">;
151 def ANDC : XForm_6<31, 60, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
152 "andc $rA, $rS, $rB">;
153 def EQV : XForm_6<31, 284, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
154 "eqv $rA, $rS, $rB">;
155 def NAND : XForm_6<31, 476, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
156 "nand $rA, $rS, $rB">;
157 def NOR : XForm_6<31, 124, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
158 "nor $rA, $rS, $rB">;
159 def OR : XForm_6<31, 444, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
161 def ORo : XForm_6<31, 444, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
162 "or. $rA, $rS, $rB">;
163 def ORC : XForm_6<31, 412, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
164 "orc $rA, $rS, $rB">;
165 def SLD : XForm_6<31, 27, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
166 "sld $rA, $rS, $rB">;
167 def SLW : XForm_6<31, 24, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
168 "slw $rA, $rS, $rB">;
169 def SRD : XForm_6<31, 539, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
170 "srd $rA, $rS, $rB">;
171 def SRW : XForm_6<31, 536, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
172 "srw $rA, $rS, $rB">;
173 def SRAD : XForm_6<31, 794, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
174 "srad $rA, $rS, $rB">;
175 def SRAW : XForm_6<31, 792, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
176 "sraw $rA, $rS, $rB">;
177 def XOR : XForm_6<31, 316, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
178 "xor $rA, $rS, $rB">;
179 def STBX : XForm_8<31, 215, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
180 "stbx $rS, $rA, $rB">;
181 def STHX : XForm_8<31, 407, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
182 "sthx $rS, $rA, $rB">;
183 def STWX : XForm_8<31, 151, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
184 "stwx $rS, $rA, $rB">;
185 def STWUX : XForm_8<31, 183, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
186 "stwux $rS, $rA, $rB">;
187 def STDX : XForm_8<31, 149, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
188 "stdx $rS, $rA, $rB">;
189 def STDUX : XForm_8<31, 181, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
190 "stdux $rS, $rA, $rB">;
191 def SRAWI : XForm_10<31, 824, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
192 "srawi $rA, $rS, $SH">;
193 def CNTLZW : XForm_11<31, 26, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
195 def EXTSB : XForm_11<31, 954, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
197 def EXTSH : XForm_11<31, 922, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
199 def EXTSW : XForm_11<31, 986, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS),
201 def CMP : XForm_16<31, 0, 0, 0,
202 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
203 "cmp $crD, $long, $rA, $rB">;
204 def CMPL : XForm_16<31, 32, 0, 0,
205 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
206 "cmpl $crD, $long, $rA, $rB">;
207 def CMPW : XForm_16_ext<31, 0, 0, 0,
208 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
209 "cmpw $crD, $rA, $rB">;
210 def CMPD : XForm_16_ext<31, 0, 1, 0,
211 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
212 "cmpd $crD, $rA, $rB">;
213 def CMPLW : XForm_16_ext<31, 32, 0, 0,
214 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
215 "cmplw $crD, $rA, $rB">;
216 def CMPLD : XForm_16_ext<31, 32, 1, 0,
217 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
218 "cmpld $crD, $rA, $rB">;
219 def FCMPU : XForm_17<63, 0, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
220 "fcmpu $crD, $fA, $fB">;
221 def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
222 "lfsx $dst, $base, $index">;
223 def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
224 "lfdx $dst, $base, $index">;
225 def FCFID : XForm_26<63, 846, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
227 def FCTIDZ : XForm_26<63, 815, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
228 "fctidz $frD, $frB">;
229 def FCTIWZ : XForm_26<63, 15, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
230 "fctiwz $frD, $frB">;
231 def FMR : XForm_26<63, 72, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
233 def FNEG : XForm_26<63, 80, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
235 def FRSP : XForm_26<63, 12, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
237 def STFSX : XForm_28<31, 663, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
238 "stfsx $frS, $rA, $rB">;
239 def STFDX : XForm_28<31, 727, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
240 "stfdx $frS, $rA, $rB">;
242 // XL-Form instructions. condition register logical ops.
244 def CRAND : XLForm_1<19, 257, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
246 def CRANDC : XLForm_1<19, 129, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
247 "crandc $D, $A, $B">;
248 def CRNOR : XLForm_1<19, 33, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
250 def CROR : XLForm_1<19, 449, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
253 // XFX-Form instructions. Instructions that deal with SPRs
255 def MFCTR : XFXForm_1_ext<31, 399, 9, 0, 0, (ops GPRC:$rT), "mfctr $rT">;
256 def MFLR : XFXForm_1_ext<31, 399, 8, 0, 0, (ops GPRC:$rT), "mflr $rT">;
257 def MTCTR : XFXForm_7_ext<31, 467, 9, 0, 0, (ops GPRC:$rS), "mtctr $rS">;
258 def MTLR : XFXForm_7_ext<31, 467, 8, 0, 0, (ops GPRC:$rS), "mtlr $rS">;
261 // XS-Form instructions. Just 'sradi'
263 def SRADI : XSForm_1<31, 413, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
264 "sradi $rA, $rS, $SH">;
266 // XO-Form instructions. Arithmetic instructions that can set overflow bit
268 def ADD : XOForm_1<31, 266, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
269 "add $rT, $rA, $rB">;
270 def ADDC : XOForm_1<31, 10, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
271 "addc $rT, $rA, $rB">;
272 def ADDE : XOForm_1<31, 138, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
273 "adde $rT, $rA, $rB">;
274 def DIVW : XOForm_1<31, 491, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
275 "divw $rT, $rA, $rB">;
276 def DIVWU : XOForm_1<31, 459, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
277 "divwu $rT, $rA, $rB">;
278 def MULHWU : XOForm_1<31, 11, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
279 "mulhwu $rT, $rA, $rB">;
280 def MULLD : XOForm_1<31, 233, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
281 "mulld $rT, $rA, $rB">;
282 def MULLW : XOForm_1<31, 235, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
283 "mullw $rT, $rA, $rB">;
284 def SUBF : XOForm_1<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
285 "subf $rT, $rA, $rB">;
286 def SUBFC : XOForm_1<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
287 "subfc $rT, $rA, $rB">;
288 def SUBFE : XOForm_1<31, 136, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
289 "subfe $rT, $rA, $rB">;
290 def SUB : XOForm_1r<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
291 "sub $rT, $rA, $rB">;
292 def SUBC : XOForm_1r<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
293 "subc $rT, $rA, $rB">;
294 def ADDZE : XOForm_3<31, 202, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
296 def NEG : XOForm_3<31, 104, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
298 def SUBFZE : XOForm_3<31, 200, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
301 // A-Form instructions. Most of the instructions executed in the FPU are of
304 def FMADD : AForm_1<63, 29, 0, 0, 0,
305 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
306 "fmadd $FRT, $FRA, $FRC, $FRB">;
307 def FSEL : AForm_1<63, 23, 0, 0, 0,
308 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
309 "fsel $FRT, $FRA, $FRC, $FRB">;
310 def FADD : AForm_2<63, 21, 0, 0, 0,
311 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
312 "fadd $FRT, $FRA, $FRB">;
313 def FADDS : AForm_2<59, 21, 0, 0, 0,
314 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
315 "fadds $FRT, $FRA, $FRB">;
316 def FDIV : AForm_2<63, 18, 0, 0, 0,
317 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
318 "fdiv $FRT, $FRA, $FRB">;
319 def FDIVS : AForm_2<59, 18, 0, 0, 0,
320 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
321 "fdivs $FRT, $FRA, $FRB">;
322 def FMUL : AForm_3<63, 25, 0, 0, 0,
323 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
324 "fmul $FRT, $FRA, $FRB">;
325 def FMULS : AForm_3<59, 25, 0, 0, 0,
326 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
327 "fmuls $FRT, $FRA, $FRB">;
328 def FSUB : AForm_2<63, 20, 0, 0, 0,
329 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
330 "fsub $FRT, $FRA, $FRB">;
331 def FSUBS : AForm_2<59, 20, 0, 0, 0,
332 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
333 "fsubs $FRT, $FRA, $FRB">;
335 // M-Form instructions. rotate and mask instructions.
337 def RLWIMI : MForm_2<20, 0, 0, 0,
338 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
339 "rlwimi $rA, $rS, $SH, $MB, $ME">;
340 def RLWINM : MForm_2<21, 0, 0, 0,
341 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
342 "rlwinm $rA, $rS, $SH, $MB, $ME">;
345 // MD-Form instructions. 64 bit rotate instructions.
347 def RLDICL : MDForm_1<30, 0, 0, 1, 0,
348 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
349 "rldicl $rA, $rS, $SH, $MB">;
350 def RLDICR : MDForm_1<30, 1, 0, 1, 0,
351 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
352 "rldicr $rA, $rS, $SH, $ME">;