1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC specific transformation functions and pattern fragments.
22 def SHL32 : SDNodeXForm<imm, [{
23 // Transformation function: 31 - imm
24 return getI32Imm(31 - N->getValue());
27 def SHL64 : SDNodeXForm<imm, [{
28 // Transformation function: 63 - imm
29 return getI32Imm(63 - N->getValue());
32 def SRL32 : SDNodeXForm<imm, [{
33 // Transformation function: 32 - imm
34 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
37 def SRL64 : SDNodeXForm<imm, [{
38 // Transformation function: 64 - imm
39 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
42 def LO16 : SDNodeXForm<imm, [{
43 // Transformation function: get the low 16 bits.
44 return getI32Imm((unsigned short)N->getValue());
47 def HI16 : SDNodeXForm<imm, [{
48 // Transformation function: shift the immediate value down into the low bits.
49 return getI32Imm((unsigned)N->getValue() >> 16);
52 def HA16 : SDNodeXForm<imm, [{
53 // Transformation function: shift the immediate value down into the low bits.
54 signed int Val = N->getValue();
55 return getI32Imm((Val - (signed short)Val) >> 16);
59 def immSExt16 : PatLeaf<(imm), [{
60 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
61 // field. Used by instructions like 'addi'.
62 return (int)N->getValue() == (short)N->getValue();
64 def immZExt16 : PatLeaf<(imm), [{
65 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
66 // field. Used by instructions like 'ori'.
67 return (unsigned)N->getValue() == (unsigned short)N->getValue();
70 def imm16Shifted : PatLeaf<(imm), [{
71 // imm16Shifted predicate - True if only bits in the top 16-bits of the
72 // immediate are set. Used by instructions like 'addis'.
73 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
77 // Example of a legalize expander: Only for PPC64.
78 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
79 [(set f64:$tmp , (FCTIDZ f64:$src)),
80 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
81 (store f64:$tmp, i32:$tmpFI),
82 (set i64:$dst, (load i32:$tmpFI))],
86 //===----------------------------------------------------------------------===//
87 // PowerPC Flag Definitions.
89 class isPPC64 { bit PPC64 = 1; }
90 class isVMX { bit VMX = 1; }
92 list<Register> Defs = [CR0];
98 //===----------------------------------------------------------------------===//
99 // PowerPC Operand Definitions.
101 def u5imm : Operand<i32> {
102 let PrintMethod = "printU5ImmOperand";
104 def u6imm : Operand<i32> {
105 let PrintMethod = "printU6ImmOperand";
107 def s16imm : Operand<i32> {
108 let PrintMethod = "printS16ImmOperand";
110 def u16imm : Operand<i32> {
111 let PrintMethod = "printU16ImmOperand";
113 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
114 let PrintMethod = "printS16X4ImmOperand";
116 def target : Operand<i32> {
117 let PrintMethod = "printBranchOperand";
119 def piclabel: Operand<i32> {
120 let PrintMethod = "printPICLabel";
122 def symbolHi: Operand<i32> {
123 let PrintMethod = "printSymbolHi";
125 def symbolLo: Operand<i32> {
126 let PrintMethod = "printSymbolLo";
128 def crbitm: Operand<i8> {
129 let PrintMethod = "printcrbitm";
134 //===----------------------------------------------------------------------===//
135 // PowerPC Instruction Definitions.
137 // Pseudo-instructions:
138 def PHI : Pseudo<(ops variable_ops), "; PHI">;
141 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN">;
142 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP">;
144 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
145 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8">;
146 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4">;
148 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
149 // scheduler into a branch sequence.
150 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
151 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
152 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
153 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
154 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
155 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
156 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
160 let isTerminator = 1 in {
162 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB>;
163 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB>;
167 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
169 let isBranch = 1, isTerminator = 1 in {
170 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
171 target:$true, target:$false),
173 def B : IForm<18, 0, 0, (ops target:$func), "b $func", BrB>;
174 //def BA : IForm<18, 1, 0, (ops target:$func), "ba $func", BrB>;
175 def BL : IForm<18, 0, 1, (ops target:$func), "bl $func", BrB>;
176 //def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func", BrB>;
178 // FIXME: 4*CR# needs to be added to the BI field!
179 // This will only work for CR0 as it stands now
180 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
181 "blt $crS, $block", BrB>;
182 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
183 "ble $crS, $block", BrB>;
184 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
185 "beq $crS, $block", BrB>;
186 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
187 "bge $crS, $block", BrB>;
188 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
189 "bgt $crS, $block", BrB>;
190 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
191 "bne $crS, $block", BrB>;
195 // All calls clobber the non-callee saved registers...
196 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
197 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
199 CR0,CR1,CR5,CR6,CR7] in {
200 // Convenient aliases for call instructions
201 def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops),
203 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1,
204 (ops variable_ops), "bctrl", BrB>;
207 // D-Form instructions. Most instructions that perform an operation on a
208 // register and an immediate are of this type.
211 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
212 "lbz $rD, $disp($rA)", LdStGeneral>;
213 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
214 "lha $rD, $disp($rA)", LdStLHA>;
215 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
216 "lhz $rD, $disp($rA)", LdStGeneral>;
217 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
218 "lmw $rD, $disp($rA)", LdStLMW>;
219 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
220 "lwz $rD, $disp($rA)", LdStGeneral>;
221 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
222 "lwzu $rD, $disp($rA)", LdStGeneral>;
224 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
225 "addi $rD, $rA, $imm", IntGeneral,
226 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
227 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
228 "addic $rD, $rA, $imm", IntGeneral,
230 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
231 "addic. $rD, $rA, $imm", IntGeneral,
233 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
234 "addis $rD, $rA, $imm", IntGeneral,
235 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
236 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
237 "la $rD, $sym($rA)", IntGeneral,
239 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
240 "mulli $rD, $rA, $imm", IntMulLI,
241 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
242 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
243 "subfic $rD, $rA, $imm", IntGeneral,
244 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
245 def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
246 "li $rD, $imm", IntGeneral,
247 [(set GPRC:$rD, immSExt16:$imm)]>;
248 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
249 "lis $rD, $imm", IntGeneral,
250 [(set GPRC:$rD, imm16Shifted:$imm)]>;
252 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
253 "stmw $rS, $disp($rA)", LdStLMW>;
254 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
255 "stb $rS, $disp($rA)", LdStGeneral>;
256 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
257 "sth $rS, $disp($rA)", LdStGeneral>;
258 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
259 "stw $rS, $disp($rA)", LdStGeneral>;
260 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
261 "stwu $rS, $disp($rA)", LdStGeneral>;
263 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
264 "andi. $dst, $src1, $src2", IntGeneral,
266 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
267 "andis. $dst, $src1, $src2", IntGeneral,
269 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
270 "ori $dst, $src1, $src2", IntGeneral,
271 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
272 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
273 "oris $dst, $src1, $src2", IntGeneral,
274 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
275 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
276 "xori $dst, $src1, $src2", IntGeneral,
277 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
278 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
279 "xoris $dst, $src1, $src2", IntGeneral,
280 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
281 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral>;
282 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
283 "cmpi $crD, $L, $rA, $imm", IntCompare>;
284 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
285 "cmpwi $crD, $rA, $imm", IntCompare>;
286 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
287 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
288 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
289 "cmpli $dst, $size, $src1, $src2", IntCompare>;
290 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
291 "cmplwi $dst, $src1, $src2", IntCompare>;
292 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
293 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
295 def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
296 "lfs $rD, $disp($rA)", LdStLFDU>;
297 def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
298 "lfd $rD, $disp($rA)", LdStLFD>;
301 def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
302 "stfs $rS, $disp($rA)", LdStUX>;
303 def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
304 "stfd $rS, $disp($rA)", LdStUX>;
307 // DS-Form instructions. Load/Store instructions available in PPC-64
310 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
311 "lwa $rT, $DS($rA)", LdStLWA>, isPPC64;
312 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
313 "ld $rT, $DS($rA)", LdStLD>, isPPC64;
316 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
317 "std $rT, $DS($rA)", LdStSTD>, isPPC64;
318 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
319 "stdu $rT, $DS($rA)", LdStSTD>, isPPC64;
322 // X-Form instructions. Most instructions that perform an operation on a
323 // register and another register are of this type.
326 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
327 "lbzx $dst, $base, $index", LdStGeneral>;
328 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
329 "lhax $dst, $base, $index", LdStLHA>;
330 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
331 "lhzx $dst, $base, $index", LdStGeneral>;
332 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
333 "lwax $dst, $base, $index", LdStLHA>, isPPC64;
334 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
335 "lwzx $dst, $base, $index", LdStGeneral>;
336 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
337 "ldx $dst, $base, $index", LdStLD>, isPPC64;
339 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
340 "nand $rA, $rS, $rB", IntGeneral,
341 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
342 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
343 "and $rA, $rS, $rB", IntGeneral,
344 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
345 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
346 "and. $rA, $rS, $rB", IntGeneral,
348 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
349 "andc $rA, $rS, $rB", IntGeneral,
350 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
351 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
352 "or $rA, $rS, $rB", IntGeneral,
353 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
354 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
355 "or $rA, $rS, $rB", IntGeneral,
356 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
357 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
358 "or $rA, $rS, $rB", IntGeneral,
360 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
361 "or $rA, $rS, $rB", IntGeneral,
363 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
364 "nor $rA, $rS, $rB", IntGeneral,
365 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
366 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
367 "or. $rA, $rS, $rB", IntGeneral,
369 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
370 "orc $rA, $rS, $rB", IntGeneral,
371 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
372 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
373 "eqv $rA, $rS, $rB", IntGeneral,
374 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
375 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
376 "xor $rA, $rS, $rB", IntGeneral,
377 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
378 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
379 "sld $rA, $rS, $rB", IntRotateD,
380 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
381 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
382 "slw $rA, $rS, $rB", IntGeneral,
383 [(set GPRC:$rA, (shl GPRC:$rS, GPRC:$rB))]>;
384 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
385 "srd $rA, $rS, $rB", IntRotateD,
386 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
387 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
388 "srw $rA, $rS, $rB", IntGeneral,
389 [(set GPRC:$rA, (srl GPRC:$rS, GPRC:$rB))]>;
390 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
391 "srad $rA, $rS, $rB", IntRotateD,
392 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
393 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
394 "sraw $rA, $rS, $rB", IntShift,
395 [(set GPRC:$rA, (sra GPRC:$rS, GPRC:$rB))]>;
397 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
398 "stbx $rS, $rA, $rB", LdStGeneral>;
399 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
400 "sthx $rS, $rA, $rB", LdStGeneral>;
401 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
402 "stwx $rS, $rA, $rB", LdStGeneral>;
403 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
404 "stwux $rS, $rA, $rB", LdStGeneral>;
405 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
406 "stdx $rS, $rA, $rB", LdStSTD>, isPPC64;
407 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
408 "stdux $rS, $rA, $rB", LdStSTD>, isPPC64;
410 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
411 "srawi $rA, $rS, $SH", IntShift,
412 [(set GPRC:$rA, (sra GPRC:$rS, imm:$SH))]>;
413 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
414 "cntlzw $rA, $rS", IntGeneral,
415 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
416 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
417 "extsb $rA, $rS", IntGeneral,
418 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
419 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
420 "extsh $rA, $rS", IntGeneral,
421 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
422 def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
423 "extsw $rA, $rS", IntRotateD,
425 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
426 "cmp $crD, $long, $rA, $rB", IntCompare>;
427 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
428 "cmpl $crD, $long, $rA, $rB", IntCompare>;
429 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
430 "cmpw $crD, $rA, $rB", IntCompare>;
431 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
432 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
433 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
434 "cmplw $crD, $rA, $rB", IntCompare>;
435 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
436 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
437 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
438 // "fcmpo $crD, $fA, $fB", FPCompare>;
439 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
440 "fcmpu $crD, $fA, $fB", FPCompare>;
441 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
442 "fcmpu $crD, $fA, $fB", FPCompare>;
445 def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
446 "lfsx $dst, $base, $index", LdStLFDU>;
447 def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
448 "lfdx $dst, $base, $index", LdStLFDU>;
450 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
451 "fcfid $frD, $frB", FPGeneral,
453 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
454 "fctidz $frD, $frB", FPGeneral,
456 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
457 "fctiwz $frD, $frB", FPGeneral,
459 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
460 "frsp $frD, $frB", FPGeneral,
461 [(set F4RC:$frD, (fround F8RC:$frB))]>;
462 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
463 "fsqrt $frD, $frB", FPSqrt,
464 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
465 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
466 "fsqrts $frD, $frB", FPSqrt,
467 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
469 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
470 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
471 "fmr $frD, $frB", FPGeneral,
472 []>; // (set F4RC:$frD, F4RC:$frB)
473 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
474 "fmr $frD, $frB", FPGeneral,
475 []>; // (set F8RC:$frD, F8RC:$frB)
476 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
477 "fmr $frD, $frB", FPGeneral,
478 [(set F8RC:$frD, (fextend F4RC:$frB))]>;
480 // These are artificially split into two different forms, for 4/8 byte FP.
481 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
482 "fabs $frD, $frB", FPGeneral,
483 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
484 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
485 "fabs $frD, $frB", FPGeneral,
486 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
487 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
488 "fnabs $frD, $frB", FPGeneral,
489 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
490 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
491 "fnabs $frD, $frB", FPGeneral,
492 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
493 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
494 "fneg $frD, $frB", FPGeneral,
495 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
496 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
497 "fneg $frD, $frB", FPGeneral,
498 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
502 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
503 "stfsx $frS, $rA, $rB", LdStUX>;
504 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
505 "stfdx $frS, $rA, $rB", LdStUX>;
508 // XL-Form instructions. condition register logical ops.
510 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
511 "mcrf $BF, $BFA", BrMCR>;
513 // XFX-Form instructions. Instructions that deal with SPRs
515 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
516 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
517 // which means the SPR value needs to be multiplied by a factor of 32.
518 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
519 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT", SprMFSPR>;
520 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>;
521 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
522 "mtcrf $FXM, $rS", BrMCRX>;
523 def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
524 "mfcr $rT, $FXM", SprMFCR>;
525 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
526 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
528 // XS-Form instructions. Just 'sradi'
530 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
531 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
533 // XO-Form instructions. Arithmetic instructions that can set overflow bit
535 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
536 "add $rT, $rA, $rB", IntGeneral,
537 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
538 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
539 "add $rT, $rA, $rB", IntGeneral,
540 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
541 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
542 "addc $rT, $rA, $rB", IntGeneral,
544 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
545 "adde $rT, $rA, $rB", IntGeneral,
547 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
548 "divd $rT, $rA, $rB", IntDivD,
549 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
550 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
551 "divdu $rT, $rA, $rB", IntDivD,
552 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
553 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
554 "divw $rT, $rA, $rB", IntDivW,
555 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
556 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
557 "divwu $rT, $rA, $rB", IntDivW,
558 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
559 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
560 "mulhd $rT, $rA, $rB", IntMulHW,
561 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
562 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
563 "mulhdu $rT, $rA, $rB", IntMulHWU,
564 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
565 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
566 "mulhw $rT, $rA, $rB", IntMulHW,
567 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
568 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
569 "mulhwu $rT, $rA, $rB", IntMulHWU,
570 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
571 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
572 "mulld $rT, $rA, $rB", IntMulHD,
573 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
574 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
575 "mullw $rT, $rA, $rB", IntMulHW,
576 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
577 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
578 "subf $rT, $rA, $rB", IntGeneral,
579 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
580 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
581 "subfc $rT, $rA, $rB", IntGeneral,
583 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
584 "subfe $rT, $rA, $rB", IntGeneral,
586 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
587 "addme $rT, $rA", IntGeneral,
589 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
590 "addze $rT, $rA", IntGeneral,
592 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
593 "neg $rT, $rA", IntGeneral,
594 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
595 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
596 "subfze $rT, $rA", IntGeneral,
599 // A-Form instructions. Most of the instructions executed in the FPU are of
602 def FMADD : AForm_1<63, 29,
603 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
604 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
605 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
607 def FMADDS : AForm_1<59, 29,
608 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
609 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
610 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
612 def FMSUB : AForm_1<63, 28,
613 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
614 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
615 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
617 def FMSUBS : AForm_1<59, 28,
618 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
619 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
620 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
622 def FNMADD : AForm_1<63, 31,
623 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
624 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
625 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
627 def FNMADDS : AForm_1<59, 31,
628 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
629 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
630 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
632 def FNMSUB : AForm_1<63, 30,
633 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
634 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
635 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
637 def FNMSUBS : AForm_1<59, 30,
638 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
639 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
640 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
642 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
643 // having 4 of these, force the comparison to always be an 8-byte double (code
644 // should use an FMRSD if the input comparison value really wants to be a float)
645 // and 4/8 byte forms for the result and operand type..
646 def FSELD : AForm_1<63, 23,
647 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
648 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
650 def FSELS : AForm_1<63, 23,
651 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
652 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
654 def FADD : AForm_2<63, 21,
655 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
656 "fadd $FRT, $FRA, $FRB", FPGeneral,
657 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
658 def FADDS : AForm_2<59, 21,
659 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
660 "fadds $FRT, $FRA, $FRB", FPGeneral,
661 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
662 def FDIV : AForm_2<63, 18,
663 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
664 "fdiv $FRT, $FRA, $FRB", FPDivD,
665 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
666 def FDIVS : AForm_2<59, 18,
667 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
668 "fdivs $FRT, $FRA, $FRB", FPDivS,
669 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
670 def FMUL : AForm_3<63, 25,
671 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
672 "fmul $FRT, $FRA, $FRB", FPFused,
673 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
674 def FMULS : AForm_3<59, 25,
675 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
676 "fmuls $FRT, $FRA, $FRB", FPGeneral,
677 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
678 def FSUB : AForm_2<63, 20,
679 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
680 "fsub $FRT, $FRA, $FRB", FPGeneral,
681 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
682 def FSUBS : AForm_2<59, 20,
683 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
684 "fsubs $FRT, $FRA, $FRB", FPGeneral,
685 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
687 // M-Form instructions. rotate and mask instructions.
689 let isTwoAddress = 1, isCommutable = 1 in {
690 // RLWIMI can be commuted if the rotate amount is zero.
691 def RLWIMI : MForm_2<20,
692 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
693 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
695 def RLDIMI : MDForm_1<30, 3,
696 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
697 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
700 def RLWINM : MForm_2<21,
701 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
702 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
704 def RLWINMo : MForm_2<21,
705 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
706 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
708 def RLWNM : MForm_2<23,
709 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
710 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
713 // MD-Form instructions. 64 bit rotate instructions.
715 def RLDICL : MDForm_1<30, 0,
716 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
717 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
719 def RLDICR : MDForm_1<30, 1,
720 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
721 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
724 //===----------------------------------------------------------------------===//
725 // PowerPC Instruction Patterns
728 // Arbitrary immediate support. Implement in terms of LIS/ORI.
729 def : Pat<(i32 imm:$imm),
730 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
732 // Implement the 'not' operation with the NOR instruction.
733 def NOT : Pat<(not GPRC:$in),
734 (NOR GPRC:$in, GPRC:$in)>;
736 // ADD an arbitrary immediate.
737 def : Pat<(add GPRC:$in, imm:$imm),
738 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
739 // OR an arbitrary immediate.
740 def : Pat<(or GPRC:$in, imm:$imm),
741 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
742 // XOR an arbitrary immediate.
743 def : Pat<(xor GPRC:$in, imm:$imm),
744 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
745 def : Pat<(or (shl GPRC:$rS, GPRC:$rB),
746 (srl GPRC:$rS, (sub 32, GPRC:$rB))),
747 (RLWNM GPRC:$rS, GPRC:$rB, 0, 31)>;
749 def : Pat<(zext GPRC:$in),
750 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
751 def : Pat<(anyext GPRC:$in),
752 (OR4To8 GPRC:$in, GPRC:$in)>;
753 def : Pat<(trunc G8RC:$in),
754 (OR8To4 G8RC:$in, G8RC:$in)>;
757 def : Pat<(shl GPRC:$in, imm:$imm),
758 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
759 def : Pat<(shl G8RC:$in, imm:$imm),
760 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
762 def : Pat<(srl GPRC:$in, imm:$imm),
763 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
764 def : Pat<(srl G8RC:$in, imm:$imm),
765 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
767 // Same as above, but using a temporary. FIXME: implement temporaries :)
769 def : Pattern<(xor GPRC:$in, imm:$imm),
770 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
771 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
775 //===----------------------------------------------------------------------===//
776 // PowerPCInstrInfo Definition
778 def PowerPCInstrInfo : InstrInfo {
781 let TSFlagsFields = [ "VMX", "PPC64" ];
782 let TSFlagsShifts = [ 0, 1 ];
784 let isLittleEndianEncoding = 1;