1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 2, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPClarx : SDTypeProfile<1, 1, [
46 SDTCisInt<0>, SDTCisPtrTy<1>
48 def SDT_PPCstcx : SDTypeProfile<0, 2, [
49 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
53 SDTCisPtrTy<0>, SDTCisVT<1, i32>
56 def SDT_PPCnop : SDTypeProfile<0, 0, []>;
58 //===----------------------------------------------------------------------===//
59 // PowerPC specific DAG Nodes.
62 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
63 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
64 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
65 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
66 [SDNPHasChain, SDNPMayStore]>;
68 // This sequence is used for long double->int conversions. It changes the
69 // bits in the FPSCR which is not modelled.
70 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
72 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
73 [SDNPInFlag, SDNPOutFlag]>;
74 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
75 [SDNPInFlag, SDNPOutFlag]>;
76 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
77 [SDNPInFlag, SDNPOutFlag]>;
78 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
83 def PPCfsel : SDNode<"PPCISD::FSEL",
84 // Type constraint for fsel.
85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
88 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
89 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
90 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
91 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
92 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
94 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
96 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
97 // amounts. These nodes are generated by the multi-precision shift code.
98 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
99 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
100 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
102 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
103 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
104 [SDNPHasChain, SDNPMayStore]>;
106 // These are target-independent nodes, but have target-specific formats.
107 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
108 [SDNPHasChain, SDNPOutFlag]>;
109 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
110 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
112 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
113 def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall,
114 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
116 def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall,
117 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
119 def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInFlag, SDNPOutFlag]>;
120 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
121 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
122 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
123 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
124 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
125 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
126 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
127 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
128 def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone,
129 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
132 def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone,
133 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
136 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
137 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
139 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
140 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
142 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
143 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
145 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
146 [SDNPHasChain, SDNPOptInFlag]>;
148 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
149 [SDNPHasChain, SDNPMayLoad]>;
150 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
151 [SDNPHasChain, SDNPMayStore]>;
153 // Instructions to support atomic operations
154 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
155 [SDNPHasChain, SDNPMayLoad]>;
156 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
157 [SDNPHasChain, SDNPMayStore]>;
159 // Instructions to support dynamic alloca.
160 def SDTDynOp : SDTypeProfile<1, 2, []>;
161 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
163 //===----------------------------------------------------------------------===//
164 // PowerPC specific transformation functions and pattern fragments.
167 def SHL32 : SDNodeXForm<imm, [{
168 // Transformation function: 31 - imm
169 return getI32Imm(31 - N->getZExtValue());
172 def SRL32 : SDNodeXForm<imm, [{
173 // Transformation function: 32 - imm
174 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
177 def LO16 : SDNodeXForm<imm, [{
178 // Transformation function: get the low 16 bits.
179 return getI32Imm((unsigned short)N->getZExtValue());
182 def HI16 : SDNodeXForm<imm, [{
183 // Transformation function: shift the immediate value down into the low bits.
184 return getI32Imm((unsigned)N->getZExtValue() >> 16);
187 def HA16 : SDNodeXForm<imm, [{
188 // Transformation function: shift the immediate value down into the low bits.
189 signed int Val = N->getZExtValue();
190 return getI32Imm((Val - (signed short)Val) >> 16);
192 def MB : SDNodeXForm<imm, [{
193 // Transformation function: get the start bit of a mask
195 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
196 return getI32Imm(mb);
199 def ME : SDNodeXForm<imm, [{
200 // Transformation function: get the end bit of a mask
202 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
203 return getI32Imm(me);
205 def maskimm32 : PatLeaf<(imm), [{
206 // maskImm predicate - True if immediate is a run of ones.
208 if (N->getValueType(0) == MVT::i32)
209 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
214 def immSExt16 : PatLeaf<(imm), [{
215 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
216 // field. Used by instructions like 'addi'.
217 if (N->getValueType(0) == MVT::i32)
218 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
220 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
222 def immZExt16 : PatLeaf<(imm), [{
223 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
224 // field. Used by instructions like 'ori'.
225 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
228 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
229 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
230 // identical in 32-bit mode, but in 64-bit mode, they return true if the
231 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
233 def imm16ShiftedZExt : PatLeaf<(imm), [{
234 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
235 // immediate are set. Used by instructions like 'xoris'.
236 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
239 def imm16ShiftedSExt : PatLeaf<(imm), [{
240 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
241 // immediate are set. Used by instructions like 'addis'. Identical to
242 // imm16ShiftedZExt in 32-bit mode.
243 if (N->getZExtValue() & 0xFFFF) return false;
244 if (N->getValueType(0) == MVT::i32)
246 // For 64-bit, make sure it is sext right.
247 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
251 //===----------------------------------------------------------------------===//
252 // PowerPC Flag Definitions.
254 class isPPC64 { bit PPC64 = 1; }
256 list<Register> Defs = [CR0];
260 class RegConstraint<string C> {
261 string Constraints = C;
263 class NoEncode<string E> {
264 string DisableEncoding = E;
268 //===----------------------------------------------------------------------===//
269 // PowerPC Operand Definitions.
271 def s5imm : Operand<i32> {
272 let PrintMethod = "printS5ImmOperand";
274 def u5imm : Operand<i32> {
275 let PrintMethod = "printU5ImmOperand";
277 def u6imm : Operand<i32> {
278 let PrintMethod = "printU6ImmOperand";
280 def s16imm : Operand<i32> {
281 let PrintMethod = "printS16ImmOperand";
283 def u16imm : Operand<i32> {
284 let PrintMethod = "printU16ImmOperand";
286 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
287 let PrintMethod = "printS16X4ImmOperand";
289 def target : Operand<OtherVT> {
290 let PrintMethod = "printBranchOperand";
292 def calltarget : Operand<iPTR> {
293 let PrintMethod = "printCallOperand";
295 def aaddr : Operand<iPTR> {
296 let PrintMethod = "printAbsAddrOperand";
298 def piclabel: Operand<iPTR> {}
299 def symbolHi: Operand<i32> {
300 let PrintMethod = "printSymbolHi";
302 def symbolLo: Operand<i32> {
303 let PrintMethod = "printSymbolLo";
305 def crbitm: Operand<i8> {
306 let PrintMethod = "printcrbitm";
309 def memri : Operand<iPTR> {
310 let PrintMethod = "printMemRegImm";
311 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
313 def memrr : Operand<iPTR> {
314 let PrintMethod = "printMemRegReg";
315 let MIOperandInfo = (ops ptr_rc, ptr_rc);
317 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
318 let PrintMethod = "printMemRegImmShifted";
319 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
321 def tocentry : Operand<iPTR> {
322 let MIOperandInfo = (ops i32imm:$imm);
325 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
326 // that doesn't matter.
327 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
328 (ops (i32 20), (i32 zero_reg))> {
329 let PrintMethod = "printPredicateOperand";
332 // Define PowerPC specific addressing mode.
333 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
334 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
335 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
336 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
338 /// This is just the offset part of iaddr, used for preinc.
339 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
341 //===----------------------------------------------------------------------===//
342 // PowerPC Instruction Predicate Definitions.
343 def FPContractions : Predicate<"!NoExcessFPPrecision">;
344 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
345 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
348 //===----------------------------------------------------------------------===//
349 // PowerPC Instruction Definitions.
351 // Pseudo-instructions:
353 let hasCtrlDep = 1 in {
354 let Defs = [R1], Uses = [R1] in {
355 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "",
356 [(callseq_start timm:$amt)]>;
357 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "",
358 [(callseq_end timm:$amt1, timm:$amt2)]>;
361 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
362 "UPDATE_VRSAVE $rD, $rS", []>;
365 let Defs = [R1], Uses = [R1] in
366 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "",
368 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
370 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
371 // instruction selection into a branch sequence.
372 let usesCustomInserter = 1, // Expanded after instruction selection.
373 PPC970_Single = 1 in {
374 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
377 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
380 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
383 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
386 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
391 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
392 // scavenge a register for it.
393 def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F),
396 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
397 let isReturn = 1, Uses = [LR, RM] in
398 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
399 "b${p:cc}lr ${p:reg}", BrB,
401 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
402 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
406 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "", []>,
409 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
410 let isBarrier = 1 in {
411 def B : IForm<18, 0, 0, (outs), (ins target:$dst),
416 // BCC represents an arbitrary conditional branch on a predicate.
417 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
418 // a two-value operand where a dag node expects two operands. :(
419 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst),
420 "b${cond:cc} ${cond:reg}, $dst"
421 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
425 let isCall = 1, PPC970_Unit = 7,
426 // All calls clobber the non-callee saved registers...
427 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
428 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
429 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
431 CR0,CR1,CR5,CR6,CR7,CARRY] in {
432 // Convenient aliases for call instructions
434 def BL_Darwin : IForm<18, 0, 1,
435 (outs), (ins calltarget:$func, variable_ops),
436 "bl $func", BrB, []>; // See Pat patterns below.
437 def BLA_Darwin : IForm<18, 1, 1,
438 (outs), (ins aaddr:$func, variable_ops),
439 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>;
441 let Uses = [CTR, RM] in {
442 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
443 (outs), (ins variable_ops),
445 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>;
450 let isCall = 1, PPC970_Unit = 7,
451 // All calls clobber the non-callee saved registers...
452 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
453 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
454 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
456 CR0,CR1,CR5,CR6,CR7,CARRY] in {
457 // Convenient aliases for call instructions
459 def BL_SVR4 : IForm<18, 0, 1,
460 (outs), (ins calltarget:$func, variable_ops),
461 "bl $func", BrB, []>; // See Pat patterns below.
462 def BLA_SVR4 : IForm<18, 1, 1,
463 (outs), (ins aaddr:$func, variable_ops),
465 [(PPCcall_SVR4 (i32 imm:$func))]>;
467 let Uses = [CTR, RM] in {
468 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1,
469 (outs), (ins variable_ops),
471 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>;
476 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
477 def TCRETURNdi :Pseudo< (outs),
478 (ins calltarget:$dst, i32imm:$offset, variable_ops),
479 "#TC_RETURNd $dst $offset",
483 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
484 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops),
485 "#TC_RETURNa $func $offset",
486 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
488 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
489 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset, variable_ops),
490 "#TC_RETURNr $dst $offset",
494 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
495 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
496 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
497 Requires<[In32BitMode]>;
501 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
502 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
503 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
508 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
509 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
510 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
515 // DCB* instructions.
516 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
517 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
518 PPC970_DGroup_Single;
519 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
520 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
521 PPC970_DGroup_Single;
522 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
523 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
524 PPC970_DGroup_Single;
525 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
526 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
527 PPC970_DGroup_Single;
528 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
529 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
530 PPC970_DGroup_Single;
531 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
532 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
533 PPC970_DGroup_Single;
534 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
535 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
536 PPC970_DGroup_Single;
537 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
538 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
539 PPC970_DGroup_Single;
542 let usesCustomInserter = 1 in {
543 let Uses = [CR0] in {
544 def ATOMIC_LOAD_ADD_I8 : Pseudo<
545 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
546 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>;
547 def ATOMIC_LOAD_SUB_I8 : Pseudo<
548 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
549 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>;
550 def ATOMIC_LOAD_AND_I8 : Pseudo<
551 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
552 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>;
553 def ATOMIC_LOAD_OR_I8 : Pseudo<
554 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
555 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>;
556 def ATOMIC_LOAD_XOR_I8 : Pseudo<
557 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
558 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>;
559 def ATOMIC_LOAD_NAND_I8 : Pseudo<
560 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
561 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>;
562 def ATOMIC_LOAD_ADD_I16 : Pseudo<
563 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
564 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>;
565 def ATOMIC_LOAD_SUB_I16 : Pseudo<
566 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
567 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>;
568 def ATOMIC_LOAD_AND_I16 : Pseudo<
569 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
570 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>;
571 def ATOMIC_LOAD_OR_I16 : Pseudo<
572 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
573 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>;
574 def ATOMIC_LOAD_XOR_I16 : Pseudo<
575 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
576 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>;
577 def ATOMIC_LOAD_NAND_I16 : Pseudo<
578 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
579 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>;
580 def ATOMIC_LOAD_ADD_I32 : Pseudo<
581 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
582 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
583 def ATOMIC_LOAD_SUB_I32 : Pseudo<
584 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
585 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>;
586 def ATOMIC_LOAD_AND_I32 : Pseudo<
587 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
588 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>;
589 def ATOMIC_LOAD_OR_I32 : Pseudo<
590 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
591 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>;
592 def ATOMIC_LOAD_XOR_I32 : Pseudo<
593 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
594 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>;
595 def ATOMIC_LOAD_NAND_I32 : Pseudo<
596 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
597 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>;
599 def ATOMIC_CMP_SWAP_I8 : Pseudo<
600 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
602 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
603 def ATOMIC_CMP_SWAP_I16 : Pseudo<
604 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
606 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
607 def ATOMIC_CMP_SWAP_I32 : Pseudo<
608 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
610 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
612 def ATOMIC_SWAP_I8 : Pseudo<
613 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
614 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>;
615 def ATOMIC_SWAP_I16 : Pseudo<
616 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
617 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>;
618 def ATOMIC_SWAP_I32 : Pseudo<
619 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
620 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>;
624 // Instructions to support atomic operations
625 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
626 "lwarx $rD, $src", LdStLWARX,
627 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>;
630 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
631 "stwcx. $rS, $dst", LdStSTWCX,
632 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>,
635 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
636 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStGeneral, [(trap)]>;
638 //===----------------------------------------------------------------------===//
639 // PPC32 Load Instructions.
642 // Unindexed (r+i) Loads.
643 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
644 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
645 "lbz $rD, $src", LdStGeneral,
646 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
647 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
648 "lha $rD, $src", LdStLHA,
649 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
650 PPC970_DGroup_Cracked;
651 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
652 "lhz $rD, $src", LdStGeneral,
653 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
654 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
655 "lwz $rD, $src", LdStGeneral,
656 [(set GPRC:$rD, (load iaddr:$src))]>;
658 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
659 "lfs $rD, $src", LdStLFDU,
660 [(set F4RC:$rD, (load iaddr:$src))]>;
661 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
662 "lfd $rD, $src", LdStLFD,
663 [(set F8RC:$rD, (load iaddr:$src))]>;
666 // Unindexed (r+i) Loads with Update (preinc).
668 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
669 "lbzu $rD, $addr", LdStGeneral,
670 []>, RegConstraint<"$addr.reg = $ea_result">,
671 NoEncode<"$ea_result">;
673 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
674 "lhau $rD, $addr", LdStGeneral,
675 []>, RegConstraint<"$addr.reg = $ea_result">,
676 NoEncode<"$ea_result">;
678 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
679 "lhzu $rD, $addr", LdStGeneral,
680 []>, RegConstraint<"$addr.reg = $ea_result">,
681 NoEncode<"$ea_result">;
683 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
684 "lwzu $rD, $addr", LdStGeneral,
685 []>, RegConstraint<"$addr.reg = $ea_result">,
686 NoEncode<"$ea_result">;
688 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
689 "lfs $rD, $addr", LdStLFDU,
690 []>, RegConstraint<"$addr.reg = $ea_result">,
691 NoEncode<"$ea_result">;
693 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
694 "lfd $rD, $addr", LdStLFD,
695 []>, RegConstraint<"$addr.reg = $ea_result">,
696 NoEncode<"$ea_result">;
700 // Indexed (r+r) Loads.
702 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
703 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
704 "lbzx $rD, $src", LdStGeneral,
705 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
706 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
707 "lhax $rD, $src", LdStLHA,
708 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
709 PPC970_DGroup_Cracked;
710 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
711 "lhzx $rD, $src", LdStGeneral,
712 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
713 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
714 "lwzx $rD, $src", LdStGeneral,
715 [(set GPRC:$rD, (load xaddr:$src))]>;
718 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
719 "lhbrx $rD, $src", LdStGeneral,
720 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>;
721 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
722 "lwbrx $rD, $src", LdStGeneral,
723 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>;
725 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
726 "lfsx $frD, $src", LdStLFDU,
727 [(set F4RC:$frD, (load xaddr:$src))]>;
728 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
729 "lfdx $frD, $src", LdStLFDU,
730 [(set F8RC:$frD, (load xaddr:$src))]>;
733 //===----------------------------------------------------------------------===//
734 // PPC32 Store Instructions.
737 // Unindexed (r+i) Stores.
738 let PPC970_Unit = 2 in {
739 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
740 "stb $rS, $src", LdStGeneral,
741 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
742 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
743 "sth $rS, $src", LdStGeneral,
744 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
745 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
746 "stw $rS, $src", LdStGeneral,
747 [(store GPRC:$rS, iaddr:$src)]>;
748 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
749 "stfs $rS, $dst", LdStUX,
750 [(store F4RC:$rS, iaddr:$dst)]>;
751 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
752 "stfd $rS, $dst", LdStUX,
753 [(store F8RC:$rS, iaddr:$dst)]>;
756 // Unindexed (r+i) Stores with Update (preinc).
757 let PPC970_Unit = 2 in {
758 def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
759 symbolLo:$ptroff, ptr_rc:$ptrreg),
760 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
761 [(set ptr_rc:$ea_res,
762 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
763 iaddroff:$ptroff))]>,
764 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
765 def STHU : DForm_1<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
766 symbolLo:$ptroff, ptr_rc:$ptrreg),
767 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
768 [(set ptr_rc:$ea_res,
769 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
770 iaddroff:$ptroff))]>,
771 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
772 def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
773 symbolLo:$ptroff, ptr_rc:$ptrreg),
774 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
775 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
776 iaddroff:$ptroff))]>,
777 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
778 def STFSU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
779 symbolLo:$ptroff, ptr_rc:$ptrreg),
780 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
781 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
782 iaddroff:$ptroff))]>,
783 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
784 def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
785 symbolLo:$ptroff, ptr_rc:$ptrreg),
786 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
787 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
788 iaddroff:$ptroff))]>,
789 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
793 // Indexed (r+r) Stores.
795 let PPC970_Unit = 2 in {
796 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
797 "stbx $rS, $dst", LdStGeneral,
798 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
799 PPC970_DGroup_Cracked;
800 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
801 "sthx $rS, $dst", LdStGeneral,
802 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
803 PPC970_DGroup_Cracked;
804 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
805 "stwx $rS, $dst", LdStGeneral,
806 [(store GPRC:$rS, xaddr:$dst)]>,
807 PPC970_DGroup_Cracked;
809 let mayStore = 1 in {
810 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
811 "stwux $rS, $rA, $rB", LdStGeneral,
814 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
815 "sthbrx $rS, $dst", LdStGeneral,
816 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>,
817 PPC970_DGroup_Cracked;
818 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
819 "stwbrx $rS, $dst", LdStGeneral,
820 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>,
821 PPC970_DGroup_Cracked;
823 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
824 "stfiwx $frS, $dst", LdStUX,
825 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
827 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
828 "stfsx $frS, $dst", LdStUX,
829 [(store F4RC:$frS, xaddr:$dst)]>;
830 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
831 "stfdx $frS, $dst", LdStUX,
832 [(store F8RC:$frS, xaddr:$dst)]>;
835 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
839 //===----------------------------------------------------------------------===//
840 // PPC32 Arithmetic Instructions.
843 let PPC970_Unit = 1 in { // FXU Operations.
844 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
845 "addi $rD, $rA, $imm", IntGeneral,
846 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
847 let Defs = [CARRY] in {
848 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
849 "addic $rD, $rA, $imm", IntGeneral,
850 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
851 PPC970_DGroup_Cracked;
852 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
853 "addic. $rD, $rA, $imm", IntGeneral,
856 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
857 "addis $rD, $rA, $imm", IntGeneral,
858 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
859 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
860 "la $rD, $sym($rA)", IntGeneral,
861 [(set GPRC:$rD, (add GPRC:$rA,
862 (PPClo tglobaladdr:$sym, 0)))]>;
863 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
864 "mulli $rD, $rA, $imm", IntMulLI,
865 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
866 let Defs = [CARRY] in {
867 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
868 "subfic $rD, $rA, $imm", IntGeneral,
869 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
872 let isReMaterializable = 1 in {
873 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
874 "li $rD, $imm", IntGeneral,
875 [(set GPRC:$rD, immSExt16:$imm)]>;
876 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
877 "lis $rD, $imm", IntGeneral,
878 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
882 let PPC970_Unit = 1 in { // FXU Operations.
883 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
884 "andi. $dst, $src1, $src2", IntGeneral,
885 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
887 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
888 "andis. $dst, $src1, $src2", IntGeneral,
889 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
891 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
892 "ori $dst, $src1, $src2", IntGeneral,
893 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
894 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
895 "oris $dst, $src1, $src2", IntGeneral,
896 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
897 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
898 "xori $dst, $src1, $src2", IntGeneral,
899 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
900 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
901 "xoris $dst, $src1, $src2", IntGeneral,
902 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
903 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral,
905 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
906 "cmpwi $crD, $rA, $imm", IntCompare>;
907 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
908 "cmplwi $dst, $src1, $src2", IntCompare>;
912 let PPC970_Unit = 1 in { // FXU Operations.
913 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
914 "nand $rA, $rS, $rB", IntGeneral,
915 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
916 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
917 "and $rA, $rS, $rB", IntGeneral,
918 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
919 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
920 "andc $rA, $rS, $rB", IntGeneral,
921 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
922 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
923 "or $rA, $rS, $rB", IntGeneral,
924 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
925 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
926 "nor $rA, $rS, $rB", IntGeneral,
927 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
928 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
929 "orc $rA, $rS, $rB", IntGeneral,
930 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
931 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
932 "eqv $rA, $rS, $rB", IntGeneral,
933 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
934 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
935 "xor $rA, $rS, $rB", IntGeneral,
936 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
937 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
938 "slw $rA, $rS, $rB", IntGeneral,
939 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
940 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
941 "srw $rA, $rS, $rB", IntGeneral,
942 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
943 let Defs = [CARRY] in {
944 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
945 "sraw $rA, $rS, $rB", IntShift,
946 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
950 let PPC970_Unit = 1 in { // FXU Operations.
951 let Defs = [CARRY] in {
952 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
953 "srawi $rA, $rS, $SH", IntShift,
954 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
956 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
957 "cntlzw $rA, $rS", IntGeneral,
958 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
959 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
960 "extsb $rA, $rS", IntGeneral,
961 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
962 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
963 "extsh $rA, $rS", IntGeneral,
964 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
966 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
967 "cmpw $crD, $rA, $rB", IntCompare>;
968 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
969 "cmplw $crD, $rA, $rB", IntCompare>;
971 let PPC970_Unit = 3 in { // FPU Operations.
972 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
973 // "fcmpo $crD, $fA, $fB", FPCompare>;
974 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
975 "fcmpu $crD, $fA, $fB", FPCompare>;
976 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
977 "fcmpu $crD, $fA, $fB", FPCompare>;
980 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
981 "fctiwz $frD, $frB", FPGeneral,
982 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
983 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
984 "frsp $frD, $frB", FPGeneral,
985 [(set F4RC:$frD, (fround F8RC:$frB))]>;
986 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
987 "fsqrt $frD, $frB", FPSqrt,
988 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
989 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
990 "fsqrts $frD, $frB", FPSqrt,
991 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
995 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
996 /// often coalesced away and we don't want the dispatch group builder to think
997 /// that they will fill slots (which could cause the load of a LSU reject to
998 /// sneak into a d-group with a store).
999 def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1000 "fmr $frD, $frB", FPGeneral,
1001 []>, // (set F4RC:$frD, F4RC:$frB)
1004 let PPC970_Unit = 3 in { // FPU Operations.
1005 // These are artificially split into two different forms, for 4/8 byte FP.
1006 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1007 "fabs $frD, $frB", FPGeneral,
1008 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
1009 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1010 "fabs $frD, $frB", FPGeneral,
1011 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
1012 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1013 "fnabs $frD, $frB", FPGeneral,
1014 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
1015 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1016 "fnabs $frD, $frB", FPGeneral,
1017 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
1018 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1019 "fneg $frD, $frB", FPGeneral,
1020 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
1021 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1022 "fneg $frD, $frB", FPGeneral,
1023 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
1027 // XL-Form instructions. condition register logical ops.
1029 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1030 "mcrf $BF, $BFA", BrMCR>,
1031 PPC970_DGroup_First, PPC970_Unit_CRU;
1033 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1034 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1035 "creqv $CRD, $CRA, $CRB", BrCR,
1038 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1039 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1040 "cror $CRD, $CRA, $CRB", BrCR,
1043 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1044 "creqv $dst, $dst, $dst", BrCR,
1047 // XFX-Form instructions. Instructions that deal with SPRs.
1049 let Uses = [CTR] in {
1050 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1051 "mfctr $rT", SprMFSPR>,
1052 PPC970_DGroup_First, PPC970_Unit_FXU;
1054 let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in {
1055 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1056 "mtctr $rS", SprMTSPR>,
1057 PPC970_DGroup_First, PPC970_Unit_FXU;
1060 let Defs = [LR] in {
1061 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1062 "mtlr $rS", SprMTSPR>,
1063 PPC970_DGroup_First, PPC970_Unit_FXU;
1065 let Uses = [LR] in {
1066 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1067 "mflr $rT", SprMFSPR>,
1068 PPC970_DGroup_First, PPC970_Unit_FXU;
1071 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1072 // a GPR on the PPC970. As such, copies in and out have the same performance
1073 // characteristics as an OR instruction.
1074 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1075 "mtspr 256, $rS", IntGeneral>,
1076 PPC970_DGroup_Single, PPC970_Unit_FXU;
1077 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1078 "mfspr $rT, 256", IntGeneral>,
1079 PPC970_DGroup_First, PPC970_Unit_FXU;
1081 def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
1082 "mtcrf $FXM, $rS", BrMCRX>,
1083 PPC970_MicroCode, PPC970_Unit_CRU;
1085 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1086 // declaring that here gives the local register allocator problems with this:
1088 // MFCR <kill of whatever preg got assigned to vreg>
1089 // while not declaring it breaks DeadMachineInstructionElimination.
1090 // As it turns out, in all cases where we currently use this,
1091 // we're only interested in one subregister of it. Represent this in the
1092 // instruction to keep the register allocator from becoming confused.
1094 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1095 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1097 PPC970_MicroCode, PPC970_Unit_CRU;
1099 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
1100 "mfcr $rT", SprMFCR>,
1101 PPC970_MicroCode, PPC970_Unit_CRU;
1103 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1104 "mfcr $rT, $FXM", SprMFCR>,
1105 PPC970_DGroup_First, PPC970_Unit_CRU;
1107 // Instructions to manipulate FPSCR. Only long double handling uses these.
1108 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1110 let Uses = [RM], Defs = [RM] in {
1111 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1112 "mtfsb0 $FM", IntMTFSB0,
1113 [(PPCmtfsb0 (i32 imm:$FM))]>,
1114 PPC970_DGroup_Single, PPC970_Unit_FPU;
1115 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1116 "mtfsb1 $FM", IntMTFSB0,
1117 [(PPCmtfsb1 (i32 imm:$FM))]>,
1118 PPC970_DGroup_Single, PPC970_Unit_FPU;
1119 // MTFSF does not actually produce an FP result. We pretend it copies
1120 // input reg B to the output. If we didn't do this it would look like the
1121 // instruction had no outputs (because we aren't modelling the FPSCR) and
1122 // it would be deleted.
1123 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
1124 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
1125 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
1126 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
1127 F8RC:$rT, F8RC:$FRB))]>,
1128 PPC970_DGroup_Single, PPC970_Unit_FPU;
1130 let Uses = [RM] in {
1131 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1132 "mffs $rT", IntMFFS,
1133 [(set F8RC:$rT, (PPCmffs))]>,
1134 PPC970_DGroup_Single, PPC970_Unit_FPU;
1135 def FADDrtz: AForm_2<63, 21,
1136 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1137 "fadd $FRT, $FRA, $FRB", FPGeneral,
1138 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
1139 PPC970_DGroup_Single, PPC970_Unit_FPU;
1143 let PPC970_Unit = 1 in { // FXU Operations.
1145 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1147 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1148 "add $rT, $rA, $rB", IntGeneral,
1149 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
1150 let Defs = [CARRY] in {
1151 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1152 "addc $rT, $rA, $rB", IntGeneral,
1153 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
1154 PPC970_DGroup_Cracked;
1156 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1157 "divw $rT, $rA, $rB", IntDivW,
1158 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
1159 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1160 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1161 "divwu $rT, $rA, $rB", IntDivW,
1162 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
1163 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1164 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1165 "mulhw $rT, $rA, $rB", IntMulHW,
1166 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
1167 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1168 "mulhwu $rT, $rA, $rB", IntMulHWU,
1169 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
1170 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1171 "mullw $rT, $rA, $rB", IntMulHW,
1172 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
1173 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1174 "subf $rT, $rA, $rB", IntGeneral,
1175 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
1176 let Defs = [CARRY] in {
1177 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1178 "subfc $rT, $rA, $rB", IntGeneral,
1179 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
1180 PPC970_DGroup_Cracked;
1182 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1183 "neg $rT, $rA", IntGeneral,
1184 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
1185 let Uses = [CARRY], Defs = [CARRY] in {
1186 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1187 "adde $rT, $rA, $rB", IntGeneral,
1188 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
1189 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1190 "addme $rT, $rA", IntGeneral,
1191 [(set GPRC:$rT, (adde GPRC:$rA, -1))]>;
1192 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1193 "addze $rT, $rA", IntGeneral,
1194 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
1195 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1196 "subfe $rT, $rA, $rB", IntGeneral,
1197 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
1198 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1199 "subfme $rT, $rA", IntGeneral,
1200 [(set GPRC:$rT, (sube -1, GPRC:$rA))]>;
1201 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1202 "subfze $rT, $rA", IntGeneral,
1203 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
1207 // A-Form instructions. Most of the instructions executed in the FPU are of
1210 let PPC970_Unit = 3 in { // FPU Operations.
1211 let Uses = [RM] in {
1212 def FMADD : AForm_1<63, 29,
1213 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1214 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1215 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1217 Requires<[FPContractions]>;
1218 def FMADDS : AForm_1<59, 29,
1219 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1220 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1221 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1223 Requires<[FPContractions]>;
1224 def FMSUB : AForm_1<63, 28,
1225 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1226 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1227 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1229 Requires<[FPContractions]>;
1230 def FMSUBS : AForm_1<59, 28,
1231 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1232 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1233 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1235 Requires<[FPContractions]>;
1236 def FNMADD : AForm_1<63, 31,
1237 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1238 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1239 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1241 Requires<[FPContractions]>;
1242 def FNMADDS : AForm_1<59, 31,
1243 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1244 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1245 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1247 Requires<[FPContractions]>;
1248 def FNMSUB : AForm_1<63, 30,
1249 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1250 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1251 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1253 Requires<[FPContractions]>;
1254 def FNMSUBS : AForm_1<59, 30,
1255 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1256 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1257 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1259 Requires<[FPContractions]>;
1261 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1262 // having 4 of these, force the comparison to always be an 8-byte double (code
1263 // should use an FMRSD if the input comparison value really wants to be a float)
1264 // and 4/8 byte forms for the result and operand type..
1265 def FSELD : AForm_1<63, 23,
1266 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1267 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1268 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1269 def FSELS : AForm_1<63, 23,
1270 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1271 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1272 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1273 let Uses = [RM] in {
1274 def FADD : AForm_2<63, 21,
1275 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1276 "fadd $FRT, $FRA, $FRB", FPGeneral,
1277 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1278 def FADDS : AForm_2<59, 21,
1279 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1280 "fadds $FRT, $FRA, $FRB", FPGeneral,
1281 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1282 def FDIV : AForm_2<63, 18,
1283 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1284 "fdiv $FRT, $FRA, $FRB", FPDivD,
1285 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1286 def FDIVS : AForm_2<59, 18,
1287 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1288 "fdivs $FRT, $FRA, $FRB", FPDivS,
1289 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1290 def FMUL : AForm_3<63, 25,
1291 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1292 "fmul $FRT, $FRA, $FRB", FPFused,
1293 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1294 def FMULS : AForm_3<59, 25,
1295 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1296 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1297 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1298 def FSUB : AForm_2<63, 20,
1299 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1300 "fsub $FRT, $FRA, $FRB", FPGeneral,
1301 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1302 def FSUBS : AForm_2<59, 20,
1303 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1304 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1305 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1309 let PPC970_Unit = 1 in { // FXU Operations.
1310 // M-Form instructions. rotate and mask instructions.
1312 let isCommutable = 1 in {
1313 // RLWIMI can be commuted if the rotate amount is zero.
1314 def RLWIMI : MForm_2<20,
1315 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1316 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1317 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1320 def RLWINM : MForm_2<21,
1321 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1322 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1324 def RLWINMo : MForm_2<21,
1325 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1326 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1327 []>, isDOT, PPC970_DGroup_Cracked;
1328 def RLWNM : MForm_2<23,
1329 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1330 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1335 //===----------------------------------------------------------------------===//
1336 // PowerPC Instruction Patterns
1339 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1340 def : Pat<(i32 imm:$imm),
1341 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1343 // Implement the 'not' operation with the NOR instruction.
1344 def NOT : Pat<(not GPRC:$in),
1345 (NOR GPRC:$in, GPRC:$in)>;
1347 // ADD an arbitrary immediate.
1348 def : Pat<(add GPRC:$in, imm:$imm),
1349 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1350 // OR an arbitrary immediate.
1351 def : Pat<(or GPRC:$in, imm:$imm),
1352 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1353 // XOR an arbitrary immediate.
1354 def : Pat<(xor GPRC:$in, imm:$imm),
1355 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1357 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1358 (SUBFIC GPRC:$in, imm:$imm)>;
1361 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1362 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1363 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1364 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1367 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1368 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1369 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1370 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1373 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1374 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1377 def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)),
1378 (BL_Darwin tglobaladdr:$dst)>;
1379 def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)),
1380 (BL_Darwin texternalsym:$dst)>;
1381 def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)),
1382 (BL_SVR4 tglobaladdr:$dst)>;
1383 def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)),
1384 (BL_SVR4 texternalsym:$dst)>;
1387 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1388 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1390 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1391 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1393 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1394 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1398 // Hi and Lo for Darwin Global Addresses.
1399 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1400 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1401 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1402 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1403 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1404 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1405 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
1406 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
1407 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1408 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1409 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1410 (ADDIS GPRC:$in, tconstpool:$g)>;
1411 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1412 (ADDIS GPRC:$in, tjumptable:$g)>;
1413 def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)),
1414 (ADDIS GPRC:$in, tblockaddress:$g)>;
1416 // Fused negative multiply subtract, alternate pattern
1417 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1418 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1419 Requires<[FPContractions]>;
1420 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1421 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1422 Requires<[FPContractions]>;
1424 // Standard shifts. These are represented separately from the real shifts above
1425 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1427 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1428 (SRAW GPRC:$rS, GPRC:$rB)>;
1429 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1430 (SRW GPRC:$rS, GPRC:$rB)>;
1431 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1432 (SLW GPRC:$rS, GPRC:$rB)>;
1434 def : Pat<(zextloadi1 iaddr:$src),
1436 def : Pat<(zextloadi1 xaddr:$src),
1438 def : Pat<(extloadi1 iaddr:$src),
1440 def : Pat<(extloadi1 xaddr:$src),
1442 def : Pat<(extloadi8 iaddr:$src),
1444 def : Pat<(extloadi8 xaddr:$src),
1446 def : Pat<(extloadi16 iaddr:$src),
1448 def : Pat<(extloadi16 xaddr:$src),
1450 def : Pat<(f64 (extloadf32 iaddr:$src)),
1451 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1452 def : Pat<(f64 (extloadf32 xaddr:$src)),
1453 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1455 def : Pat<(f64 (fextend F4RC:$src)),
1456 (COPY_TO_REGCLASS F4RC:$src, F8RC)>;
1459 def : Pat<(membarrier (i32 imm /*ll*/),
1463 (i32 imm /*device*/)),
1466 include "PPCInstrAltivec.td"
1467 include "PPCInstr64Bit.td"