1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC specific transformation functions and pattern fragments.
21 def GET_ZERO : SDNodeXForm<imm, [{
22 // Transformation function: get the low 16 bits.
25 def GET_32 : SDNodeXForm<imm, [{
26 // Transformation function: get the low 16 bits.
30 def LO16 : SDNodeXForm<imm, [{
31 // Transformation function: get the low 16 bits.
32 return getI32Imm((unsigned short)N->getValue());
35 def HI16 : SDNodeXForm<imm, [{
36 // Transformation function: shift the immediate value down into the low bits.
37 return getI32Imm((unsigned)N->getValue() >> 16);
40 def HA16 : SDNodeXForm<imm, [{
41 // Transformation function: shift the immediate value down into the low bits.
42 signed int Val = N->getValue();
43 return getI32Imm((Val - (signed short)Val) >> 16);
47 def immSExt16 : PatLeaf<(imm), [{
48 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
49 // field. Used by instructions like 'addi'.
50 return (int)N->getValue() == (short)N->getValue();
52 def immZExt16 : PatLeaf<(imm), [{
53 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
54 // field. Used by instructions like 'ori'.
55 return (unsigned)N->getValue() == (unsigned short)N->getValue();
58 def imm16Shifted : PatLeaf<(imm), [{
59 // imm16Shifted predicate - True if only bits in the top 16-bits of the
60 // immediate are set. Used by instructions like 'addis'.
61 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
65 // Example of a legalize expander: Only for PPC64.
66 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
67 [(set f64:$tmp , (FCTIDZ f64:$src)),
68 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
69 (store f64:$tmp, i32:$tmpFI),
70 (set i64:$dst, (load i32:$tmpFI))],
74 //===----------------------------------------------------------------------===//
75 // PowerPC Flag Definitions.
77 class isPPC64 { bit PPC64 = 1; }
78 class isVMX { bit VMX = 1; }
80 list<Register> Defs = [CR0];
86 //===----------------------------------------------------------------------===//
87 // PowerPC Operand Definitions.
89 def u5imm : Operand<i32> {
90 let PrintMethod = "printU5ImmOperand";
92 def u6imm : Operand<i32> {
93 let PrintMethod = "printU6ImmOperand";
95 def s16imm : Operand<i32> {
96 let PrintMethod = "printS16ImmOperand";
98 def u16imm : Operand<i32> {
99 let PrintMethod = "printU16ImmOperand";
101 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
102 let PrintMethod = "printS16X4ImmOperand";
104 def target : Operand<i32> {
105 let PrintMethod = "printBranchOperand";
107 def piclabel: Operand<i32> {
108 let PrintMethod = "printPICLabel";
110 def symbolHi: Operand<i32> {
111 let PrintMethod = "printSymbolHi";
113 def symbolLo: Operand<i32> {
114 let PrintMethod = "printSymbolLo";
116 def crbitm: Operand<i8> {
117 let PrintMethod = "printcrbitm";
122 //===----------------------------------------------------------------------===//
123 // PowerPC Instruction Definitions.
125 // Pseudo-instructions:
126 def PHI : Pseudo<(ops variable_ops), "; PHI">;
129 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN">;
130 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP">;
132 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
133 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8">;
134 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4">;
136 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
137 // scheduler into a branch sequence.
138 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
139 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
140 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
141 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
142 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
143 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
144 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
148 let isTerminator = 1 in {
150 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">;
151 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">;
155 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
157 let isBranch = 1, isTerminator = 1 in {
158 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
159 target:$true, target:$false),
161 def B : IForm<18, 0, 0, (ops target:$func), "b $func">;
162 //def BA : IForm<18, 1, 0, (ops target:$func), "ba $func">;
163 def BL : IForm<18, 0, 1, (ops target:$func), "bl $func">;
164 //def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func">;
166 // FIXME: 4*CR# needs to be added to the BI field!
167 // This will only work for CR0 as it stands now
168 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
170 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
172 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
174 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
176 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
178 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
183 // All calls clobber the non-callee saved registers...
184 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
185 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
187 CR0,CR1,CR5,CR6,CR7] in {
188 // Convenient aliases for call instructions
189 def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops), "bl $func">;
190 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1,
191 (ops variable_ops), "bctrl">;
194 // D-Form instructions. Most instructions that perform an operation on a
195 // register and an immediate are of this type.
198 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
199 "lbz $rD, $disp($rA)">;
200 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
201 "lha $rD, $disp($rA)">;
202 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
203 "lhz $rD, $disp($rA)">;
204 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
205 "lmw $rD, $disp($rA)">;
206 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
207 "lwz $rD, $disp($rA)">;
208 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
209 "lwzu $rD, $disp($rA)">;
211 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
212 "addi $rD, $rA, $imm",
213 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
214 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
215 "addic $rD, $rA, $imm",
217 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
218 "addic. $rD, $rA, $imm",
220 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
221 "addis $rD, $rA, $imm",
222 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
223 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
226 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
227 "mulli $rD, $rA, $imm",
228 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
229 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
230 "subfic $rD, $rA, $imm",
231 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
232 def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
234 [(set GPRC:$rD, immSExt16:$imm)]>;
235 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
237 [(set GPRC:$rD, imm16Shifted:$imm)]>;
239 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
240 "stmw $rS, $disp($rA)">;
241 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
242 "stb $rS, $disp($rA)">;
243 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
244 "sth $rS, $disp($rA)">;
245 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
246 "stw $rS, $disp($rA)">;
247 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
248 "stwu $rS, $disp($rA)">;
250 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
251 "andi. $dst, $src1, $src2",
253 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
254 "andis. $dst, $src1, $src2",
256 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
257 "ori $dst, $src1, $src2",
258 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
259 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
260 "oris $dst, $src1, $src2",
261 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
262 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
263 "xori $dst, $src1, $src2",
264 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
265 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
266 "xoris $dst, $src1, $src2",
267 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
268 def NOP : DForm_4_zero<24, (ops), "nop">;
269 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
270 "cmpi $crD, $L, $rA, $imm">;
271 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
272 "cmpwi $crD, $rA, $imm">;
273 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
274 "cmpdi $crD, $rA, $imm">, isPPC64;
275 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
276 "cmpli $dst, $size, $src1, $src2">;
277 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
278 "cmplwi $dst, $src1, $src2">;
279 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
280 "cmpldi $dst, $src1, $src2">, isPPC64;
282 def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
283 "lfs $rD, $disp($rA)">;
284 def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
285 "lfd $rD, $disp($rA)">;
288 def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
289 "stfs $rS, $disp($rA)">;
290 def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
291 "stfd $rS, $disp($rA)">;
294 // DS-Form instructions. Load/Store instructions available in PPC-64
297 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
298 "lwa $rT, $DS($rA)">, isPPC64;
299 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
300 "ld $rT, $DS($rA)">, isPPC64;
303 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
304 "std $rT, $DS($rA)">, isPPC64;
305 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
306 "stdu $rT, $DS($rA)">, isPPC64;
309 // X-Form instructions. Most instructions that perform an operation on a
310 // register and another register are of this type.
313 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
314 "lbzx $dst, $base, $index">;
315 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
316 "lhax $dst, $base, $index">;
317 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
318 "lhzx $dst, $base, $index">;
319 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
320 "lwax $dst, $base, $index">, isPPC64;
321 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
322 "lwzx $dst, $base, $index">;
323 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
324 "ldx $dst, $base, $index">, isPPC64;
326 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
327 "nand $rA, $rS, $rB",
328 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
329 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
331 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
332 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
333 "and. $rA, $rS, $rB",
335 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
336 "andc $rA, $rS, $rB",
337 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
338 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
340 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
341 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
343 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
344 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
347 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
350 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
352 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
353 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
356 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
358 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
359 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
361 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
362 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
364 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
365 def SLD : XForm_6<31, 27, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
368 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
370 [(set GPRC:$rA, (shl GPRC:$rS, GPRC:$rB))]>;
371 def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
374 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
376 [(set GPRC:$rA, (srl GPRC:$rS, GPRC:$rB))]>;
377 def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
378 "srad $rA, $rS, $rB",
380 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
381 "sraw $rA, $rS, $rB",
382 [(set GPRC:$rA, (sra GPRC:$rS, GPRC:$rB))]>;
384 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
385 "stbx $rS, $rA, $rB">;
386 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
387 "sthx $rS, $rA, $rB">;
388 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
389 "stwx $rS, $rA, $rB">;
390 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
391 "stwux $rS, $rA, $rB">;
392 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
393 "stdx $rS, $rA, $rB">, isPPC64;
394 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
395 "stdux $rS, $rA, $rB">, isPPC64;
397 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
398 "srawi $rA, $rS, $SH",
399 [(set GPRC:$rA, (sra GPRC:$rS, imm:$SH))]>;
400 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
402 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
403 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
405 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
406 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
408 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
409 def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
412 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
413 "cmp $crD, $long, $rA, $rB">;
414 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
415 "cmpl $crD, $long, $rA, $rB">;
416 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
417 "cmpw $crD, $rA, $rB">;
418 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
419 "cmpd $crD, $rA, $rB">, isPPC64;
420 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
421 "cmplw $crD, $rA, $rB">;
422 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
423 "cmpld $crD, $rA, $rB">, isPPC64;
424 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
425 // "fcmpo $crD, $fA, $fB">;
426 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
427 "fcmpu $crD, $fA, $fB">;
428 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
429 "fcmpu $crD, $fA, $fB">;
432 def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
433 "lfsx $dst, $base, $index">;
434 def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
435 "lfdx $dst, $base, $index">;
437 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
440 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
443 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
446 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
448 [(set F4RC:$frD, (fround F8RC:$frB))]>;
449 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
451 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
452 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
454 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
456 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
457 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
459 []>; // (set F4RC:$frD, F4RC:$frB)
460 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
462 []>; // (set F8RC:$frD, F8RC:$frB)
463 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
465 [(set F8RC:$frD, (fextend F4RC:$frB))]>;
467 // These are artificially split into two different forms, for 4/8 byte FP.
468 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
470 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
471 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
473 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
474 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
476 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
477 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
479 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
480 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
482 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
483 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
485 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
489 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
490 "stfsx $frS, $rA, $rB">;
491 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
492 "stfdx $frS, $rA, $rB">;
495 // XL-Form instructions. condition register logical ops.
497 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
500 // XFX-Form instructions. Instructions that deal with SPRs
502 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
503 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
504 // which means the SPR value needs to be multiplied by a factor of 32.
505 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT">;
506 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT">;
507 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">;
508 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
510 def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
512 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">;
513 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;
515 // XS-Form instructions. Just 'sradi'
517 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
518 "sradi $rA, $rS, $SH">, isPPC64;
520 // XO-Form instructions. Arithmetic instructions that can set overflow bit
522 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
524 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
525 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
527 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
528 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
529 "addc $rT, $rA, $rB",
531 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
532 "adde $rT, $rA, $rB",
534 def DIVD : XOForm_1<31, 489, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
535 "divd $rT, $rA, $rB",
537 def DIVDU : XOForm_1<31, 457, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
538 "divdu $rT, $rA, $rB",
540 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
541 "divw $rT, $rA, $rB",
542 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
543 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
544 "divwu $rT, $rA, $rB",
545 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
546 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
547 "mulhw $rT, $rA, $rB",
548 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
549 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
550 "mulhwu $rT, $rA, $rB",
551 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
552 def MULLD : XOForm_1<31, 233, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
553 "mulld $rT, $rA, $rB",
555 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
556 "mullw $rT, $rA, $rB",
557 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
558 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
559 "subf $rT, $rA, $rB",
560 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
561 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
562 "subfc $rT, $rA, $rB",
564 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
565 "subfe $rT, $rA, $rB",
567 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
570 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
573 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
575 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
576 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
580 // A-Form instructions. Most of the instructions executed in the FPU are of
583 def FMADD : AForm_1<63, 29,
584 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
585 "fmadd $FRT, $FRA, $FRC, $FRB",
586 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
588 def FMADDS : AForm_1<59, 29,
589 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
590 "fmadds $FRT, $FRA, $FRC, $FRB",
591 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
593 def FMSUB : AForm_1<63, 28,
594 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
595 "fmsub $FRT, $FRA, $FRC, $FRB",
596 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
598 def FMSUBS : AForm_1<59, 28,
599 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
600 "fmsubs $FRT, $FRA, $FRC, $FRB",
601 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
603 def FNMADD : AForm_1<63, 31,
604 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
605 "fnmadd $FRT, $FRA, $FRC, $FRB",
606 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
608 def FNMADDS : AForm_1<59, 31,
609 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
610 "fnmadds $FRT, $FRA, $FRC, $FRB",
611 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
613 def FNMSUB : AForm_1<63, 30,
614 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
615 "fnmsub $FRT, $FRA, $FRC, $FRB",
616 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
618 def FNMSUBS : AForm_1<59, 30,
619 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
620 "fnmsubs $FRT, $FRA, $FRC, $FRB",
621 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
623 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
624 // having 4 of these, force the comparison to always be an 8-byte double (code
625 // should use an FMRSD if the input comparison value really wants to be a float)
626 // and 4/8 byte forms for the result and operand type..
627 def FSELD : AForm_1<63, 23,
628 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
629 "fsel $FRT, $FRA, $FRC, $FRB",
631 def FSELS : AForm_1<63, 23,
632 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
633 "fsel $FRT, $FRA, $FRC, $FRB",
635 def FADD : AForm_2<63, 21,
636 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
637 "fadd $FRT, $FRA, $FRB",
638 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
639 def FADDS : AForm_2<59, 21,
640 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
641 "fadds $FRT, $FRA, $FRB",
642 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
643 def FDIV : AForm_2<63, 18,
644 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
645 "fdiv $FRT, $FRA, $FRB",
646 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
647 def FDIVS : AForm_2<59, 18,
648 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
649 "fdivs $FRT, $FRA, $FRB",
650 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
651 def FMUL : AForm_3<63, 25,
652 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
653 "fmul $FRT, $FRA, $FRB",
654 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
655 def FMULS : AForm_3<59, 25,
656 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
657 "fmuls $FRT, $FRA, $FRB",
658 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
659 def FSUB : AForm_2<63, 20,
660 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
661 "fsub $FRT, $FRA, $FRB",
662 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
663 def FSUBS : AForm_2<59, 20,
664 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
665 "fsubs $FRT, $FRA, $FRB",
666 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
668 // M-Form instructions. rotate and mask instructions.
670 let isTwoAddress = 1, isCommutable = 1 in {
671 // RLWIMI can be commuted if the rotate amount is zero.
672 def RLWIMI : MForm_2<20,
673 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
674 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
675 def RLDIMI : MDForm_1<30, 3,
676 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
677 "rldimi $rA, $rS, $SH, $MB">, isPPC64;
679 def RLWINM : MForm_2<21,
680 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
681 "rlwinm $rA, $rS, $SH, $MB, $ME">;
682 def RLWINMo : MForm_2<21,
683 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
684 "rlwinm. $rA, $rS, $SH, $MB, $ME">, isDOT;
685 def RLWNM : MForm_2<23,
686 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
687 "rlwnm $rA, $rS, $rB, $MB, $ME">;
689 // MD-Form instructions. 64 bit rotate instructions.
691 def RLDICL : MDForm_1<30, 0,
692 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
693 "rldicl $rA, $rS, $SH, $MB">, isPPC64;
694 def RLDICR : MDForm_1<30, 1,
695 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
696 "rldicr $rA, $rS, $SH, $ME">, isPPC64;
698 //===----------------------------------------------------------------------===//
699 // PowerPC Instruction Patterns
702 // Arbitrary immediate support. Implement in terms of LIS/ORI.
703 def : Pat<(i32 imm:$imm),
704 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
706 // Implement the 'not' operation with the NOR instruction.
707 def NOT : Pat<(not GPRC:$in),
708 (NOR GPRC:$in, GPRC:$in)>;
710 // ADD an arbitrary immediate.
711 def : Pat<(add GPRC:$in, imm:$imm),
712 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
713 // OR an arbitrary immediate.
714 def : Pat<(or GPRC:$in, imm:$imm),
715 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
716 // XOR an arbitrary immediate.
717 def : Pat<(xor GPRC:$in, imm:$imm),
718 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
720 // Same as above, but using a temporary. FIXME: implement temporaries :)
722 def : Pattern<(xor GPRC:$in, imm:$imm),
723 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
724 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
728 //===----------------------------------------------------------------------===//
729 // PowerPCInstrInfo Definition
731 def PowerPCInstrInfo : InstrInfo {
734 let TSFlagsFields = [ "VMX", "PPC64" ];
735 let TSFlagsShifts = [ 0, 1 ];
737 let isLittleEndianEncoding = 1;