2 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
4 // The LLVM Compiler Infrastructure
6 // This file was developed by the LLVM research group and is distributed under
7 // the University of Illinois Open Source License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the subset of the 32-bit PowerPC instruction set, as used
12 // by the PowerPC instruction selector.
14 //===----------------------------------------------------------------------===//
16 include "PowerPCInstrFormats.td"
18 let isTerminator = 1 in {
20 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, 0, 0, (ops), "blr">;
21 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, 0, 0, (ops), "bctr">;
24 def u5imm : Operand<i8> {
25 let PrintMethod = "printU5ImmOperand";
27 def u6imm : Operand<i8> {
28 let PrintMethod = "printU6ImmOperand";
30 def s16imm : Operand<i16> {
31 let PrintMethod = "printS16ImmOperand";
33 def u16imm : Operand<i16> {
34 let PrintMethod = "printU16ImmOperand";
36 def target : Operand<i32> {
37 let PrintMethod = "printBranchOperand";
39 def piclabel: Operand<i32> {
40 let PrintMethod = "printPICLabel";
42 def symbolHi: Operand<i32> {
43 let PrintMethod = "printSymbolHi";
45 def symbolLo: Operand<i32> {
46 let PrintMethod = "printSymbolLo";
49 // Pseudo-instructions:
50 def PHI : Pseudo<(ops), "; PHI">;
52 def ADJCALLSTACKDOWN : Pseudo<(ops), "; ADJCALLSTACKDOWN">;
53 def ADJCALLSTACKUP : Pseudo<(ops), "; ADJCALLSTACKUP">;
55 def IMPLICIT_DEF : Pseudo<(ops), "; IMPLICIT_DEF">;
58 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
60 let isBranch = 1, isTerminator = 1 in {
61 def COND_BRANCH : Pseudo<(ops), "; COND_BRANCH">;
62 def B : IForm<18, 0, 0, 0, 0, (ops target:$func), "b $func">;
63 //def BA : IForm<18, 1, 0, 0, 0, (ops target:$func), "ba $func">;
64 def BL : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
65 //def BLA : IForm<18, 1, 1, 0, 0, (ops target:$func), "bla $func">;
67 // FIXME: 4*CR# needs to be added to the BI field!
68 // This will only work for CR0 as it stands now
69 def BLT : BForm_ext<16, 0, 0, 12, 0, 0, 0, (ops CRRC:$crS, target:$block),
71 def BLE : BForm_ext<16, 0, 0, 4, 1, 0, 0, (ops CRRC:$crS, target:$block),
73 def BEQ : BForm_ext<16, 0, 0, 12, 2, 0, 0, (ops CRRC:$crS, target:$block),
75 def BGE : BForm_ext<16, 0, 0, 4, 0, 0, 0, (ops CRRC:$crS, target:$block),
77 def BGT : BForm_ext<16, 0, 0, 12, 1, 0, 0, (ops CRRC:$crS, target:$block),
79 def BNE : BForm_ext<16, 0, 0, 4, 2, 0, 0, (ops CRRC:$crS, target:$block),
83 let isBranch = 1, isTerminator = 1, isCall = 1,
84 // All calls clobber the non-callee saved registers...
85 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
86 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
88 CR0,CR1,CR5,CR6,CR7] in {
89 // Convenient aliases for call instructions
90 def CALLpcrel : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
91 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1, 0, 0, (ops), "bctrl">;
94 // D-Form instructions. Most instructions that perform an operation on a
95 // register and an immediate are of this type.
98 def LBZ : DForm_1<34, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
99 "lbz $rD, $disp($rA)">;
100 def LHA : DForm_1<42, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
101 "lha $rD, $disp($rA)">;
102 def LHZ : DForm_1<40, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
103 "lhz $rD, $disp($rA)">;
104 def LMW : DForm_1<46, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
105 "lmw $rD, $disp($rA)">;
106 def LWZ : DForm_1<32, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
107 "lwz $rD, $disp($rA)">;
108 def LWZU : DForm_1<35, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
109 "lwzu $rD, $disp($rA)">;
111 def ADDI : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
112 "addi $rD, $rA, $imm">;
113 def ADDIC : DForm_2<12, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
114 "addic $rD, $rA, $imm">;
115 def ADDICo : DForm_2<13, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
116 "addic. $rD, $rA, $imm">;
117 def ADDIS : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
118 "addis $rD, $rA, $imm">;
119 def LA : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
120 "la $rD, $sym($rA)">;
121 def LOADHiAddr : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolHi:$sym),
122 "addis $rD, $rA, $sym">;
123 def MULLI : DForm_2< 7, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
124 "mulli $rD, $rA, $imm">;
125 def SUBFIC : DForm_2< 8, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
126 "subfic $rD, $rA, $imm">;
127 def LI : DForm_2_r0<14, 0, 0, (ops GPRC:$rD, s16imm:$imm),
129 def LIS : DForm_2_r0<15, 0, 0, (ops GPRC:$rD, s16imm:$imm),
132 def STMW : DForm_3<47, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
133 "stmw $rS, $disp($rA)">;
134 def STB : DForm_3<38, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
135 "stb $rS, $disp($rA)">;
136 def STH : DForm_3<44, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
137 "sth $rS, $disp($rA)">;
138 def STW : DForm_3<36, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
139 "stw $rS, $disp($rA)">;
140 def STWU : DForm_3<37, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
141 "stwu $rS, $disp($rA)">;
143 let Defs = [CR0] in {
144 def ANDIo : DForm_4<28, 0, 0,
145 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
146 "andi. $dst, $src1, $src2">;
147 def ANDISo : DForm_4<29, 0, 0,
148 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
149 "andis. $dst, $src1, $src2">;
151 def ORI : DForm_4<24, 0, 0,
152 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
153 "ori $dst, $src1, $src2">;
154 def ORIS : DForm_4<25, 0, 0,
155 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
156 "oris $dst, $src1, $src2">;
157 def XORI : DForm_4<26, 0, 0,
158 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
159 "xori $dst, $src1, $src2">;
160 def XORIS : DForm_4<27, 0, 0,
161 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
162 "xoris $dst, $src1, $src2">;
163 def NOP : DForm_4_zero<24, 0, 0, (ops), "nop">;
164 def CMPI : DForm_5<11, 0, 0, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
165 "cmpi $crD, $L, $rA, $imm">;
166 def CMPWI : DForm_5_ext<11, 0, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
167 "cmpwi $crD, $rA, $imm">;
168 def CMPDI : DForm_5_ext<11, 1, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
169 "cmpdi $crD, $rA, $imm">;
170 def CMPLI : DForm_6<10, 0, 0,
171 (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
172 "cmpli $dst, $size, $src1, $src2">;
173 def CMPLWI : DForm_6_ext<10, 0, 0,
174 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
175 "cmplwi $dst, $src1, $src2">;
176 def CMPLDI : DForm_6_ext<10, 1, 0,
177 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
178 "cmpldi $dst, $src1, $src2">;
180 def LFS : DForm_8<48, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
181 "lfs $rD, $disp($rA)">;
182 def LFD : DForm_8<50, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
183 "lfd $rD, $disp($rA)">;
186 def STFS : DForm_9<52, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
187 "stfs $rS, $disp($rA)">;
188 def STFD : DForm_9<54, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
189 "stfd $rS, $disp($rA)">;
192 // DS-Form instructions. Load/Store instructions available in PPC-64
195 def LWA : DSForm_1<58, 2, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
196 "lwa $rT, $DS($rA)">;
197 def LD : DSForm_2<58, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
201 def STD : DSForm_2<62, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
202 "std $rT, $DS($rA)">;
203 def STDU : DSForm_2<62, 1, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
204 "stdu $rT, $DS($rA)">;
207 // X-Form instructions. Most instructions that perform an operation on a
208 // register and another register are of this type.
211 def LBZX : XForm_1<31, 87, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
212 "lbzx $dst, $base, $index">;
213 def LHAX : XForm_1<31, 343, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
214 "lhax $dst, $base, $index">;
215 def LHZX : XForm_1<31, 279, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
216 "lhzx $dst, $base, $index">;
217 def LWAX : XForm_1<31, 341, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
218 "lwax $dst, $base, $index">;
219 def LWZX : XForm_1<31, 23, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
220 "lwzx $dst, $base, $index">;
221 def LDX : XForm_1<31, 21, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
222 "ldx $dst, $base, $index">;
224 def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
225 "and $rA, $rS, $rB">;
227 def ANDo : XForm_6<31, 28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
228 "and. $rA, $rS, $rB">;
229 def ANDC : XForm_6<31, 60, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
230 "andc $rA, $rS, $rB">;
231 def EQV : XForm_6<31, 284, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
232 "eqv $rA, $rS, $rB">;
233 def NAND : XForm_6<31, 476, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
234 "nand $rA, $rS, $rB">;
235 def NOR : XForm_6<31, 124, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
236 "nor $rA, $rS, $rB">;
237 def OR : XForm_6<31, 444, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
240 def ORo : XForm_6<31, 444, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
241 "or. $rA, $rS, $rB">;
242 def ORC : XForm_6<31, 412, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
243 "orc $rA, $rS, $rB">;
244 def SLD : XForm_6<31, 27, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
245 "sld $rA, $rS, $rB">;
246 def SLW : XForm_6<31, 24, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
247 "slw $rA, $rS, $rB">;
248 def SRD : XForm_6<31, 539, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
249 "srd $rA, $rS, $rB">;
250 def SRW : XForm_6<31, 536, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
251 "srw $rA, $rS, $rB">;
252 def SRAD : XForm_6<31, 794, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
253 "srad $rA, $rS, $rB">;
254 def SRAW : XForm_6<31, 792, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
255 "sraw $rA, $rS, $rB">;
256 def XOR : XForm_6<31, 316, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
257 "xor $rA, $rS, $rB">;
259 def STBX : XForm_8<31, 215, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
260 "stbx $rS, $rA, $rB">;
261 def STHX : XForm_8<31, 407, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
262 "sthx $rS, $rA, $rB">;
263 def STWX : XForm_8<31, 151, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
264 "stwx $rS, $rA, $rB">;
265 def STWUX : XForm_8<31, 183, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
266 "stwux $rS, $rA, $rB">;
267 def STDX : XForm_8<31, 149, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
268 "stdx $rS, $rA, $rB">;
269 def STDUX : XForm_8<31, 181, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
270 "stdux $rS, $rA, $rB">;
272 def SRAWI : XForm_10<31, 824, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
273 "srawi $rA, $rS, $SH">;
274 def CNTLZW : XForm_11<31, 26, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
276 def EXTSB : XForm_11<31, 954, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
278 def EXTSH : XForm_11<31, 922, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
280 def EXTSW : XForm_11<31, 986, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS),
282 def CMP : XForm_16<31, 0, 0, 0,
283 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
284 "cmp $crD, $long, $rA, $rB">;
285 def CMPL : XForm_16<31, 32, 0, 0,
286 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
287 "cmpl $crD, $long, $rA, $rB">;
288 def CMPW : XForm_16_ext<31, 0, 0, 0,
289 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
290 "cmpw $crD, $rA, $rB">;
291 def CMPD : XForm_16_ext<31, 0, 1, 0,
292 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
293 "cmpd $crD, $rA, $rB">;
294 def CMPLW : XForm_16_ext<31, 32, 0, 0,
295 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
296 "cmplw $crD, $rA, $rB">;
297 def CMPLD : XForm_16_ext<31, 32, 1, 0,
298 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
299 "cmpld $crD, $rA, $rB">;
300 def FCMPO : XForm_17<63, 32, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
301 "fcmpo $crD, $fA, $fB">;
302 def FCMPU : XForm_17<63, 0, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
303 "fcmpu $crD, $fA, $fB">;
305 def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
306 "lfsx $dst, $base, $index">;
307 def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
308 "lfdx $dst, $base, $index">;
310 def FCFID : XForm_26<63, 846, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
312 def FCTIDZ : XForm_26<63, 815, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
313 "fctidz $frD, $frB">;
314 def FCTIWZ : XForm_26<63, 15, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
315 "fctiwz $frD, $frB">;
316 def FABS : XForm_26<63, 264, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
318 def FMR : XForm_26<63, 72, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
320 def FNABS : XForm_26<63, 136, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
322 def FNEG : XForm_26<63, 40, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
324 def FRSP : XForm_26<63, 12, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
327 def STFSX : XForm_28<31, 663, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
328 "stfsx $frS, $rA, $rB">;
329 def STFDX : XForm_28<31, 727, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
330 "stfdx $frS, $rA, $rB">;
333 // XL-Form instructions. condition register logical ops.
335 def CRAND : XLForm_1<19, 257, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
337 def CRANDC : XLForm_1<19, 129, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
338 "crandc $D, $A, $B">;
339 def CRNOR : XLForm_1<19, 33, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
341 def CROR : XLForm_1<19, 449, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
343 def MCRF : XLForm_3<19, 0, 0, 0, (ops CRRC:$BF, CRRC:$BFA),
346 // XFX-Form instructions. Instructions that deal with SPRs
348 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
349 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
350 // which means the SPR value needs to be multiplied by a factor of 32.
351 def MFCTR : XFXForm_1_ext<31, 339, 288, 0, 0, (ops GPRC:$rT), "mfctr $rT">;
352 def MFLR : XFXForm_1_ext<31, 339, 256, 0, 0, (ops GPRC:$rT), "mflr $rT">;
353 def MFCR : XFXForm_3<31, 19, 0, 0, (ops GPRC:$rT), "mfcr $rT">;
354 def MTCRF : XFXForm_5<31, 144, 0, 0, (ops CRRC:$FXM, GPRC:$rS),
356 def MTCTR : XFXForm_7_ext<31, 467, 288, 0, 0, (ops GPRC:$rS), "mtctr $rS">;
357 def MTLR : XFXForm_7_ext<31, 467, 256, 0, 0, (ops GPRC:$rS), "mtlr $rS">;
359 // XS-Form instructions. Just 'sradi'
361 def SRADI : XSForm_1<31, 413, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
362 "sradi $rA, $rS, $SH">;
364 // XO-Form instructions. Arithmetic instructions that can set overflow bit
366 def ADD : XOForm_1<31, 266, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
367 "add $rT, $rA, $rB">;
368 def ADDC : XOForm_1<31, 10, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
369 "addc $rT, $rA, $rB">;
370 def ADDE : XOForm_1<31, 138, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
371 "adde $rT, $rA, $rB">;
372 def DIVD : XOForm_1<31, 489, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
373 "divd $rT, $rA, $rB">;
374 def DIVDU : XOForm_1<31, 457, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
375 "divdu $rT, $rA, $rB">;
376 def DIVW : XOForm_1<31, 491, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
377 "divw $rT, $rA, $rB">;
378 def DIVWU : XOForm_1<31, 459, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
379 "divwu $rT, $rA, $rB">;
380 def MULHW : XOForm_1<31, 75, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
381 "mulhw $rT, $rA, $rB">;
382 def MULHWU : XOForm_1<31, 11, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
383 "mulhwu $rT, $rA, $rB">;
384 def MULLD : XOForm_1<31, 233, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
385 "mulld $rT, $rA, $rB">;
386 def MULLW : XOForm_1<31, 235, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
387 "mullw $rT, $rA, $rB">;
388 def SUBF : XOForm_1<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
389 "subf $rT, $rA, $rB">;
390 def SUBFC : XOForm_1<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
391 "subfc $rT, $rA, $rB">;
392 def SUBFE : XOForm_1<31, 136, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
393 "subfe $rT, $rA, $rB">;
394 def SUB : XOForm_1r<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
395 "sub $rT, $rA, $rB">;
396 def ADDME : XOForm_3<31, 234, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
398 def ADDZE : XOForm_3<31, 202, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
400 def NEG : XOForm_3<31, 104, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
402 def SUBFZE : XOForm_3<31, 200, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
405 // A-Form instructions. Most of the instructions executed in the FPU are of
408 def FMADD : AForm_1<63, 29, 0, 0, 0,
409 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
410 "fmadd $FRT, $FRA, $FRC, $FRB">;
411 def FMADDS : AForm_1<59, 29, 0, 0, 0,
412 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
413 "fmadds $FRT, $FRA, $FRC, $FRB">;
414 def FMSUB : AForm_1<63, 28, 0, 0, 0,
415 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
416 "fmsub $FRT, $FRA, $FRC, $FRB">;
417 def FMSUBS : AForm_1<59, 28, 0, 0, 0,
418 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
419 "fmsubs $FRT, $FRA, $FRC, $FRB">;
420 def FNMADD : AForm_1<63, 31, 0, 0, 0,
421 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
422 "fnmadd $FRT, $FRA, $FRC, $FRB">;
423 def FNMADDS : AForm_1<59, 31, 0, 0, 0,
424 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
425 "fnmadds $FRT, $FRA, $FRC, $FRB">;
426 def FNMSUB : AForm_1<63, 30, 0, 0, 0,
427 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
428 "fnmsub $FRT, $FRA, $FRC, $FRB">;
429 def FNMSUBS : AForm_1<59, 30, 0, 0, 0,
430 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
431 "fnmsubs $FRT, $FRA, $FRC, $FRB">;
432 def FSEL : AForm_1<63, 23, 0, 0, 0,
433 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
434 "fsel $FRT, $FRA, $FRC, $FRB">;
435 def FADD : AForm_2<63, 21, 0, 0, 0,
436 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
437 "fadd $FRT, $FRA, $FRB">;
438 def FADDS : AForm_2<59, 21, 0, 0, 0,
439 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
440 "fadds $FRT, $FRA, $FRB">;
441 def FDIV : AForm_2<63, 18, 0, 0, 0,
442 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
443 "fdiv $FRT, $FRA, $FRB">;
444 def FDIVS : AForm_2<59, 18, 0, 0, 0,
445 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
446 "fdivs $FRT, $FRA, $FRB">;
447 def FMUL : AForm_3<63, 25, 0, 0, 0,
448 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
449 "fmul $FRT, $FRA, $FRB">;
450 def FMULS : AForm_3<59, 25, 0, 0, 0,
451 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
452 "fmuls $FRT, $FRA, $FRB">;
453 def FSUB : AForm_2<63, 20, 0, 0, 0,
454 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
455 "fsub $FRT, $FRA, $FRB">;
456 def FSUBS : AForm_2<59, 20, 0, 0, 0,
457 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
458 "fsubs $FRT, $FRA, $FRB">;
460 // M-Form instructions. rotate and mask instructions.
462 let isTwoAddress = 1 in {
463 def RLWIMI : MForm_2<20, 0, 0, 0,
464 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
465 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
467 def RLWINM : MForm_2<21, 0, 0, 0,
468 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
469 "rlwinm $rA, $rS, $SH, $MB, $ME">;
471 def RLWINMo : MForm_2<21, 1, 0, 0,
472 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
473 "rlwinm. $rA, $rS, $SH, $MB, $ME">;
474 def RLWNM : MForm_2<23, 0, 0, 0,
475 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
476 "rlwnm $rA, $rS, $rB, $MB, $ME">;
478 // MD-Form instructions. 64 bit rotate instructions.
480 def RLDICL : MDForm_1<30, 0, 0, 1, 0,
481 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
482 "rldicl $rA, $rS, $SH, $MB">;
483 def RLDICR : MDForm_1<30, 1, 0, 1, 0,
484 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
485 "rldicr $rA, $rS, $SH, $ME">;
487 def PowerPCInstrInfo : InstrInfo {
490 let TSFlagsFields = [ "VMX", "PPC64" ];
491 let TSFlagsShifts = [ 0, 1 ];
493 let isLittleEndianEncoding = 1;