1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific DAG Nodes.
21 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
22 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
23 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
25 def PPCfsel : SDNode<"PPCISD::FSEL",
26 // Type constraint for fsel.
27 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
28 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
30 //===----------------------------------------------------------------------===//
31 // PowerPC specific transformation functions and pattern fragments.
34 def SHL32 : SDNodeXForm<imm, [{
35 // Transformation function: 31 - imm
36 return getI32Imm(31 - N->getValue());
39 def SHL64 : SDNodeXForm<imm, [{
40 // Transformation function: 63 - imm
41 return getI32Imm(63 - N->getValue());
44 def SRL32 : SDNodeXForm<imm, [{
45 // Transformation function: 32 - imm
46 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
49 def SRL64 : SDNodeXForm<imm, [{
50 // Transformation function: 64 - imm
51 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
54 def LO16 : SDNodeXForm<imm, [{
55 // Transformation function: get the low 16 bits.
56 return getI32Imm((unsigned short)N->getValue());
59 def HI16 : SDNodeXForm<imm, [{
60 // Transformation function: shift the immediate value down into the low bits.
61 return getI32Imm((unsigned)N->getValue() >> 16);
64 def HA16 : SDNodeXForm<imm, [{
65 // Transformation function: shift the immediate value down into the low bits.
66 signed int Val = N->getValue();
67 return getI32Imm((Val - (signed short)Val) >> 16);
71 def immSExt16 : PatLeaf<(imm), [{
72 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
73 // field. Used by instructions like 'addi'.
74 return (int)N->getValue() == (short)N->getValue();
76 def immZExt16 : PatLeaf<(imm), [{
77 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
78 // field. Used by instructions like 'ori'.
79 return (unsigned)N->getValue() == (unsigned short)N->getValue();
82 def imm16Shifted : PatLeaf<(imm), [{
83 // imm16Shifted predicate - True if only bits in the top 16-bits of the
84 // immediate are set. Used by instructions like 'addis'.
85 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
89 // Example of a legalize expander: Only for PPC64.
90 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
91 [(set f64:$tmp , (FCTIDZ f64:$src)),
92 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
93 (store f64:$tmp, i32:$tmpFI),
94 (set i64:$dst, (load i32:$tmpFI))],
98 //===----------------------------------------------------------------------===//
99 // PowerPC Flag Definitions.
101 class isPPC64 { bit PPC64 = 1; }
102 class isVMX { bit VMX = 1; }
104 list<Register> Defs = [CR0];
110 //===----------------------------------------------------------------------===//
111 // PowerPC Operand Definitions.
113 def u5imm : Operand<i32> {
114 let PrintMethod = "printU5ImmOperand";
116 def u6imm : Operand<i32> {
117 let PrintMethod = "printU6ImmOperand";
119 def s16imm : Operand<i32> {
120 let PrintMethod = "printS16ImmOperand";
122 def u16imm : Operand<i32> {
123 let PrintMethod = "printU16ImmOperand";
125 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
126 let PrintMethod = "printS16X4ImmOperand";
128 def target : Operand<i32> {
129 let PrintMethod = "printBranchOperand";
131 def piclabel: Operand<i32> {
132 let PrintMethod = "printPICLabel";
134 def symbolHi: Operand<i32> {
135 let PrintMethod = "printSymbolHi";
137 def symbolLo: Operand<i32> {
138 let PrintMethod = "printSymbolLo";
140 def crbitm: Operand<i8> {
141 let PrintMethod = "printcrbitm";
146 //===----------------------------------------------------------------------===//
147 // PowerPC Instruction Definitions.
149 // Pseudo-instructions:
150 def PHI : Pseudo<(ops variable_ops), "; PHI", []>;
153 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN", []>;
154 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP", []>;
156 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
157 [(set GPRC:$rD, (undef))]>;
158 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8",
159 [(set F8RC:$rD, (undef))]>;
160 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4",
161 [(set F4RC:$rD, (undef))]>;
163 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
164 // scheduler into a branch sequence.
165 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
166 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
167 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
168 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
169 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
170 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
171 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
175 let isTerminator = 1 in {
177 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB>;
178 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB>;
182 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>;
184 let isBranch = 1, isTerminator = 1 in {
185 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
186 target:$true, target:$false),
187 "; COND_BRANCH", []>;
188 def B : IForm<18, 0, 0, (ops target:$func), "b $func", BrB>;
189 //def BA : IForm<18, 1, 0, (ops target:$func), "ba $func", BrB>;
190 def BL : IForm<18, 0, 1, (ops target:$func), "bl $func", BrB>;
191 //def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func", BrB>;
193 // FIXME: 4*CR# needs to be added to the BI field!
194 // This will only work for CR0 as it stands now
195 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
196 "blt $crS, $block", BrB>;
197 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
198 "ble $crS, $block", BrB>;
199 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
200 "beq $crS, $block", BrB>;
201 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
202 "bge $crS, $block", BrB>;
203 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
204 "bgt $crS, $block", BrB>;
205 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
206 "bne $crS, $block", BrB>;
207 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
208 "bun $crS, $block", BrB>;
209 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
210 "bnu $crS, $block", BrB>;
214 // All calls clobber the non-callee saved registers...
215 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
216 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
218 CR0,CR1,CR5,CR6,CR7] in {
219 // Convenient aliases for call instructions
220 def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops),
222 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1,
223 (ops variable_ops), "bctrl", BrB>;
226 // D-Form instructions. Most instructions that perform an operation on a
227 // register and an immediate are of this type.
230 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
231 "lbz $rD, $disp($rA)", LdStGeneral>;
232 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
233 "lha $rD, $disp($rA)", LdStLHA>;
234 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
235 "lhz $rD, $disp($rA)", LdStGeneral>;
236 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
237 "lmw $rD, $disp($rA)", LdStLMW>;
238 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
239 "lwz $rD, $disp($rA)", LdStGeneral>;
240 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
241 "lwzu $rD, $disp($rA)", LdStGeneral>;
243 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
244 "addi $rD, $rA, $imm", IntGeneral,
245 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
246 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
247 "addic $rD, $rA, $imm", IntGeneral,
249 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
250 "addic. $rD, $rA, $imm", IntGeneral,
252 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
253 "addis $rD, $rA, $imm", IntGeneral,
254 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
255 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
256 "la $rD, $sym($rA)", IntGeneral,
258 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
259 "mulli $rD, $rA, $imm", IntMulLI,
260 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
261 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
262 "subfic $rD, $rA, $imm", IntGeneral,
263 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
264 def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
265 "li $rD, $imm", IntGeneral,
266 [(set GPRC:$rD, immSExt16:$imm)]>;
267 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
268 "lis $rD, $imm", IntGeneral,
269 [(set GPRC:$rD, imm16Shifted:$imm)]>;
271 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
272 "stmw $rS, $disp($rA)", LdStLMW>;
273 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
274 "stb $rS, $disp($rA)", LdStGeneral>;
275 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
276 "sth $rS, $disp($rA)", LdStGeneral>;
277 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
278 "stw $rS, $disp($rA)", LdStGeneral>;
279 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
280 "stwu $rS, $disp($rA)", LdStGeneral>;
282 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
283 "andi. $dst, $src1, $src2", IntGeneral,
285 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
286 "andis. $dst, $src1, $src2", IntGeneral,
288 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
289 "ori $dst, $src1, $src2", IntGeneral,
290 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
291 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
292 "oris $dst, $src1, $src2", IntGeneral,
293 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
294 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
295 "xori $dst, $src1, $src2", IntGeneral,
296 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
297 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
298 "xoris $dst, $src1, $src2", IntGeneral,
299 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
300 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral>;
301 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
302 "cmpi $crD, $L, $rA, $imm", IntCompare>;
303 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
304 "cmpwi $crD, $rA, $imm", IntCompare>;
305 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
306 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
307 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
308 "cmpli $dst, $size, $src1, $src2", IntCompare>;
309 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
310 "cmplwi $dst, $src1, $src2", IntCompare>;
311 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
312 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
314 def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
315 "lfs $rD, $disp($rA)", LdStLFDU>;
316 def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
317 "lfd $rD, $disp($rA)", LdStLFD>;
320 def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
321 "stfs $rS, $disp($rA)", LdStUX>;
322 def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
323 "stfd $rS, $disp($rA)", LdStUX>;
326 // DS-Form instructions. Load/Store instructions available in PPC-64
329 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
330 "lwa $rT, $DS($rA)", LdStLWA>, isPPC64;
331 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
332 "ld $rT, $DS($rA)", LdStLD>, isPPC64;
335 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
336 "std $rT, $DS($rA)", LdStSTD>, isPPC64;
337 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
338 "stdu $rT, $DS($rA)", LdStSTD>, isPPC64;
341 // X-Form instructions. Most instructions that perform an operation on a
342 // register and another register are of this type.
345 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
346 "lbzx $dst, $base, $index", LdStGeneral>;
347 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
348 "lhax $dst, $base, $index", LdStLHA>;
349 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
350 "lhzx $dst, $base, $index", LdStGeneral>;
351 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
352 "lwax $dst, $base, $index", LdStLHA>, isPPC64;
353 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
354 "lwzx $dst, $base, $index", LdStGeneral>;
355 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
356 "ldx $dst, $base, $index", LdStLD>, isPPC64;
358 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
359 "nand $rA, $rS, $rB", IntGeneral,
360 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
361 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
362 "and $rA, $rS, $rB", IntGeneral,
363 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
364 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
365 "and. $rA, $rS, $rB", IntGeneral,
367 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
368 "andc $rA, $rS, $rB", IntGeneral,
369 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
370 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
371 "or $rA, $rS, $rB", IntGeneral,
372 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
373 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
374 "or $rA, $rS, $rB", IntGeneral,
375 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
376 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
377 "or $rA, $rS, $rB", IntGeneral,
379 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
380 "or $rA, $rS, $rB", IntGeneral,
382 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
383 "nor $rA, $rS, $rB", IntGeneral,
384 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
385 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
386 "or. $rA, $rS, $rB", IntGeneral,
388 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
389 "orc $rA, $rS, $rB", IntGeneral,
390 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
391 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
392 "eqv $rA, $rS, $rB", IntGeneral,
393 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
394 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
395 "xor $rA, $rS, $rB", IntGeneral,
396 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
397 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
398 "sld $rA, $rS, $rB", IntRotateD,
399 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
400 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
401 "slw $rA, $rS, $rB", IntGeneral,
402 [(set GPRC:$rA, (shl GPRC:$rS, GPRC:$rB))]>;
403 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
404 "srd $rA, $rS, $rB", IntRotateD,
405 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
406 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
407 "srw $rA, $rS, $rB", IntGeneral,
408 [(set GPRC:$rA, (srl GPRC:$rS, GPRC:$rB))]>;
409 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
410 "srad $rA, $rS, $rB", IntRotateD,
411 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
412 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
413 "sraw $rA, $rS, $rB", IntShift,
414 [(set GPRC:$rA, (sra GPRC:$rS, GPRC:$rB))]>;
416 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
417 "stbx $rS, $rA, $rB", LdStGeneral>;
418 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
419 "sthx $rS, $rA, $rB", LdStGeneral>;
420 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
421 "stwx $rS, $rA, $rB", LdStGeneral>;
422 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
423 "stwux $rS, $rA, $rB", LdStGeneral>;
424 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
425 "stdx $rS, $rA, $rB", LdStSTD>, isPPC64;
426 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
427 "stdux $rS, $rA, $rB", LdStSTD>, isPPC64;
429 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
430 "srawi $rA, $rS, $SH", IntShift,
431 [(set GPRC:$rA, (sra GPRC:$rS, imm:$SH))]>;
432 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
433 "cntlzw $rA, $rS", IntGeneral,
434 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
435 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
436 "extsb $rA, $rS", IntGeneral,
437 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
438 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
439 "extsh $rA, $rS", IntGeneral,
440 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
441 def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
442 "extsw $rA, $rS", IntRotateD,
444 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
445 "cmp $crD, $long, $rA, $rB", IntCompare>;
446 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
447 "cmpl $crD, $long, $rA, $rB", IntCompare>;
448 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
449 "cmpw $crD, $rA, $rB", IntCompare>;
450 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
451 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
452 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
453 "cmplw $crD, $rA, $rB", IntCompare>;
454 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
455 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
456 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
457 // "fcmpo $crD, $fA, $fB", FPCompare>;
458 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
459 "fcmpu $crD, $fA, $fB", FPCompare>;
460 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
461 "fcmpu $crD, $fA, $fB", FPCompare>;
464 def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
465 "lfsx $dst, $base, $index", LdStLFDU>;
466 def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
467 "lfdx $dst, $base, $index", LdStLFDU>;
469 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
470 "fcfid $frD, $frB", FPGeneral,
471 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
472 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
473 "fctidz $frD, $frB", FPGeneral,
474 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
475 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
476 "fctiwz $frD, $frB", FPGeneral,
477 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
478 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
479 "frsp $frD, $frB", FPGeneral,
480 [(set F4RC:$frD, (fround F8RC:$frB))]>;
481 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
482 "fsqrt $frD, $frB", FPSqrt,
483 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
484 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
485 "fsqrts $frD, $frB", FPSqrt,
486 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
488 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
489 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
490 "fmr $frD, $frB", FPGeneral,
491 []>; // (set F4RC:$frD, F4RC:$frB)
492 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
493 "fmr $frD, $frB", FPGeneral,
494 []>; // (set F8RC:$frD, F8RC:$frB)
495 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
496 "fmr $frD, $frB", FPGeneral,
497 [(set F8RC:$frD, (fextend F4RC:$frB))]>;
499 // These are artificially split into two different forms, for 4/8 byte FP.
500 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
501 "fabs $frD, $frB", FPGeneral,
502 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
503 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
504 "fabs $frD, $frB", FPGeneral,
505 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
506 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
507 "fnabs $frD, $frB", FPGeneral,
508 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
509 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
510 "fnabs $frD, $frB", FPGeneral,
511 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
512 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
513 "fneg $frD, $frB", FPGeneral,
514 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
515 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
516 "fneg $frD, $frB", FPGeneral,
517 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
521 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
522 "stfsx $frS, $rA, $rB", LdStUX>;
523 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
524 "stfdx $frS, $rA, $rB", LdStUX>;
527 // XL-Form instructions. condition register logical ops.
529 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
530 "mcrf $BF, $BFA", BrMCR>;
532 // XFX-Form instructions. Instructions that deal with SPRs
534 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
535 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
536 // which means the SPR value needs to be multiplied by a factor of 32.
537 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
538 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT", SprMFSPR>;
539 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>;
540 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
541 "mtcrf $FXM, $rS", BrMCRX>;
542 def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
543 "mfcr $rT, $FXM", SprMFCR>;
544 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
545 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
547 // XS-Form instructions. Just 'sradi'
549 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
550 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
552 // XO-Form instructions. Arithmetic instructions that can set overflow bit
554 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
555 "add $rT, $rA, $rB", IntGeneral,
556 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
557 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
558 "add $rT, $rA, $rB", IntGeneral,
559 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
560 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
561 "addc $rT, $rA, $rB", IntGeneral,
563 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
564 "adde $rT, $rA, $rB", IntGeneral,
566 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
567 "divd $rT, $rA, $rB", IntDivD,
568 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
569 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
570 "divdu $rT, $rA, $rB", IntDivD,
571 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
572 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
573 "divw $rT, $rA, $rB", IntDivW,
574 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
575 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
576 "divwu $rT, $rA, $rB", IntDivW,
577 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
578 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
579 "mulhd $rT, $rA, $rB", IntMulHW,
580 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
581 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
582 "mulhdu $rT, $rA, $rB", IntMulHWU,
583 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
584 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
585 "mulhw $rT, $rA, $rB", IntMulHW,
586 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
587 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
588 "mulhwu $rT, $rA, $rB", IntMulHWU,
589 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
590 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
591 "mulld $rT, $rA, $rB", IntMulHD,
592 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
593 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
594 "mullw $rT, $rA, $rB", IntMulHW,
595 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
596 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
597 "subf $rT, $rA, $rB", IntGeneral,
598 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
599 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
600 "subfc $rT, $rA, $rB", IntGeneral,
602 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
603 "subfe $rT, $rA, $rB", IntGeneral,
605 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
606 "addme $rT, $rA", IntGeneral,
608 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
609 "addze $rT, $rA", IntGeneral,
611 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
612 "neg $rT, $rA", IntGeneral,
613 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
614 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
615 "subfze $rT, $rA", IntGeneral,
618 // A-Form instructions. Most of the instructions executed in the FPU are of
621 def FMADD : AForm_1<63, 29,
622 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
623 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
624 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
626 def FMADDS : AForm_1<59, 29,
627 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
628 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
629 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
631 def FMSUB : AForm_1<63, 28,
632 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
633 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
634 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
636 def FMSUBS : AForm_1<59, 28,
637 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
638 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
639 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
641 def FNMADD : AForm_1<63, 31,
642 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
643 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
644 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
646 def FNMADDS : AForm_1<59, 31,
647 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
648 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
649 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
651 def FNMSUB : AForm_1<63, 30,
652 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
653 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
654 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
656 def FNMSUBS : AForm_1<59, 30,
657 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
658 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
659 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
661 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
662 // having 4 of these, force the comparison to always be an 8-byte double (code
663 // should use an FMRSD if the input comparison value really wants to be a float)
664 // and 4/8 byte forms for the result and operand type..
665 def FSELD : AForm_1<63, 23,
666 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
667 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
668 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
669 def FSELS : AForm_1<63, 23,
670 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
671 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
672 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
673 def FADD : AForm_2<63, 21,
674 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
675 "fadd $FRT, $FRA, $FRB", FPGeneral,
676 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
677 def FADDS : AForm_2<59, 21,
678 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
679 "fadds $FRT, $FRA, $FRB", FPGeneral,
680 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
681 def FDIV : AForm_2<63, 18,
682 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
683 "fdiv $FRT, $FRA, $FRB", FPDivD,
684 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
685 def FDIVS : AForm_2<59, 18,
686 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
687 "fdivs $FRT, $FRA, $FRB", FPDivS,
688 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
689 def FMUL : AForm_3<63, 25,
690 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
691 "fmul $FRT, $FRA, $FRB", FPFused,
692 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
693 def FMULS : AForm_3<59, 25,
694 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
695 "fmuls $FRT, $FRA, $FRB", FPGeneral,
696 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
697 def FSUB : AForm_2<63, 20,
698 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
699 "fsub $FRT, $FRA, $FRB", FPGeneral,
700 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
701 def FSUBS : AForm_2<59, 20,
702 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
703 "fsubs $FRT, $FRA, $FRB", FPGeneral,
704 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
706 // M-Form instructions. rotate and mask instructions.
708 let isTwoAddress = 1, isCommutable = 1 in {
709 // RLWIMI can be commuted if the rotate amount is zero.
710 def RLWIMI : MForm_2<20,
711 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
712 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
714 def RLDIMI : MDForm_1<30, 3,
715 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
716 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
719 def RLWINM : MForm_2<21,
720 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
721 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
723 def RLWINMo : MForm_2<21,
724 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
725 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
727 def RLWNM : MForm_2<23,
728 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
729 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
732 // MD-Form instructions. 64 bit rotate instructions.
734 def RLDICL : MDForm_1<30, 0,
735 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
736 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
738 def RLDICR : MDForm_1<30, 1,
739 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
740 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
743 //===----------------------------------------------------------------------===//
744 // PowerPC Instruction Patterns
747 // Arbitrary immediate support. Implement in terms of LIS/ORI.
748 def : Pat<(i32 imm:$imm),
749 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
751 // Implement the 'not' operation with the NOR instruction.
752 def NOT : Pat<(not GPRC:$in),
753 (NOR GPRC:$in, GPRC:$in)>;
755 // ADD an arbitrary immediate.
756 def : Pat<(add GPRC:$in, imm:$imm),
757 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
758 // OR an arbitrary immediate.
759 def : Pat<(or GPRC:$in, imm:$imm),
760 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
761 // XOR an arbitrary immediate.
762 def : Pat<(xor GPRC:$in, imm:$imm),
763 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
764 def : Pat<(or (shl GPRC:$rS, GPRC:$rB),
765 (srl GPRC:$rS, (sub 32, GPRC:$rB))),
766 (RLWNM GPRC:$rS, GPRC:$rB, 0, 31)>;
768 def : Pat<(zext GPRC:$in),
769 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
770 def : Pat<(anyext GPRC:$in),
771 (OR4To8 GPRC:$in, GPRC:$in)>;
772 def : Pat<(trunc G8RC:$in),
773 (OR8To4 G8RC:$in, G8RC:$in)>;
776 def : Pat<(shl GPRC:$in, imm:$imm),
777 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
778 def : Pat<(shl G8RC:$in, imm:$imm),
779 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
781 def : Pat<(srl GPRC:$in, imm:$imm),
782 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
783 def : Pat<(srl G8RC:$in, imm:$imm),
784 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
786 // Same as above, but using a temporary. FIXME: implement temporaries :)
788 def : Pattern<(xor GPRC:$in, imm:$imm),
789 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
790 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
793 //===----------------------------------------------------------------------===//
794 // PowerPCInstrInfo Definition
796 def PowerPCInstrInfo : InstrInfo {
799 let TSFlagsFields = [ "VMX", "PPC64" ];
800 let TSFlagsShifts = [ 0, 1 ];
802 let isLittleEndianEncoding = 1;