1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific DAG Nodes.
21 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
22 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
23 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
25 def PPCfsel : SDNode<"PPCISD::FSEL",
26 // Type constraint for fsel.
27 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
28 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
30 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
31 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
32 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
33 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
35 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
36 // amounts. These nodes are generated by the multi-precision shift code.
37 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
38 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
40 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
41 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
42 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
44 // These are target-independent nodes, but have target-specific formats.
45 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
46 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>;
47 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>;
49 def SDT_PPCRetFlag : SDTypeProfile<0, 0, []>;
50 def retflag : SDNode<"PPCISD::RET_FLAG", SDT_PPCRetFlag,
51 [SDNPHasChain, SDNPOptInFlag]>;
53 //===----------------------------------------------------------------------===//
54 // PowerPC specific transformation functions and pattern fragments.
57 def SHL32 : SDNodeXForm<imm, [{
58 // Transformation function: 31 - imm
59 return getI32Imm(31 - N->getValue());
62 def SHL64 : SDNodeXForm<imm, [{
63 // Transformation function: 63 - imm
64 return getI32Imm(63 - N->getValue());
67 def SRL32 : SDNodeXForm<imm, [{
68 // Transformation function: 32 - imm
69 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
72 def SRL64 : SDNodeXForm<imm, [{
73 // Transformation function: 64 - imm
74 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
77 def LO16 : SDNodeXForm<imm, [{
78 // Transformation function: get the low 16 bits.
79 return getI32Imm((unsigned short)N->getValue());
82 def HI16 : SDNodeXForm<imm, [{
83 // Transformation function: shift the immediate value down into the low bits.
84 return getI32Imm((unsigned)N->getValue() >> 16);
87 def HA16 : SDNodeXForm<imm, [{
88 // Transformation function: shift the immediate value down into the low bits.
89 signed int Val = N->getValue();
90 return getI32Imm((Val - (signed short)Val) >> 16);
94 def immSExt16 : PatLeaf<(imm), [{
95 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
96 // field. Used by instructions like 'addi'.
97 return (int)N->getValue() == (short)N->getValue();
99 def immZExt16 : PatLeaf<(imm), [{
100 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
101 // field. Used by instructions like 'ori'.
102 return (unsigned)N->getValue() == (unsigned short)N->getValue();
105 def imm16Shifted : PatLeaf<(imm), [{
106 // imm16Shifted predicate - True if only bits in the top 16-bits of the
107 // immediate are set. Used by instructions like 'addis'.
108 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
112 // Example of a legalize expander: Only for PPC64.
113 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
114 [(set f64:$tmp , (FCTIDZ f64:$src)),
115 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
116 (store f64:$tmp, i32:$tmpFI),
117 (set i64:$dst, (load i32:$tmpFI))],
121 //===----------------------------------------------------------------------===//
122 // PowerPC Flag Definitions.
124 class isPPC64 { bit PPC64 = 1; }
125 class isVMX { bit VMX = 1; }
127 list<Register> Defs = [CR0];
133 //===----------------------------------------------------------------------===//
134 // PowerPC Operand Definitions.
136 def u5imm : Operand<i32> {
137 let PrintMethod = "printU5ImmOperand";
139 def u6imm : Operand<i32> {
140 let PrintMethod = "printU6ImmOperand";
142 def s16imm : Operand<i32> {
143 let PrintMethod = "printS16ImmOperand";
145 def u16imm : Operand<i32> {
146 let PrintMethod = "printU16ImmOperand";
148 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
149 let PrintMethod = "printS16X4ImmOperand";
151 def target : Operand<OtherVT> {
152 let PrintMethod = "printBranchOperand";
154 def calltarget : Operand<i32> {
155 let PrintMethod = "printCallOperand";
157 def aaddr : Operand<i32> {
158 let PrintMethod = "printAbsAddrOperand";
160 def piclabel: Operand<i32> {
161 let PrintMethod = "printPICLabel";
163 def symbolHi: Operand<i32> {
164 let PrintMethod = "printSymbolHi";
166 def symbolLo: Operand<i32> {
167 let PrintMethod = "printSymbolLo";
169 def crbitm: Operand<i8> {
170 let PrintMethod = "printcrbitm";
173 def memri : Operand<i32> {
174 let PrintMethod = "printMemRegImm";
175 let NumMIOperands = 2;
176 let MIOperandInfo = (ops i32imm, GPRC);
178 def memrr : Operand<i32> {
179 let PrintMethod = "printMemRegReg";
180 let NumMIOperands = 2;
181 let MIOperandInfo = (ops GPRC, GPRC);
184 // Define X86 specific addressing mode.
185 def iaddr : ComplexPattern<i32, 2, "SelectAddrImm", []>;
186 def xaddr : ComplexPattern<i32, 2, "SelectAddrIdx", []>;
187 def xoaddr : ComplexPattern<i32, 2, "SelectAddrIdxOnly",[]>;
189 //===----------------------------------------------------------------------===//
190 // PowerPC Instruction Predicate Definitions.
191 def FPContractions : Predicate<"!NoExcessFPPrecision">;
193 //===----------------------------------------------------------------------===//
194 // PowerPC Instruction Definitions.
196 // Pseudo-instructions:
197 def PHI : Pseudo<(ops variable_ops), "; PHI", []>;
199 let isLoad = 1, hasCtrlDep = 1 in {
200 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
201 "; ADJCALLSTACKDOWN",
202 [(callseq_start imm:$amt)]>;
203 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
205 [(callseq_end imm:$amt)]>;
207 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
208 [(set GPRC:$rD, (undef))]>;
209 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8",
210 [(set F8RC:$rD, (undef))]>;
211 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4",
212 [(set F4RC:$rD, (undef))]>;
214 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
215 // scheduler into a branch sequence.
216 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
217 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
218 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
219 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
220 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
221 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
222 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
226 let isTerminator = 1, noResults = 1 in {
227 // FIXME: temporary workaround for return without an incoming flag.
229 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>;
230 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
234 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>;
236 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1 in {
237 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
238 target:$true, target:$false),
239 "; COND_BRANCH", []>;
240 def B : IForm<18, 0, 0, (ops target:$dst),
244 // FIXME: 4*CR# needs to be added to the BI field!
245 // This will only work for CR0 as it stands now
246 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
247 "blt $crS, $block", BrB>;
248 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
249 "ble $crS, $block", BrB>;
250 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
251 "beq $crS, $block", BrB>;
252 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
253 "bge $crS, $block", BrB>;
254 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
255 "bgt $crS, $block", BrB>;
256 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
257 "bne $crS, $block", BrB>;
258 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
259 "bun $crS, $block", BrB>;
260 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
261 "bnu $crS, $block", BrB>;
264 let isCall = 1, noResults = 1,
265 // All calls clobber the non-callee saved registers...
266 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
267 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
269 CR0,CR1,CR5,CR6,CR7] in {
270 // Convenient aliases for call instructions
271 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
272 "bl $func", BrB, []>;
273 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
274 "bla $func", BrB, []>;
275 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB,
279 // D-Form instructions. Most instructions that perform an operation on a
280 // register and an immediate are of this type.
283 def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
284 "lbz $rD, $src", LdStGeneral,
285 [(set GPRC:$rD, (zextload iaddr:$src, i8))]>;
286 def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
287 "lha $rD, $src", LdStLHA,
288 [(set GPRC:$rD, (sextload iaddr:$src, i16))]>;
289 def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
290 "lhz $rD, $src", LdStGeneral,
291 [(set GPRC:$rD, (zextload iaddr:$src, i16))]>;
292 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
293 "lmw $rD, $disp($rA)", LdStLMW,
295 def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
296 "lwz $rD, $src", LdStGeneral,
297 [(set GPRC:$rD, (load iaddr:$src))]>;
298 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
299 "lwzu $rD, $disp($rA)", LdStGeneral,
302 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
303 "addi $rD, $rA, $imm", IntGeneral,
304 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
305 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
306 "addic $rD, $rA, $imm", IntGeneral,
308 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
309 "addic. $rD, $rA, $imm", IntGeneral,
311 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
312 "addis $rD, $rA, $imm", IntGeneral,
313 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
314 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
315 "la $rD, $sym($rA)", IntGeneral,
316 [(set GPRC:$rD, (add GPRC:$rA,
317 (PPClo tglobaladdr:$sym, 0)))]>;
318 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
319 "mulli $rD, $rA, $imm", IntMulLI,
320 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
321 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
322 "subfic $rD, $rA, $imm", IntGeneral,
323 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
324 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
325 "li $rD, $imm", IntGeneral,
326 [(set GPRC:$rD, immSExt16:$imm)]>;
327 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
328 "lis $rD, $imm", IntGeneral,
329 [(set GPRC:$rD, imm16Shifted:$imm)]>;
330 let isStore = 1, noResults = 1 in {
331 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
332 "stmw $rS, $disp($rA)", LdStLMW,
334 def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
335 "stb $rS, $src", LdStGeneral,
336 [(truncstore GPRC:$rS, iaddr:$src, i8)]>;
337 def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
338 "sth $rS, $src", LdStGeneral,
339 [(truncstore GPRC:$rS, iaddr:$src, i16)]>;
340 def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
341 "stw $rS, $src", LdStGeneral,
342 [(store GPRC:$rS, iaddr:$src)]>;
343 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
344 "stwu $rS, $disp($rA)", LdStGeneral,
347 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
348 "andi. $dst, $src1, $src2", IntGeneral,
350 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
351 "andis. $dst, $src1, $src2", IntGeneral,
353 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
354 "ori $dst, $src1, $src2", IntGeneral,
355 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
356 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
357 "oris $dst, $src1, $src2", IntGeneral,
358 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
359 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
360 "xori $dst, $src1, $src2", IntGeneral,
361 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
362 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
363 "xoris $dst, $src1, $src2", IntGeneral,
364 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
365 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
367 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
368 "cmpi $crD, $L, $rA, $imm", IntCompare>;
369 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
370 "cmpwi $crD, $rA, $imm", IntCompare>;
371 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
372 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
373 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
374 "cmpli $dst, $size, $src1, $src2", IntCompare>;
375 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
376 "cmplwi $dst, $src1, $src2", IntCompare>;
377 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
378 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
380 def LFS : DForm_8<48, (ops F4RC:$rD, memri:$src),
381 "lfs $rD, $src", LdStLFDU,
382 [(set F4RC:$rD, (load iaddr:$src))]>;
383 def LFD : DForm_8<50, (ops F8RC:$rD, memri:$src),
384 "lfd $rD, $src", LdStLFD,
385 [(set F8RC:$rD, (load iaddr:$src))]>;
387 let isStore = 1, noResults = 1 in {
388 def STFS : DForm_9<52, (ops F4RC:$rS, memri:$dst),
389 "stfs $rS, $dst", LdStUX,
390 [(store F4RC:$rS, iaddr:$dst)]>;
391 def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst),
392 "stfd $rS, $dst", LdStUX,
393 [(store F8RC:$rS, iaddr:$dst)]>;
396 // DS-Form instructions. Load/Store instructions available in PPC-64
399 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
400 "lwa $rT, $DS($rA)", LdStLWA,
402 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
403 "ld $rT, $DS($rA)", LdStLD,
406 let isStore = 1, noResults = 1 in {
407 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
408 "std $rT, $DS($rA)", LdStSTD,
410 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
411 "stdu $rT, $DS($rA)", LdStSTD,
415 // X-Form instructions. Most instructions that perform an operation on a
416 // register and another register are of this type.
419 def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
420 "lbzx $rD, $src", LdStGeneral,
421 [(set GPRC:$rD, (zextload xaddr:$src, i8))]>;
422 def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
423 "lhax $rD, $src", LdStLHA,
424 [(set GPRC:$rD, (sextload xaddr:$src, i16))]>;
425 def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
426 "lhzx $rD, $src", LdStGeneral,
427 [(set GPRC:$rD, (zextload xaddr:$src, i16))]>;
428 def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
429 "lwax $rD, $src", LdStLHA,
430 [(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64;
431 def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
432 "lwzx $rD, $src", LdStGeneral,
433 [(set GPRC:$rD, (load xaddr:$src))]>;
434 def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
435 "ldx $rD, $src", LdStLD,
436 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
437 def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
438 "lvebx $vD, $base, $rA", LdStGeneral,
440 def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
441 "lvehx $vD, $base, $rA", LdStGeneral,
443 def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
444 "lvewx $vD, $base, $rA", LdStGeneral,
446 def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
447 "lvx $vD, $src", LdStGeneral,
448 [(set VRRC:$vD, (v4f32 (load xoaddr:$src)))]>;
450 def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
451 "lvsl $vD, $base, $rA", LdStGeneral,
453 def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
454 "lvsl $vD, $base, $rA", LdStGeneral,
456 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
457 "nand $rA, $rS, $rB", IntGeneral,
458 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
459 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
460 "and $rA, $rS, $rB", IntGeneral,
461 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
462 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
463 "and. $rA, $rS, $rB", IntGeneral,
465 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
466 "andc $rA, $rS, $rB", IntGeneral,
467 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
468 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
469 "or $rA, $rS, $rB", IntGeneral,
470 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
471 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
472 "or $rA, $rS, $rB", IntGeneral,
473 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
474 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
475 "or $rA, $rS, $rB", IntGeneral,
477 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
478 "or $rA, $rS, $rB", IntGeneral,
480 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
481 "nor $rA, $rS, $rB", IntGeneral,
482 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
483 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
484 "or. $rA, $rS, $rB", IntGeneral,
486 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
487 "orc $rA, $rS, $rB", IntGeneral,
488 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
489 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
490 "eqv $rA, $rS, $rB", IntGeneral,
491 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
492 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
493 "xor $rA, $rS, $rB", IntGeneral,
494 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
495 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
496 "sld $rA, $rS, $rB", IntRotateD,
497 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
498 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
499 "slw $rA, $rS, $rB", IntGeneral,
500 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
501 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
502 "srd $rA, $rS, $rB", IntRotateD,
503 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
504 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
505 "srw $rA, $rS, $rB", IntGeneral,
506 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
507 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
508 "srad $rA, $rS, $rB", IntRotateD,
509 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
510 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
511 "sraw $rA, $rS, $rB", IntShift,
512 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
513 let isStore = 1, noResults = 1 in {
514 def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
515 "stbx $rS, $dst", LdStGeneral,
516 [(truncstore GPRC:$rS, xaddr:$dst, i8)]>;
517 def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
518 "sthx $rS, $dst", LdStGeneral,
519 [(truncstore GPRC:$rS, xaddr:$dst, i16)]>;
520 def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
521 "stwx $rS, $dst", LdStGeneral,
522 [(store GPRC:$rS, xaddr:$dst)]>;
523 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
524 "stwux $rS, $rA, $rB", LdStGeneral,
526 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
527 "stdx $rS, $rA, $rB", LdStSTD,
529 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
530 "stdux $rS, $rA, $rB", LdStSTD,
532 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
533 "stvebx $rS, $rA, $rB", LdStGeneral,
535 def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
536 "stvehx $rS, $rA, $rB", LdStGeneral,
538 def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
539 "stvewx $rS, $rA, $rB", LdStGeneral,
541 def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
542 "stvx $rS, $dst", LdStGeneral,
543 [(store (v4f32 VRRC:$rS), xoaddr:$dst)]>;
545 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
546 "srawi $rA, $rS, $SH", IntShift,
547 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
548 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
549 "cntlzw $rA, $rS", IntGeneral,
550 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
551 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
552 "extsb $rA, $rS", IntGeneral,
553 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
554 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
555 "extsh $rA, $rS", IntGeneral,
556 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
557 def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
558 "extsw $rA, $rS", IntGeneral,
559 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
560 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
561 "cmp $crD, $long, $rA, $rB", IntCompare>;
562 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
563 "cmpl $crD, $long, $rA, $rB", IntCompare>;
564 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
565 "cmpw $crD, $rA, $rB", IntCompare>;
566 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
567 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
568 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
569 "cmplw $crD, $rA, $rB", IntCompare>;
570 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
571 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
572 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
573 // "fcmpo $crD, $fA, $fB", FPCompare>;
574 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
575 "fcmpu $crD, $fA, $fB", FPCompare>;
576 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
577 "fcmpu $crD, $fA, $fB", FPCompare>;
580 def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src),
581 "lfsx $frD, $src", LdStLFDU,
582 [(set F4RC:$frD, (load xaddr:$src))]>;
583 def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
584 "lfdx $frD, $src", LdStLFDU,
585 [(set F8RC:$frD, (load xaddr:$src))]>;
587 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
588 "fcfid $frD, $frB", FPGeneral,
589 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
590 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
591 "fctidz $frD, $frB", FPGeneral,
592 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
593 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
594 "fctiwz $frD, $frB", FPGeneral,
595 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
596 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
597 "frsp $frD, $frB", FPGeneral,
598 [(set F4RC:$frD, (fround F8RC:$frB))]>;
599 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
600 "fsqrt $frD, $frB", FPSqrt,
601 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
602 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
603 "fsqrts $frD, $frB", FPSqrt,
604 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
606 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
607 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
608 "fmr $frD, $frB", FPGeneral,
609 []>; // (set F4RC:$frD, F4RC:$frB)
610 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
611 "fmr $frD, $frB", FPGeneral,
612 []>; // (set F8RC:$frD, F8RC:$frB)
613 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
614 "fmr $frD, $frB", FPGeneral,
615 [(set F8RC:$frD, (fextend F4RC:$frB))]>;
617 // These are artificially split into two different forms, for 4/8 byte FP.
618 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
619 "fabs $frD, $frB", FPGeneral,
620 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
621 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
622 "fabs $frD, $frB", FPGeneral,
623 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
624 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
625 "fnabs $frD, $frB", FPGeneral,
626 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
627 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
628 "fnabs $frD, $frB", FPGeneral,
629 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
630 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
631 "fneg $frD, $frB", FPGeneral,
632 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
633 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
634 "fneg $frD, $frB", FPGeneral,
635 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
638 let isStore = 1, noResults = 1 in {
639 def STFIWX: XForm_28<31, 983, (ops F4RC:$frS, memrr:$dst),
640 "stfiwx $frS, $dst", LdStUX,
642 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst),
643 "stfsx $frS, $dst", LdStUX,
644 [(store F4RC:$frS, xaddr:$dst)]>;
645 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst),
646 "stfdx $frS, $dst", LdStUX,
647 [(store F8RC:$frS, xaddr:$dst)]>;
650 // XL-Form instructions. condition register logical ops.
652 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
653 "mcrf $BF, $BFA", BrMCR>;
655 // XFX-Form instructions. Instructions that deal with SPRs
657 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
658 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
659 // which means the SPR value needs to be multiplied by a factor of 32.
660 def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
661 def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>;
662 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>;
663 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
664 "mtcrf $FXM, $rS", BrMCRX>;
665 def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
666 "mfcr $rT, $FXM", SprMFCR>;
667 def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
668 def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
669 def MTSPR : XFXForm_7<31, 467, (ops GPRC:$rS, u16imm:$UIMM), "mtspr $UIMM, $rS",
672 // XS-Form instructions. Just 'sradi'
674 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
675 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
677 // XO-Form instructions. Arithmetic instructions that can set overflow bit
679 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
680 "add $rT, $rA, $rB", IntGeneral,
681 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
682 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
683 "add $rT, $rA, $rB", IntGeneral,
684 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
685 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
686 "addc $rT, $rA, $rB", IntGeneral,
688 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
689 "adde $rT, $rA, $rB", IntGeneral,
691 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
692 "divd $rT, $rA, $rB", IntDivD,
693 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
694 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
695 "divdu $rT, $rA, $rB", IntDivD,
696 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
697 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
698 "divw $rT, $rA, $rB", IntDivW,
699 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
700 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
701 "divwu $rT, $rA, $rB", IntDivW,
702 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
703 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
704 "mulhd $rT, $rA, $rB", IntMulHW,
705 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
706 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
707 "mulhdu $rT, $rA, $rB", IntMulHWU,
708 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
709 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
710 "mulhw $rT, $rA, $rB", IntMulHW,
711 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
712 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
713 "mulhwu $rT, $rA, $rB", IntMulHWU,
714 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
715 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
716 "mulld $rT, $rA, $rB", IntMulHD,
717 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
718 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
719 "mullw $rT, $rA, $rB", IntMulHW,
720 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
721 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
722 "subf $rT, $rA, $rB", IntGeneral,
723 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
724 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
725 "subfc $rT, $rA, $rB", IntGeneral,
727 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
728 "subfe $rT, $rA, $rB", IntGeneral,
730 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
731 "addme $rT, $rA", IntGeneral,
733 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
734 "addze $rT, $rA", IntGeneral,
736 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
737 "neg $rT, $rA", IntGeneral,
738 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
739 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
740 "subfze $rT, $rA", IntGeneral,
743 // A-Form instructions. Most of the instructions executed in the FPU are of
746 def FMADD : AForm_1<63, 29,
747 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
748 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
749 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
751 Requires<[FPContractions]>;
752 def FMADDS : AForm_1<59, 29,
753 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
754 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
755 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
757 Requires<[FPContractions]>;
758 def FMSUB : AForm_1<63, 28,
759 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
760 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
761 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
763 Requires<[FPContractions]>;
764 def FMSUBS : AForm_1<59, 28,
765 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
766 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
767 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
769 Requires<[FPContractions]>;
770 def FNMADD : AForm_1<63, 31,
771 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
772 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
773 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
775 Requires<[FPContractions]>;
776 def FNMADDS : AForm_1<59, 31,
777 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
778 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
779 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
781 Requires<[FPContractions]>;
782 def FNMSUB : AForm_1<63, 30,
783 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
784 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
785 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
787 Requires<[FPContractions]>;
788 def FNMSUBS : AForm_1<59, 30,
789 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
790 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
791 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
793 Requires<[FPContractions]>;
794 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
795 // having 4 of these, force the comparison to always be an 8-byte double (code
796 // should use an FMRSD if the input comparison value really wants to be a float)
797 // and 4/8 byte forms for the result and operand type..
798 def FSELD : AForm_1<63, 23,
799 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
800 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
801 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
802 def FSELS : AForm_1<63, 23,
803 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
804 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
805 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
806 def FADD : AForm_2<63, 21,
807 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
808 "fadd $FRT, $FRA, $FRB", FPGeneral,
809 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
810 def FADDS : AForm_2<59, 21,
811 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
812 "fadds $FRT, $FRA, $FRB", FPGeneral,
813 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
814 def FDIV : AForm_2<63, 18,
815 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
816 "fdiv $FRT, $FRA, $FRB", FPDivD,
817 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
818 def FDIVS : AForm_2<59, 18,
819 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
820 "fdivs $FRT, $FRA, $FRB", FPDivS,
821 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
822 def FMUL : AForm_3<63, 25,
823 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
824 "fmul $FRT, $FRA, $FRB", FPFused,
825 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
826 def FMULS : AForm_3<59, 25,
827 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
828 "fmuls $FRT, $FRA, $FRB", FPGeneral,
829 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
830 def FSUB : AForm_2<63, 20,
831 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
832 "fsub $FRT, $FRA, $FRB", FPGeneral,
833 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
834 def FSUBS : AForm_2<59, 20,
835 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
836 "fsubs $FRT, $FRA, $FRB", FPGeneral,
837 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
839 // M-Form instructions. rotate and mask instructions.
841 let isTwoAddress = 1, isCommutable = 1 in {
842 // RLWIMI can be commuted if the rotate amount is zero.
843 def RLWIMI : MForm_2<20,
844 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
845 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
847 def RLDIMI : MDForm_1<30, 3,
848 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
849 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
852 def RLWINM : MForm_2<21,
853 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
854 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
856 def RLWINMo : MForm_2<21,
857 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
858 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
860 def RLWNM : MForm_2<23,
861 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
862 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
865 // MD-Form instructions. 64 bit rotate instructions.
867 def RLDICL : MDForm_1<30, 0,
868 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
869 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
871 def RLDICR : MDForm_1<30, 1,
872 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
873 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
876 // VA-Form instructions. 3-input AltiVec ops.
877 def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
878 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
879 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
881 Requires<[FPContractions]>;
882 def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
883 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
884 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA,
887 Requires<[FPContractions]>;
889 // VX-Form instructions. AltiVec arithmetic ops.
890 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
891 "vaddfp $vD, $vA, $vB", VecFP,
892 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
893 def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
894 "vadduwm $vD, $vA, $vB", VecGeneral,
895 [(set VRRC:$vD, (add VRRC:$vA, VRRC:$vB))]>;
896 def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
897 "vcfsx $vD, $vB, $UIMM", VecFP,
899 def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
900 "vcfux $vD, $vB, $UIMM", VecFP,
902 def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
903 "vctsxs $vD, $vB, $UIMM", VecFP,
905 def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
906 "vctuxs $vD, $vB, $UIMM", VecFP,
908 def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
909 "vexptefp $vD, $vB", VecFP,
911 def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
912 "vlogefp $vD, $vB", VecFP,
914 def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
915 "vmaxfp $vD, $vA, $vB", VecFP,
917 def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
918 "vminfp $vD, $vA, $vB", VecFP,
920 def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
921 "vrefp $vD, $vB", VecFP,
923 def VRFIM : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB),
924 "vrfim $vD, $vB", VecFP,
926 def VRFIN : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB),
927 "vrfin $vD, $vB", VecFP,
929 def VRFIP : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB),
930 "vrfip $vD, $vB", VecFP,
932 def VRFIZ : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB),
933 "vrfiz $vD, $vB", VecFP,
935 def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
936 "vrsqrtefp $vD, $vB", VecFP,
938 def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
939 "vsubfp $vD, $vA, $vB", VecFP,
940 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
941 def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
942 "vxor $vD, $vA, $vB", VecFP,
945 // VX-Form Pseudo Instructions
947 def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
948 "vxor $vD, $vD, $vD", VecFP,
952 //===----------------------------------------------------------------------===//
953 // DWARF Pseudo Instructions
956 def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
957 "; .loc $file, $line, $col",
958 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
961 def DWARF_LABEL : Pseudo<(ops i32imm:$id),
963 [(dwarf_label (i32 imm:$id))]>;
965 //===----------------------------------------------------------------------===//
966 // PowerPC Instruction Patterns
969 // Arbitrary immediate support. Implement in terms of LIS/ORI.
970 def : Pat<(i32 imm:$imm),
971 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
973 // Implement the 'not' operation with the NOR instruction.
974 def NOT : Pat<(not GPRC:$in),
975 (NOR GPRC:$in, GPRC:$in)>;
977 // ADD an arbitrary immediate.
978 def : Pat<(add GPRC:$in, imm:$imm),
979 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
980 // OR an arbitrary immediate.
981 def : Pat<(or GPRC:$in, imm:$imm),
982 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
983 // XOR an arbitrary immediate.
984 def : Pat<(xor GPRC:$in, imm:$imm),
985 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
986 def : Pat<(or (shl GPRC:$rS, GPRC:$rB),
987 (srl GPRC:$rS, (sub 32, GPRC:$rB))),
988 (RLWNM GPRC:$rS, GPRC:$rB, 0, 31)>;
990 def : Pat<(i64 (zext GPRC:$in)),
991 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
992 def : Pat<(i64 (anyext GPRC:$in)),
993 (OR4To8 GPRC:$in, GPRC:$in)>;
994 def : Pat<(i32 (trunc G8RC:$in)),
995 (OR8To4 G8RC:$in, G8RC:$in)>;
998 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
999 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1000 def : Pat<(shl G8RC:$in, (i64 imm:$imm)),
1001 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
1003 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1004 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1005 def : Pat<(srl G8RC:$in, (i64 imm:$imm)),
1006 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
1008 // Hi and Lo for Darwin Global Addresses.
1009 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1010 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1011 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1012 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1013 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1014 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1015 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1016 (ADDIS GPRC:$in, tconstpool:$g)>;
1018 def : Pat<(fmul VRRC:$vA, VRRC:$vB),
1019 (VMADDFP VRRC:$vA, (V_SET0), VRRC:$vB)>;
1021 // Fused negative multiply subtract, alternate pattern
1022 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1023 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1024 Requires<[FPContractions]>;
1025 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1026 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1027 Requires<[FPContractions]>;
1029 // Fused multiply add and multiply sub for packed float. These are represented
1030 // separately from the real instructions above, for operations that must have
1031 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
1032 def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
1033 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
1034 def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
1035 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
1037 // Standard shifts. These are represented separately from the real shifts above
1038 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1040 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1041 (SRAW GPRC:$rS, GPRC:$rB)>;
1042 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1043 (SRW GPRC:$rS, GPRC:$rB)>;
1044 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1045 (SLW GPRC:$rS, GPRC:$rB)>;
1047 def : Pat<(i32 (zextload iaddr:$src, i1)),
1049 def : Pat<(i32 (zextload xaddr:$src, i1)),
1051 def : Pat<(i32 (extload iaddr:$src, i1)),
1053 def : Pat<(i32 (extload xaddr:$src, i1)),
1055 def : Pat<(i32 (extload iaddr:$src, i8)),
1057 def : Pat<(i32 (extload xaddr:$src, i8)),
1059 def : Pat<(i32 (extload iaddr:$src, i16)),
1061 def : Pat<(i32 (extload xaddr:$src, i16)),
1063 def : Pat<(f64 (extload iaddr:$src, f32)),
1064 (FMRSD (LFS iaddr:$src))>;
1065 def : Pat<(f64 (extload xaddr:$src, f32)),
1066 (FMRSD (LFSX xaddr:$src))>;
1068 def : Pat<(v4i32 (load xoaddr:$src)),
1069 (v4i32 (LVX xoaddr:$src))>;
1070 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
1071 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
1073 // Same as above, but using a temporary. FIXME: implement temporaries :)
1075 def : Pattern<(xor GPRC:$in, imm:$imm),
1076 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
1077 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
1080 //===----------------------------------------------------------------------===//
1081 // PowerPCInstrInfo Definition
1083 def PowerPCInstrInfo : InstrInfo {
1086 let TSFlagsFields = [ "VMX", "PPC64" ];
1087 let TSFlagsShifts = [ 0, 1 ];
1089 let isLittleEndianEncoding = 1;