1 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PowerPCInstrFormats.td"
17 let isTerminator = 1 in {
19 def BLR : XLForm_2_ext<19, 16, 20, 31, 1, 0, 0, (ops), "blr">;
20 def BCTR : XLForm_2_ext<19, 528, 20, 31, 1, 0, 0, (ops), "bctr">;
23 def u5imm : Operand<i8> {
24 let PrintMethod = "printU5ImmOperand";
26 def u6imm : Operand<i8> {
27 let PrintMethod = "printU6ImmOperand";
29 def s16imm : Operand<i16> {
30 let PrintMethod = "printS16ImmOperand";
32 def u16imm : Operand<i16> {
33 let PrintMethod = "printU16ImmOperand";
35 def target : Operand<i32> {
36 let PrintMethod = "printBranchOperand";
38 def piclabel: Operand<i32> {
39 let PrintMethod = "printPICLabel";
41 def symbolHi: Operand<i32> {
42 let PrintMethod = "printSymbolHi";
44 def symbolLo: Operand<i32> {
45 let PrintMethod = "printSymbolLo";
48 // Pseudo-instructions:
49 def PHI : Pseudo<(ops), "; PHI">;
51 def ADJCALLSTACKDOWN : Pseudo<(ops), "; ADJCALLSTACKDOWN">;
52 def ADJCALLSTACKUP : Pseudo<(ops), "; ADJCALLSTACKUP">;
54 def IMPLICIT_DEF : Pseudo<(ops), "; IMPLICIT_DEF">;
55 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
57 let isBranch = 1, isTerminator = 1 in {
58 def COND_BRANCH : Pseudo<(ops), "; COND_BRANCH">;
59 def B : IForm<18, 0, 0, 0, 0, (ops target:$func), "b $func">;
60 //def BA : IForm<18, 1, 0, 0, 0, (ops target:$func), "ba $func">;
61 def BL : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
62 //def BLA : IForm<18, 1, 1, 0, 0, (ops target:$func), "bla $func">;
64 // FIXME: 4*CR# needs to be added to the BI field!
65 // This will only work for CR0 as it stands now
66 def BLT : BForm_ext<16, 0, 0, 12, 0, 0, 0, (ops CRRC:$crS, target:$block),
68 def BLE : BForm_ext<16, 0, 0, 4, 1, 0, 0, (ops CRRC:$crS, target:$block),
70 def BEQ : BForm_ext<16, 0, 0, 12, 2, 0, 0, (ops CRRC:$crS, target:$block),
72 def BGE : BForm_ext<16, 0, 0, 4, 0, 0, 0, (ops CRRC:$crS, target:$block),
74 def BGT : BForm_ext<16, 0, 0, 12, 1, 0, 0, (ops CRRC:$crS, target:$block),
76 def BNE : BForm_ext<16, 0, 0, 4, 2, 0, 0, (ops CRRC:$crS, target:$block),
80 let isBranch = 1, isTerminator = 1, isCall = 1,
81 // All calls clobber the non-callee saved registers...
82 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
83 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
85 CR0,CR1,CR5,CR6,CR7] in {
86 // Convenient aliases for call instructions
87 def CALLpcrel : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
88 def CALLindirect : XLForm_2_ext<19, 528, 20, 31, 1, 0, 0, (ops), "bctrl">;
91 // D-Form instructions. Most instructions that perform an operation on a
92 // register and an immediate are of this type.
95 def LBZ : DForm_1<35, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
96 "lbz $rD, $disp($rA)">;
97 def LHA : DForm_1<42, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
98 "lha $rD, $disp($rA)">;
99 def LHZ : DForm_1<40, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
100 "lhz $rD, $disp($rA)">;
101 def LMW : DForm_1<46, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
102 "lmw $rD, $disp($rA)">;
103 def LWZ : DForm_1<32, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
104 "lwz $rD, $disp($rA)">;
105 def LWZU : DForm_1<33, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
106 "lwzu $rD, $disp($rA)">;
108 def ADDI : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
109 "addi $rD, $rA, $imm">;
110 def ADDIC : DForm_2<12, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
111 "addic $rD, $rA, $imm">;
112 def ADDICo : DForm_2<13, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
113 "addic. $rD, $rA, $imm">;
114 def ADDIS : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
115 "addis $rD, $rA, $imm">;
116 def LA : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
117 "la $rD, $sym($rA)">;
118 def LOADHiAddr : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolHi:$sym),
119 "addis $rD, $rA, $sym">;
120 def MULLI : DForm_2< 7, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
121 "mulli $rD, $rA, $imm">;
122 def SUBFIC : DForm_2< 8, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
123 "subfic $rD, $rA, $imm">;
124 def LI : DForm_2_r0<14, 0, 0, (ops GPRC:$rD, s16imm:$imm),
126 def LIS : DForm_2_r0<15, 0, 0, (ops GPRC:$rD, s16imm:$imm),
129 def STMW : DForm_3<47, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
130 "stmw $rS, $disp($rA)">;
131 def STB : DForm_3<38, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
132 "stb $rS, $disp($rA)">;
133 def STBU : DForm_3<39, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
134 "stbu $rS, $disp($rA)">;
135 def STH : DForm_3<44, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
136 "sth $rS, $disp($rA)">;
137 def STHU : DForm_3<45, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
138 "sthu $rS, $disp($rA)">;
139 def STW : DForm_3<36, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
140 "stw $rS, $disp($rA)">;
141 def STWU : DForm_3<37, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
142 "stwu $rS, $disp($rA)">;
144 def ANDIo : DForm_4<28, 0, 0,
145 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
146 "andi. $dst, $src1, $src2">;
147 def ANDISo : DForm_4<29, 0, 0,
148 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
149 "andis. $dst, $src1, $src2">;
150 def ORI : DForm_4<24, 0, 0,
151 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
152 "ori $dst, $src1, $src2">;
153 def ORIS : DForm_4<25, 0, 0,
154 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
155 "oris $dst, $src1, $src2">;
156 def XORI : DForm_4<26, 0, 0,
157 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
158 "xori $dst, $src1, $src2">;
159 def XORIS : DForm_4<27, 0, 0,
160 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
161 "xoris $dst, $src1, $src2">;
162 def NOP : DForm_4_zero<24, 0, 0, (ops), "nop">;
163 def CMPI : DForm_5<11, 0, 0, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
164 "cmpi $crD, $L, $rA, $imm">;
165 def CMPWI : DForm_5_ext<11, 0, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
166 "cmpwi $crD, $rA, $imm">;
167 def CMPDI : DForm_5_ext<11, 1, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
168 "cmpdi $crD, $rA, $imm">;
169 def CMPLI : DForm_6<10, 0, 0,
170 (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
171 "cmpli $dst, $size, $src1, $src2">;
172 def CMPLWI : DForm_6_ext<10, 0, 0,
173 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
174 "cmplwi $dst, $src1, $src2">;
175 def CMPLDI : DForm_6_ext<10, 1, 0,
176 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
177 "cmpldi $dst, $src1, $src2">;
179 def LFS : DForm_8<48, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
180 "lfs $rD, $disp($rA)">;
181 def LFD : DForm_8<50, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
182 "lfd $rD, $disp($rA)">;
185 def STFS : DForm_9<52, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
186 "stfs $rS, $disp($rA)">;
187 def STFD : DForm_9<54, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
188 "stfd $rS, $disp($rA)">;
191 // DS-Form instructions. Load/Store instructions available in PPC-64
194 def LWA : DSForm_1<58, 2, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
195 "lwa $rT, $DS($rA)">;
196 def LD : DSForm_2<58, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
200 def STD : DSForm_2<62, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
201 "std $rT, $DS($rA)">;
202 def STDU : DSForm_2<62, 1, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
203 "stdu $rT, $DS($rA)">;
206 // X-Form instructions. Most instructions that perform an operation on a
207 // register and another register are of this type.
210 def LBZX : XForm_1<31, 87, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
211 "lbzx $dst, $base, $index">;
212 def LHAX : XForm_1<31, 343, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
213 "lhax $dst, $base, $index">;
214 def LHZX : XForm_1<31, 279, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
215 "lhzx $dst, $base, $index">;
216 def LWAX : XForm_1<31, 341, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
217 "lwax $dst, $base, $index">;
218 def LWZX : XForm_1<31, 23, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
219 "lwzx $dst, $base, $index">;
220 def LDX : XForm_1<31, 21, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
221 "ldx $dst, $base, $index">;
223 def MFCR : XForm_5<31, 19, 0, 0, (ops GPRC:$dst), "mfcr $dst">;
224 def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
225 "and $rA, $rS, $rB">;
226 def ANDC : XForm_6<31, 60, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
227 "andc $rA, $rS, $rB">;
228 def EQV : XForm_6<31, 284, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
229 "eqv $rA, $rS, $rB">;
230 def NAND : XForm_6<31, 476, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
231 "nand $rA, $rS, $rB">;
232 def NOR : XForm_6<31, 124, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
233 "nor $rA, $rS, $rB">;
234 def OR : XForm_6<31, 444, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
236 def ORo : XForm_6<31, 444, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
237 "or. $rA, $rS, $rB">;
238 def ORC : XForm_6<31, 412, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
239 "orc $rA, $rS, $rB">;
240 def SLD : XForm_6<31, 27, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
241 "sld $rA, $rS, $rB">;
242 def SLW : XForm_6<31, 24, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
243 "slw $rA, $rS, $rB">;
244 def SRD : XForm_6<31, 539, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
245 "srd $rA, $rS, $rB">;
246 def SRW : XForm_6<31, 536, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
247 "srw $rA, $rS, $rB">;
248 def SRAD : XForm_6<31, 794, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
249 "srad $rA, $rS, $rB">;
250 def SRAW : XForm_6<31, 792, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
251 "sraw $rA, $rS, $rB">;
252 def XOR : XForm_6<31, 316, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
253 "xor $rA, $rS, $rB">;
255 def STBX : XForm_8<31, 215, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
256 "stbx $rS, $rA, $rB">;
257 def STHX : XForm_8<31, 407, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
258 "sthx $rS, $rA, $rB">;
259 def STWX : XForm_8<31, 151, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
260 "stwx $rS, $rA, $rB">;
261 def STWUX : XForm_8<31, 183, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
262 "stwux $rS, $rA, $rB">;
263 def STDX : XForm_8<31, 149, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
264 "stdx $rS, $rA, $rB">;
265 def STDUX : XForm_8<31, 181, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
266 "stdux $rS, $rA, $rB">;
268 def SRAWI : XForm_10<31, 824, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
269 "srawi $rA, $rS, $SH">;
270 def CNTLZW : XForm_11<31, 26, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
272 def EXTSB : XForm_11<31, 954, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
274 def EXTSH : XForm_11<31, 922, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
276 def EXTSW : XForm_11<31, 986, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS),
278 def CMP : XForm_16<31, 0, 0, 0,
279 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
280 "cmp $crD, $long, $rA, $rB">;
281 def CMPL : XForm_16<31, 32, 0, 0,
282 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
283 "cmpl $crD, $long, $rA, $rB">;
284 def CMPW : XForm_16_ext<31, 0, 0, 0,
285 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
286 "cmpw $crD, $rA, $rB">;
287 def CMPD : XForm_16_ext<31, 0, 1, 0,
288 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
289 "cmpd $crD, $rA, $rB">;
290 def CMPLW : XForm_16_ext<31, 32, 0, 0,
291 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
292 "cmplw $crD, $rA, $rB">;
293 def CMPLD : XForm_16_ext<31, 32, 1, 0,
294 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
295 "cmpld $crD, $rA, $rB">;
296 def FCMPU : XForm_17<63, 0, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
297 "fcmpu $crD, $fA, $fB">;
299 def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
300 "lfsx $dst, $base, $index">;
301 def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
302 "lfdx $dst, $base, $index">;
304 def FCFID : XForm_26<63, 846, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
306 def FCTIDZ : XForm_26<63, 815, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
307 "fctidz $frD, $frB">;
308 def FCTIWZ : XForm_26<63, 15, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
309 "fctiwz $frD, $frB">;
310 def FMR : XForm_26<63, 72, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
312 def FNEG : XForm_26<63, 80, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
314 def FRSP : XForm_26<63, 12, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
317 def STFSX : XForm_28<31, 663, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
318 "stfsx $frS, $rA, $rB">;
319 def STFDX : XForm_28<31, 727, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
320 "stfdx $frS, $rA, $rB">;
323 // XL-Form instructions. condition register logical ops.
325 def CRAND : XLForm_1<19, 257, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
327 def CRANDC : XLForm_1<19, 129, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
328 "crandc $D, $A, $B">;
329 def CRNOR : XLForm_1<19, 33, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
331 def CROR : XLForm_1<19, 449, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
334 // XFX-Form instructions. Instructions that deal with SPRs
336 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
337 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
338 // which means the SPR value needs to be multiplied by a factor of 32.
339 def MFCTR : XFXForm_1_ext<31, 339, 288, 0, 0, (ops GPRC:$rT), "mfctr $rT">;
340 def MFLR : XFXForm_1_ext<31, 339, 256, 0, 0, (ops GPRC:$rT), "mflr $rT">;
341 def MTCTR : XFXForm_7_ext<31, 467, 288, 0, 0, (ops GPRC:$rS), "mtctr $rS">;
342 def MTLR : XFXForm_7_ext<31, 467, 256, 0, 0, (ops GPRC:$rS), "mtlr $rS">;
345 // XS-Form instructions. Just 'sradi'
347 def SRADI : XSForm_1<31, 413, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
348 "sradi $rA, $rS, $SH">;
350 // XO-Form instructions. Arithmetic instructions that can set overflow bit
352 def ADD : XOForm_1<31, 266, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
353 "add $rT, $rA, $rB">;
354 def ADDC : XOForm_1<31, 10, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
355 "addc $rT, $rA, $rB">;
356 def ADDE : XOForm_1<31, 138, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
357 "adde $rT, $rA, $rB">;
358 def DIVD : XOForm_1<31, 489, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
359 "divd $rT, $rA, $rB">;
360 def DIVDU : XOForm_1<31, 457, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
361 "divdu $rT, $rA, $rB">;
362 def DIVW : XOForm_1<31, 491, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
363 "divw $rT, $rA, $rB">;
364 def DIVWU : XOForm_1<31, 459, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
365 "divwu $rT, $rA, $rB">;
366 def MULHWU : XOForm_1<31, 11, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
367 "mulhwu $rT, $rA, $rB">;
368 def MULLD : XOForm_1<31, 233, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
369 "mulld $rT, $rA, $rB">;
370 def MULLW : XOForm_1<31, 235, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
371 "mullw $rT, $rA, $rB">;
372 def SUBF : XOForm_1<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
373 "subf $rT, $rA, $rB">;
374 def SUBFC : XOForm_1<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
375 "subfc $rT, $rA, $rB">;
376 def SUBFE : XOForm_1<31, 136, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
377 "subfe $rT, $rA, $rB">;
378 def SUB : XOForm_1r<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
379 "sub $rT, $rA, $rB">;
380 def SUBC : XOForm_1r<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
381 "subc $rT, $rA, $rB">;
382 def ADDME : XOForm_3<31, 234, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
384 def ADDZE : XOForm_3<31, 202, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
386 def NEG : XOForm_3<31, 104, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
388 def SUBFZE : XOForm_3<31, 200, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
391 // A-Form instructions. Most of the instructions executed in the FPU are of
394 def FMADD : AForm_1<63, 29, 0, 0, 0,
395 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
396 "fmadd $FRT, $FRA, $FRC, $FRB">;
397 def FSEL : AForm_1<63, 23, 0, 0, 0,
398 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
399 "fsel $FRT, $FRA, $FRC, $FRB">;
400 def FADD : AForm_2<63, 21, 0, 0, 0,
401 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
402 "fadd $FRT, $FRA, $FRB">;
403 def FADDS : AForm_2<59, 21, 0, 0, 0,
404 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
405 "fadds $FRT, $FRA, $FRB">;
406 def FDIV : AForm_2<63, 18, 0, 0, 0,
407 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
408 "fdiv $FRT, $FRA, $FRB">;
409 def FDIVS : AForm_2<59, 18, 0, 0, 0,
410 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
411 "fdivs $FRT, $FRA, $FRB">;
412 def FMUL : AForm_3<63, 25, 0, 0, 0,
413 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
414 "fmul $FRT, $FRA, $FRB">;
415 def FMULS : AForm_3<59, 25, 0, 0, 0,
416 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
417 "fmuls $FRT, $FRA, $FRB">;
418 def FSUB : AForm_2<63, 20, 0, 0, 0,
419 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
420 "fsub $FRT, $FRA, $FRB">;
421 def FSUBS : AForm_2<59, 20, 0, 0, 0,
422 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
423 "fsubs $FRT, $FRA, $FRB">;
425 // M-Form instructions. rotate and mask instructions.
427 let isTwoAddress = 1 in {
428 def RLWIMI : MForm_2<20, 0, 0, 0,
429 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
430 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
432 def RLWINM : MForm_2<21, 0, 0, 0,
433 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
434 "rlwinm $rA, $rS, $SH, $MB, $ME">;
437 // MD-Form instructions. 64 bit rotate instructions.
439 def RLDICL : MDForm_1<30, 0, 0, 1, 0,
440 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
441 "rldicl $rA, $rS, $SH, $MB">;
442 def RLDICR : MDForm_1<30, 1, 0, 1, 0,
443 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
444 "rldicr $rA, $rS, $SH, $ME">;