1 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PowerPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // Selection DAG Type Constraint definitions.
20 // Note that the semantics of these constraints are hard coded into tblgen. To
21 // modify or add constraints, you have to hack tblgen.
24 class SDTypeConstraint<int opnum> {
25 int OperandNum = opnum;
28 // SDTCisVT - The specified operand has exactly this VT.
29 class SDTCisVT <int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP <int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 //===----------------------------------------------------------------------===//
51 // Selection DAG Type Profile definitions.
53 // These use the constraints defined above to describe the type requirements of
54 // the various nodes. These are not hard coded into tblgen, allowing targets to
55 // add their own if needed.
58 // SDTypeProfile - This profile describes the type requirements of a Selection
60 class SDTypeProfile<int numresults, int numoperands,
61 list<SDTypeConstraint> constraints> {
62 int NumResults = numresults;
63 int NumOperands = numoperands;
64 list<SDTypeConstraint> Constraints = constraints;
68 def SDTImm : SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
69 def SDTVT : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'
70 def SDTBinOp : SDTypeProfile<1, 2, [ // add, mul, etc.
71 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
73 def SDTIntBinOp : SDTypeProfile<1, 2, [ // and, or, xor, udiv, etc.
74 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
76 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
77 SDTCisSameAs<0, 1>, SDTCisInt<0>
79 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
80 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
81 SDTCisVTSmallerThanOp<2, 1>
84 //===----------------------------------------------------------------------===//
85 // Selection DAG Node Properties.
87 // Note: These are hard coded into tblgen.
90 def SDNPCommutative : SDNodeProperty;
92 //===----------------------------------------------------------------------===//
93 // Selection DAG Node definitions.
95 class SDNode<string opcode, SDTypeProfile typeprof,
96 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
97 string Opcode = opcode;
98 string SDClass = sdclass;
99 list<SDNodeProperty> Properties = props;
100 SDTypeProfile TypeProfile = typeprof;
106 def imm : SDNode<"ISD::Constant" , SDTImm , [], "ConstantSDNode">;
107 def vt : SDNode<"ISD::VALUETYPE" , SDTVT , [], "VTSDNode">;
108 def and : SDNode<"ISD::AND" , SDTIntBinOp, [SDNPCommutative]>;
109 def or : SDNode<"ISD::OR" , SDTIntBinOp, [SDNPCommutative]>;
110 def xor : SDNode<"ISD::XOR" , SDTIntBinOp, [SDNPCommutative]>;
111 def add : SDNode<"ISD::ADD" , SDTBinOp , [SDNPCommutative]>;
112 def sub : SDNode<"ISD::SUB" , SDTBinOp>;
113 def mul : SDNode<"ISD::MUL" , SDTBinOp , [SDNPCommutative]>;
114 def sdiv : SDNode<"ISD::SDIV" , SDTBinOp>;
115 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
116 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
117 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
118 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
119 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
121 //===----------------------------------------------------------------------===//
122 // Selection DAG Node Transformation Functions.
124 // This mechanism allows targets to manipulate nodes in the output DAG once a
125 // match has been formed. This is typically used to manipulate immediate
128 class SDNodeXForm<SDNode opc, code xformFunction> {
130 code XFormFunction = xformFunction;
133 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
136 //===----------------------------------------------------------------------===//
137 // Selection DAG Pattern Fragments.
139 // Pattern fragments are reusable chunks of dags that match specific things.
140 // They can take arguments and have C++ predicates that control whether they
141 // match. They are intended to make the patterns for common instructions more
142 // compact and readable.
145 /// PatFrag - Represents a pattern fragment. This can match something on the
146 /// DAG, frame a single node to multiply nested other fragments.
148 class PatFrag<dag ops, dag frag, code pred = [{}],
149 SDNodeXForm xform = NOOP_SDNodeXForm> {
152 code Predicate = pred;
153 SDNodeXForm OperandTransform = xform;
156 // PatLeaf's are pattern fragments that have no operands. This is just a helper
157 // to define immediates and other common things concisely.
158 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
159 : PatFrag<(ops), frag, pred, xform>;
163 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
164 def immZero : PatLeaf<(imm), [{ return N->isNullValue(); }]>;
166 def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
167 def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
169 // Other helper fragments.
171 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
172 def ineg : PatFrag<(ops node:$in), (sub immZero, node:$in)>;
174 //===----------------------------------------------------------------------===//
175 // Selection DAG Pattern Support.
177 // Patterns are what are actually matched against the target-flavored
178 // instruction selection DAG. Instructions defined by the target implicitly
179 // define patterns in most cases, but patterns can also be explicitly added when
180 // an operation is defined by a sequence of instructions (e.g. loading a large
181 // immediate value on RISC targets that do not support immediates as large as
185 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
186 dag PatternToMatch = patternToMatch;
187 list<dag> ResultInstrs = resultInstrs;
190 // Pat - A simple (but common) form of a pattern, which produces a simple result
191 // not needing a full list.
192 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
194 //===----------------------------------------------------------------------===//
195 // PowerPC specific transformation functions and pattern fragments.
197 def LO16 : SDNodeXForm<imm, [{
198 // Transformation function: get the low 16 bits.
199 return getI32Imm((unsigned short)N->getValue());
202 def HI16 : SDNodeXForm<imm, [{
203 // Transformation function: shift the immediate value down into the low bits.
204 return getI32Imm((unsigned)N->getValue() >> 16);
207 def immSExt16 : PatLeaf<(imm), [{
208 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
209 // field. Used by instructions like 'addi'.
210 return (int)N->getValue() == (short)N->getValue();
212 def immZExt16 : PatLeaf<(imm), [{
213 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
214 // field. Used by instructions like 'ori'.
215 return (unsigned)N->getValue() == (unsigned short)N->getValue();
218 def imm16Shifted : PatLeaf<(imm), [{
219 // imm16Shifted predicate - True if only bits in the top 16-bits of the
220 // immediate are set. Used by instructions like 'addis'.
221 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
225 // Example of a legalize expander: Only for PPC64.
226 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
227 [(set f64:$tmp , (FCTIDZ f64:$src)),
228 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
229 (store f64:$tmp, i32:$tmpFI),
230 (set i64:$dst, (load i32:$tmpFI))],
234 //===----------------------------------------------------------------------===//
235 // PowerPC Flag Definitions.
237 class isPPC64 { bit PPC64 = 1; }
238 class isVMX { bit VMX = 1; }
240 list<Register> Defs = [CR0];
246 //===----------------------------------------------------------------------===//
247 // PowerPC Operand Definitions.
249 def u5imm : Operand<i32> {
250 let PrintMethod = "printU5ImmOperand";
252 def u6imm : Operand<i32> {
253 let PrintMethod = "printU6ImmOperand";
255 def s16imm : Operand<i32> {
256 let PrintMethod = "printS16ImmOperand";
258 def u16imm : Operand<i32> {
259 let PrintMethod = "printU16ImmOperand";
261 def target : Operand<i32> {
262 let PrintMethod = "printBranchOperand";
264 def piclabel: Operand<i32> {
265 let PrintMethod = "printPICLabel";
267 def symbolHi: Operand<i32> {
268 let PrintMethod = "printSymbolHi";
270 def symbolLo: Operand<i32> {
271 let PrintMethod = "printSymbolLo";
273 def crbitm: Operand<i8> {
274 let PrintMethod = "printcrbitm";
279 //===----------------------------------------------------------------------===//
280 // PowerPC Instruction Definitions.
282 // Pseudo-instructions:
283 def PHI : Pseudo<(ops variable_ops), "; PHI">;
286 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN">;
287 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP">;
289 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
290 def IMPLICIT_DEF_FP : Pseudo<(ops FPRC:$rD), "; %rD = IMPLICIT_DEF_FP">;
292 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
293 // scheduler into a branch sequence.
294 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
295 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
296 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
297 def SELECT_CC_FP : Pseudo<(ops FPRC:$dst, CRRC:$cond, FPRC:$T, FPRC:$F,
298 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
302 let isTerminator = 1 in {
304 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">;
305 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">;
309 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
311 let isBranch = 1, isTerminator = 1 in {
312 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
313 target:$true, target:$false),
315 def B : IForm<18, 0, 0, (ops target:$func), "b $func">;
316 //def BA : IForm<18, 1, 0, (ops target:$func), "ba $func">;
317 def BL : IForm<18, 0, 1, (ops target:$func), "bl $func">;
318 //def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func">;
320 // FIXME: 4*CR# needs to be added to the BI field!
321 // This will only work for CR0 as it stands now
322 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
324 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
326 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
328 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
330 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
332 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
337 // All calls clobber the non-callee saved registers...
338 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
339 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
341 CR0,CR1,CR5,CR6,CR7] in {
342 // Convenient aliases for call instructions
343 def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops), "bl $func">;
344 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1,
345 (ops variable_ops), "bctrl">;
348 // D-Form instructions. Most instructions that perform an operation on a
349 // register and an immediate are of this type.
352 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
353 "lbz $rD, $disp($rA)">;
354 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
355 "lha $rD, $disp($rA)">;
356 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
357 "lhz $rD, $disp($rA)">;
358 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
359 "lmw $rD, $disp($rA)">;
360 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
361 "lwz $rD, $disp($rA)">;
362 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
363 "lwzu $rD, $disp($rA)">;
365 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
366 "addi $rD, $rA, $imm",
367 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
368 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
369 "addic $rD, $rA, $imm",
371 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
372 "addic. $rD, $rA, $imm",
374 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
375 "addis $rD, $rA, $imm",
376 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
377 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
380 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
381 "mulli $rD, $rA, $imm",
382 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
383 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
384 "subfic $rD, $rA, $imm",
386 def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
388 [(set GPRC:$rD, immSExt16:$imm)]>;
389 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
391 [(set GPRC:$rD, imm16Shifted:$imm)]>;
393 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
394 "stmw $rS, $disp($rA)">;
395 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
396 "stb $rS, $disp($rA)">;
397 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
398 "sth $rS, $disp($rA)">;
399 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
400 "stw $rS, $disp($rA)">;
401 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
402 "stwu $rS, $disp($rA)">;
404 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
405 "andi. $dst, $src1, $src2",
407 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
408 "andis. $dst, $src1, $src2",
410 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
411 "ori $dst, $src1, $src2",
412 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
413 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
414 "oris $dst, $src1, $src2",
415 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
416 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
417 "xori $dst, $src1, $src2",
418 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
419 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
420 "xoris $dst, $src1, $src2",
421 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
422 def NOP : DForm_4_zero<24, (ops), "nop">;
423 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
424 "cmpi $crD, $L, $rA, $imm">;
425 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
426 "cmpwi $crD, $rA, $imm">;
427 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
428 "cmpdi $crD, $rA, $imm">, isPPC64;
429 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
430 "cmpli $dst, $size, $src1, $src2">;
431 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
432 "cmplwi $dst, $src1, $src2">;
433 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
434 "cmpldi $dst, $src1, $src2">, isPPC64;
436 def LFS : DForm_8<48, (ops FPRC:$rD, symbolLo:$disp, GPRC:$rA),
437 "lfs $rD, $disp($rA)">;
438 def LFD : DForm_8<50, (ops FPRC:$rD, symbolLo:$disp, GPRC:$rA),
439 "lfd $rD, $disp($rA)">;
442 def STFS : DForm_9<52, (ops FPRC:$rS, symbolLo:$disp, GPRC:$rA),
443 "stfs $rS, $disp($rA)">;
444 def STFD : DForm_9<54, (ops FPRC:$rS, symbolLo:$disp, GPRC:$rA),
445 "stfd $rS, $disp($rA)">;
448 // DS-Form instructions. Load/Store instructions available in PPC-64
451 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
452 "lwa $rT, $DS($rA)">, isPPC64;
453 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
454 "ld $rT, $DS($rA)">, isPPC64;
457 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
458 "std $rT, $DS($rA)">, isPPC64;
459 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
460 "stdu $rT, $DS($rA)">, isPPC64;
463 // X-Form instructions. Most instructions that perform an operation on a
464 // register and another register are of this type.
467 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
468 "lbzx $dst, $base, $index">;
469 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
470 "lhax $dst, $base, $index">;
471 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
472 "lhzx $dst, $base, $index">;
473 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
474 "lwax $dst, $base, $index">, isPPC64;
475 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
476 "lwzx $dst, $base, $index">;
477 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
478 "ldx $dst, $base, $index">, isPPC64;
480 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
481 "nand $rA, $rS, $rB",
482 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
483 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
485 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
486 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
487 "and. $rA, $rS, $rB",
489 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
490 "andc $rA, $rS, $rB",
491 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
492 def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
494 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
495 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
497 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
498 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
501 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
503 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
504 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
506 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
507 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
509 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
510 def SLD : XForm_6<31, 27, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
513 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
516 def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
519 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
522 def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
523 "srad $rA, $rS, $rB",
525 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
526 "sraw $rA, $rS, $rB",
529 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
530 "stbx $rS, $rA, $rB">;
531 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
532 "sthx $rS, $rA, $rB">;
533 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
534 "stwx $rS, $rA, $rB">;
535 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
536 "stwux $rS, $rA, $rB">;
537 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
538 "stdx $rS, $rA, $rB">, isPPC64;
539 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
540 "stdux $rS, $rA, $rB">, isPPC64;
542 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
543 "srawi $rA, $rS, $SH">;
544 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
546 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
547 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
549 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
550 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
552 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
553 def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
556 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
557 "cmp $crD, $long, $rA, $rB">;
558 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
559 "cmpl $crD, $long, $rA, $rB">;
560 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
561 "cmpw $crD, $rA, $rB">;
562 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
563 "cmpd $crD, $rA, $rB">, isPPC64;
564 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
565 "cmplw $crD, $rA, $rB">;
566 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
567 "cmpld $crD, $rA, $rB">, isPPC64;
568 def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
569 "fcmpo $crD, $fA, $fB">;
570 def FCMPU : XForm_17<63, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
571 "fcmpu $crD, $fA, $fB">;
573 def LFSX : XForm_25<31, 535, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
574 "lfsx $dst, $base, $index">;
575 def LFDX : XForm_25<31, 599, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
576 "lfdx $dst, $base, $index">;
578 def FCFID : XForm_26<63, 846, (ops FPRC:$frD, FPRC:$frB),
579 "fcfid $frD, $frB">, isPPC64;
580 def FCTIDZ : XForm_26<63, 815, (ops FPRC:$frD, FPRC:$frB),
581 "fctidz $frD, $frB">, isPPC64;
582 def FCTIWZ : XForm_26<63, 15, (ops FPRC:$frD, FPRC:$frB),
583 "fctiwz $frD, $frB">;
584 def FABS : XForm_26<63, 264, (ops FPRC:$frD, FPRC:$frB),
586 def FMR : XForm_26<63, 72, (ops FPRC:$frD, FPRC:$frB),
588 def FNABS : XForm_26<63, 136, (ops FPRC:$frD, FPRC:$frB),
590 def FNEG : XForm_26<63, 40, (ops FPRC:$frD, FPRC:$frB),
592 def FRSP : XForm_26<63, 12, (ops FPRC:$frD, FPRC:$frB),
594 def FSQRT : XForm_26<63, 22, (ops FPRC:$frD, FPRC:$frB),
596 def FSQRTS : XForm_26<59, 22, (ops FPRC:$frD, FPRC:$frB),
597 "fsqrts $frD, $frB">;
600 def STFSX : XForm_28<31, 663, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
601 "stfsx $frS, $rA, $rB">;
602 def STFDX : XForm_28<31, 727, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
603 "stfdx $frS, $rA, $rB">;
606 // XL-Form instructions. condition register logical ops.
608 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
611 // XFX-Form instructions. Instructions that deal with SPRs
613 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
614 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
615 // which means the SPR value needs to be multiplied by a factor of 32.
616 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT">;
617 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT">;
618 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">;
619 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
621 def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
623 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">;
624 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;
626 // XS-Form instructions. Just 'sradi'
628 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
629 "sradi $rA, $rS, $SH">, isPPC64;
631 // XO-Form instructions. Arithmetic instructions that can set overflow bit
633 def ADD : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
635 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
636 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
637 "addc $rT, $rA, $rB",
639 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
640 "adde $rT, $rA, $rB",
642 def DIVD : XOForm_1<31, 489, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
643 "divd $rT, $rA, $rB",
645 def DIVDU : XOForm_1<31, 457, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
646 "divdu $rT, $rA, $rB",
648 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
649 "divw $rT, $rA, $rB",
650 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
651 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
652 "divwu $rT, $rA, $rB",
653 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
654 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
655 "mulhw $rT, $rA, $rB",
656 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
657 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
658 "mulhwu $rT, $rA, $rB",
659 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
660 def MULLD : XOForm_1<31, 233, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
661 "mulld $rT, $rA, $rB",
663 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
664 "mullw $rT, $rA, $rB",
665 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
666 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
667 "subf $rT, $rA, $rB",
668 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
669 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
670 "subfc $rT, $rA, $rB",
672 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
673 "subfe $rT, $rA, $rB",
675 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
678 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
681 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
683 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
684 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
688 // A-Form instructions. Most of the instructions executed in the FPU are of
691 def FMADD : AForm_1<63, 29,
692 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
693 "fmadd $FRT, $FRA, $FRC, $FRB">;
694 def FMADDS : AForm_1<59, 29,
695 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
696 "fmadds $FRT, $FRA, $FRC, $FRB">;
697 def FMSUB : AForm_1<63, 28,
698 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
699 "fmsub $FRT, $FRA, $FRC, $FRB">;
700 def FMSUBS : AForm_1<59, 28,
701 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
702 "fmsubs $FRT, $FRA, $FRC, $FRB">;
703 def FNMADD : AForm_1<63, 31,
704 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
705 "fnmadd $FRT, $FRA, $FRC, $FRB">;
706 def FNMADDS : AForm_1<59, 31,
707 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
708 "fnmadds $FRT, $FRA, $FRC, $FRB">;
709 def FNMSUB : AForm_1<63, 30,
710 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
711 "fnmsub $FRT, $FRA, $FRC, $FRB">;
712 def FNMSUBS : AForm_1<59, 30,
713 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
714 "fnmsubs $FRT, $FRA, $FRC, $FRB">;
715 def FSEL : AForm_1<63, 23,
716 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
717 "fsel $FRT, $FRA, $FRC, $FRB">;
718 def FADD : AForm_2<63, 21,
719 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
720 "fadd $FRT, $FRA, $FRB">;
721 def FADDS : AForm_2<59, 21,
722 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
723 "fadds $FRT, $FRA, $FRB">;
724 def FDIV : AForm_2<63, 18,
725 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
726 "fdiv $FRT, $FRA, $FRB">;
727 def FDIVS : AForm_2<59, 18,
728 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
729 "fdivs $FRT, $FRA, $FRB">;
730 def FMUL : AForm_3<63, 25,
731 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
732 "fmul $FRT, $FRA, $FRB">;
733 def FMULS : AForm_3<59, 25,
734 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
735 "fmuls $FRT, $FRA, $FRB">;
736 def FSUB : AForm_2<63, 20,
737 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
738 "fsub $FRT, $FRA, $FRB">;
739 def FSUBS : AForm_2<59, 20,
740 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
741 "fsubs $FRT, $FRA, $FRB">;
743 // M-Form instructions. rotate and mask instructions.
745 let isTwoAddress = 1, isCommutable = 1 in {
746 // RLWIMI can be commuted if the rotate amount is zero.
747 def RLWIMI : MForm_2<20,
748 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
749 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
751 def RLWINM : MForm_2<21,
752 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
753 "rlwinm $rA, $rS, $SH, $MB, $ME">;
754 def RLWINMo : MForm_2<21,
755 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
756 "rlwinm. $rA, $rS, $SH, $MB, $ME">, isDOT;
757 def RLWNM : MForm_2<23,
758 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
759 "rlwnm $rA, $rS, $rB, $MB, $ME">;
761 // MD-Form instructions. 64 bit rotate instructions.
763 def RLDICL : MDForm_1<30, 0,
764 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
765 "rldicl $rA, $rS, $SH, $MB">, isPPC64;
766 def RLDICR : MDForm_1<30, 1,
767 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
768 "rldicr $rA, $rS, $SH, $ME">, isPPC64;
770 //===----------------------------------------------------------------------===//
771 // PowerPC Instruction Patterns
774 // Arbitrary immediate support. Implement in terms of LIS/ORI.
775 def : Pat<(i32 imm:$imm),
776 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
779 // Implement the 'not' operation with the NOR instruction.
780 def NOT : Pat<(not GPRC:$in),
781 (NOR GPRC:$in, GPRC:$in)>;
784 def EQV1 : Pat<(xor (not GPRC:$in1), GPRC:$in2),
785 (EQV GPRC:$in1, GPRC:$in2)>;
786 // FIXME: This should be autogenerated from the above due to xor commutativity.
787 def EQV2 : Pat<(xor GPRC:$in1, (not GPRC:$in2)),
788 (EQV GPRC:$in1, GPRC:$in2)>;
790 // or by an arbitrary immediate.
791 def : Pat<(or GPRC:$in, imm:$imm),
792 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
793 // xor by an arbitrary immediate.
794 def : Pat<(xor GPRC:$in, imm:$imm),
795 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
799 // Same as above, but using a temporary. FIXME: implement temporaries :)
801 def : Pattern<(xor GPRC:$in, imm:$imm),
802 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
803 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
807 //===----------------------------------------------------------------------===//
808 // PowerPCInstrInfo Definition
810 def PowerPCInstrInfo : InstrInfo {
813 let TSFlagsFields = [ "VMX", "PPC64" ];
814 let TSFlagsShifts = [ 0, 1 ];
816 let isLittleEndianEncoding = 1;