1 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PowerPCInstrFormats.td"
17 class SDNode<string Opc> {
22 def and : SDNode<"ISD::AND">;
23 def or : SDNode<"ISD::OR">;
24 def xor : SDNode<"ISD::XOR">;
25 def add : SDNode<"ISD::ADD">;
26 def sub : SDNode<"ISD::SUB">;
27 def mul : SDNode<"ISD::MUL">;
28 def sdiv : SDNode<"ISD::SDIV">;
29 def udiv : SDNode<"ISD::UDIV">;
30 def mulhs : SDNode<"ISD::MULHS">;
31 def mulhu : SDNode<"ISD::MULHU">;
32 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG">;
33 def ctlz : SDNode<"ISD::CTLZ">;
36 class isPPC64 { bit PPC64 = 1; }
37 class isVMX { bit VMX = 1; }
39 list<Register> Defs = [CR0];
43 let isTerminator = 1 in {
45 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">;
46 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">;
49 def u5imm : Operand<i8> {
50 let PrintMethod = "printU5ImmOperand";
52 def u6imm : Operand<i8> {
53 let PrintMethod = "printU6ImmOperand";
55 def s16imm : Operand<i16> {
56 let PrintMethod = "printS16ImmOperand";
58 def u16imm : Operand<i16> {
59 let PrintMethod = "printU16ImmOperand";
61 def target : Operand<i32> {
62 let PrintMethod = "printBranchOperand";
64 def piclabel: Operand<i32> {
65 let PrintMethod = "printPICLabel";
67 def symbolHi: Operand<i32> {
68 let PrintMethod = "printSymbolHi";
70 def symbolLo: Operand<i32> {
71 let PrintMethod = "printSymbolLo";
73 def crbitm: Operand<i8> {
74 let PrintMethod = "printcrbitm";
77 // Pseudo-instructions:
78 def PHI : Pseudo<(ops variable_ops), "; PHI">;
80 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm), "; ADJCALLSTACKDOWN">;
81 def ADJCALLSTACKUP : Pseudo<(ops u16imm), "; ADJCALLSTACKUP">;
83 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
84 def IMPLICIT_DEF_FP : Pseudo<(ops FPRC:$rD), "; %rD = IMPLICIT_DEF_FP">;
86 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
87 // scheduler into a branch sequence.
88 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
89 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
90 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
91 def SELECT_CC_FP : Pseudo<(ops FPRC:$dst, CRRC:$cond, FPRC:$T, FPRC:$F,
92 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
97 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
99 let isBranch = 1, isTerminator = 1 in {
100 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm, target:$true, target:$false),
102 def B : IForm<18, 0, 0, (ops target:$func), "b $func">;
103 //def BA : IForm<18, 1, 0, (ops target:$func), "ba $func">;
104 def BL : IForm<18, 0, 1, (ops target:$func), "bl $func">;
105 //def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func">;
107 // FIXME: 4*CR# needs to be added to the BI field!
108 // This will only work for CR0 as it stands now
109 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
111 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
113 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
115 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
117 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
119 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
124 // All calls clobber the non-callee saved registers...
125 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
126 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
128 CR0,CR1,CR5,CR6,CR7] in {
129 // Convenient aliases for call instructions
130 def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops), "bl $func">;
131 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1,
132 (ops variable_ops), "bctrl">;
135 // D-Form instructions. Most instructions that perform an operation on a
136 // register and an immediate are of this type.
139 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
140 "lbz $rD, $disp($rA)">;
141 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
142 "lha $rD, $disp($rA)">;
143 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
144 "lhz $rD, $disp($rA)">;
145 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
146 "lmw $rD, $disp($rA)">;
147 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
148 "lwz $rD, $disp($rA)">;
149 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
150 "lwzu $rD, $disp($rA)">;
152 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
153 "addi $rD, $rA, $imm">;
154 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
155 "addic $rD, $rA, $imm">;
156 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
157 "addic. $rD, $rA, $imm">;
158 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
159 "addis $rD, $rA, $imm">;
160 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
161 "la $rD, $sym($rA)">;
162 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
163 "mulli $rD, $rA, $imm">;
164 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
165 "subfic $rD, $rA, $imm">;
166 def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
168 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
171 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
172 "stmw $rS, $disp($rA)">;
173 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
174 "stb $rS, $disp($rA)">;
175 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
176 "sth $rS, $disp($rA)">;
177 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
178 "stw $rS, $disp($rA)">;
179 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
180 "stwu $rS, $disp($rA)">;
182 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
183 "andi. $dst, $src1, $src2">, isDOT;
184 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
185 "andis. $dst, $src1, $src2">, isDOT;
186 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
187 "ori $dst, $src1, $src2">;
188 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
189 "oris $dst, $src1, $src2">;
190 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
191 "xori $dst, $src1, $src2">;
192 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
193 "xoris $dst, $src1, $src2">;
194 def NOP : DForm_4_zero<24, (ops), "nop">;
195 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
196 "cmpi $crD, $L, $rA, $imm">;
197 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
198 "cmpwi $crD, $rA, $imm">;
199 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
200 "cmpdi $crD, $rA, $imm">, isPPC64;
201 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
202 "cmpli $dst, $size, $src1, $src2">;
203 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
204 "cmplwi $dst, $src1, $src2">;
205 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
206 "cmpldi $dst, $src1, $src2">, isPPC64;
208 def LFS : DForm_8<48, (ops FPRC:$rD, symbolLo:$disp, GPRC:$rA),
209 "lfs $rD, $disp($rA)">;
210 def LFD : DForm_8<50, (ops FPRC:$rD, symbolLo:$disp, GPRC:$rA),
211 "lfd $rD, $disp($rA)">;
214 def STFS : DForm_9<52, (ops FPRC:$rS, symbolLo:$disp, GPRC:$rA),
215 "stfs $rS, $disp($rA)">;
216 def STFD : DForm_9<54, (ops FPRC:$rS, symbolLo:$disp, GPRC:$rA),
217 "stfd $rS, $disp($rA)">;
220 // DS-Form instructions. Load/Store instructions available in PPC-64
223 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
224 "lwa $rT, $DS($rA)">, isPPC64;
225 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
226 "ld $rT, $DS($rA)">, isPPC64;
229 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
230 "std $rT, $DS($rA)">, isPPC64;
231 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
232 "stdu $rT, $DS($rA)">, isPPC64;
235 // X-Form instructions. Most instructions that perform an operation on a
236 // register and another register are of this type.
239 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
240 "lbzx $dst, $base, $index">;
241 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
242 "lhax $dst, $base, $index">;
243 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
244 "lhzx $dst, $base, $index">;
245 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
246 "lwax $dst, $base, $index">, isPPC64;
247 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
248 "lwzx $dst, $base, $index">;
249 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
250 "ldx $dst, $base, $index">, isPPC64;
252 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
254 [(set GPRC:$rT, (and GPRC:$rA, GPRC:$rB))]>;
255 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
256 "and. $rA, $rS, $rB",
258 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
259 "andc $rA, $rS, $rB",
261 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
264 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
265 "nand $rA, $rS, $rB",
267 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
270 def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
272 [(set GPRC:$rT, (or GPRC:$rA, GPRC:$rB))]>;
273 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
276 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
279 def SLD : XForm_6<31, 27, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
282 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
285 def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
288 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
291 def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
292 "srad $rA, $rS, $rB",
294 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
295 "sraw $rA, $rS, $rB",
297 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
299 [(set GPRC:$rT, (xor GPRC:$rA, GPRC:$rB))]>;
301 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
302 "stbx $rS, $rA, $rB">;
303 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
304 "sthx $rS, $rA, $rB">;
305 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
306 "stwx $rS, $rA, $rB">;
307 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
308 "stwux $rS, $rA, $rB">;
309 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
310 "stdx $rS, $rA, $rB">, isPPC64;
311 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
312 "stdux $rS, $rA, $rB">, isPPC64;
314 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
315 "srawi $rA, $rS, $SH">;
316 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
318 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
319 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
321 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
322 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
324 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
325 def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
328 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
329 "cmp $crD, $long, $rA, $rB">;
330 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
331 "cmpl $crD, $long, $rA, $rB">;
332 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
333 "cmpw $crD, $rA, $rB">;
334 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
335 "cmpd $crD, $rA, $rB">, isPPC64;
336 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
337 "cmplw $crD, $rA, $rB">;
338 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
339 "cmpld $crD, $rA, $rB">, isPPC64;
340 def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
341 "fcmpo $crD, $fA, $fB">;
342 def FCMPU : XForm_17<63, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
343 "fcmpu $crD, $fA, $fB">;
345 def LFSX : XForm_25<31, 535, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
346 "lfsx $dst, $base, $index">;
347 def LFDX : XForm_25<31, 599, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
348 "lfdx $dst, $base, $index">;
350 def FCFID : XForm_26<63, 846, (ops FPRC:$frD, FPRC:$frB),
351 "fcfid $frD, $frB">, isPPC64;
352 def FCTIDZ : XForm_26<63, 815, (ops FPRC:$frD, FPRC:$frB),
353 "fctidz $frD, $frB">, isPPC64;
354 def FCTIWZ : XForm_26<63, 15, (ops FPRC:$frD, FPRC:$frB),
355 "fctiwz $frD, $frB">;
356 def FABS : XForm_26<63, 264, (ops FPRC:$frD, FPRC:$frB),
358 def FMR : XForm_26<63, 72, (ops FPRC:$frD, FPRC:$frB),
360 def FNABS : XForm_26<63, 136, (ops FPRC:$frD, FPRC:$frB),
362 def FNEG : XForm_26<63, 40, (ops FPRC:$frD, FPRC:$frB),
364 def FRSP : XForm_26<63, 12, (ops FPRC:$frD, FPRC:$frB),
366 def FSQRT : XForm_26<63, 22, (ops FPRC:$frD, FPRC:$frB),
368 def FSQRTS : XForm_26<59, 22, (ops FPRC:$frD, FPRC:$frB),
369 "fsqrts $frD, $frB">;
372 def STFSX : XForm_28<31, 663, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
373 "stfsx $frS, $rA, $rB">;
374 def STFDX : XForm_28<31, 727, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
375 "stfdx $frS, $rA, $rB">;
378 // XL-Form instructions. condition register logical ops.
380 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
383 // XFX-Form instructions. Instructions that deal with SPRs
385 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
386 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
387 // which means the SPR value needs to be multiplied by a factor of 32.
388 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT">;
389 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT">;
390 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">;
391 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
393 def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
395 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">;
396 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;
398 // XS-Form instructions. Just 'sradi'
400 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
401 "sradi $rA, $rS, $SH">, isPPC64;
403 // XO-Form instructions. Arithmetic instructions that can set overflow bit
405 def ADD : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
407 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
408 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
409 "addc $rT, $rA, $rB",
411 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
412 "adde $rT, $rA, $rB",
414 def DIVD : XOForm_1<31, 489, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
415 "divd $rT, $rA, $rB",
417 def DIVDU : XOForm_1<31, 457, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
418 "divdu $rT, $rA, $rB",
420 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
421 "divw $rT, $rA, $rB",
422 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
423 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
424 "divwu $rT, $rA, $rB",
425 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
426 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
427 "mulhw $rT, $rA, $rB",
428 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
429 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
430 "mulhwu $rT, $rA, $rB",
431 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
432 def MULLD : XOForm_1<31, 233, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
433 "mulld $rT, $rA, $rB",
435 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
436 "mullw $rT, $rA, $rB",
437 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
438 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
439 "subf $rT, $rA, $rB",
440 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
441 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
442 "subfc $rT, $rA, $rB",
444 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
445 "subfe $rT, $rA, $rB",
447 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
449 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
451 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
453 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
456 // A-Form instructions. Most of the instructions executed in the FPU are of
459 def FMADD : AForm_1<63, 29,
460 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
461 "fmadd $FRT, $FRA, $FRC, $FRB">;
462 def FMADDS : AForm_1<59, 29,
463 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
464 "fmadds $FRT, $FRA, $FRC, $FRB">;
465 def FMSUB : AForm_1<63, 28,
466 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
467 "fmsub $FRT, $FRA, $FRC, $FRB">;
468 def FMSUBS : AForm_1<59, 28,
469 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
470 "fmsubs $FRT, $FRA, $FRC, $FRB">;
471 def FNMADD : AForm_1<63, 31,
472 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
473 "fnmadd $FRT, $FRA, $FRC, $FRB">;
474 def FNMADDS : AForm_1<59, 31,
475 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
476 "fnmadds $FRT, $FRA, $FRC, $FRB">;
477 def FNMSUB : AForm_1<63, 30,
478 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
479 "fnmsub $FRT, $FRA, $FRC, $FRB">;
480 def FNMSUBS : AForm_1<59, 30,
481 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
482 "fnmsubs $FRT, $FRA, $FRC, $FRB">;
483 def FSEL : AForm_1<63, 23,
484 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
485 "fsel $FRT, $FRA, $FRC, $FRB">;
486 def FADD : AForm_2<63, 21,
487 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
488 "fadd $FRT, $FRA, $FRB">;
489 def FADDS : AForm_2<59, 21,
490 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
491 "fadds $FRT, $FRA, $FRB">;
492 def FDIV : AForm_2<63, 18,
493 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
494 "fdiv $FRT, $FRA, $FRB">;
495 def FDIVS : AForm_2<59, 18,
496 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
497 "fdivs $FRT, $FRA, $FRB">;
498 def FMUL : AForm_3<63, 25,
499 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
500 "fmul $FRT, $FRA, $FRB">;
501 def FMULS : AForm_3<59, 25,
502 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
503 "fmuls $FRT, $FRA, $FRB">;
504 def FSUB : AForm_2<63, 20,
505 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
506 "fsub $FRT, $FRA, $FRB">;
507 def FSUBS : AForm_2<59, 20,
508 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
509 "fsubs $FRT, $FRA, $FRB">;
511 // M-Form instructions. rotate and mask instructions.
513 let isTwoAddress = 1 in {
514 def RLWIMI : MForm_2<20,
515 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
516 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
518 def RLWINM : MForm_2<21,
519 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
520 "rlwinm $rA, $rS, $SH, $MB, $ME">;
521 def RLWINMo : MForm_2<21,
522 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
523 "rlwinm. $rA, $rS, $SH, $MB, $ME">, isDOT;
524 def RLWNM : MForm_2<23,
525 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
526 "rlwnm $rA, $rS, $rB, $MB, $ME">;
528 // MD-Form instructions. 64 bit rotate instructions.
530 def RLDICL : MDForm_1<30, 0,
531 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
532 "rldicl $rA, $rS, $SH, $MB">, isPPC64;
533 def RLDICR : MDForm_1<30, 1,
534 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
535 "rldicr $rA, $rS, $SH, $ME">, isPPC64;
537 def PowerPCInstrInfo : InstrInfo {
540 let TSFlagsFields = [ "VMX", "PPC64" ];
541 let TSFlagsShifts = [ 0, 1 ];
543 let isLittleEndianEncoding = 1;