1 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PowerPCInstrFormats.td"
17 class SDNode<string opcode, string sdclass = "SDNode"> {
18 string Opcode = opcode;
19 string SDClass = sdclass;
25 def imm : SDNode<"ISD::Constant", "ConstantSDNode">;
26 def vt : SDNode<"ISD::VALUETYPE", "VTSDNode">;
27 def and : SDNode<"ISD::AND">;
28 def or : SDNode<"ISD::OR">;
29 def xor : SDNode<"ISD::XOR">;
30 def add : SDNode<"ISD::ADD">;
31 def sub : SDNode<"ISD::SUB">;
32 def mul : SDNode<"ISD::MUL">;
33 def sdiv : SDNode<"ISD::SDIV">;
34 def udiv : SDNode<"ISD::UDIV">;
35 def mulhs : SDNode<"ISD::MULHS">;
36 def mulhu : SDNode<"ISD::MULHU">;
37 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG">;
38 def ctlz : SDNode<"ISD::CTLZ">;
40 /// PatFrag - Represents a pattern fragment. This can match something on the
41 /// DAG, frame a single node to multiply nested other fragments.
43 class PatFrag<dag ops, dag frag, code pred = [{}], code xform = [{}]> {
46 code Predicate = pred;
47 code OperandTransform = xform;
50 // PatLeaf's are pattern fragments that have no operands. This is just a helper
51 // to define immediates and other common things concisely.
52 class PatLeaf<dag frag, code pred = [{}], code xform = [{}]>
53 : PatFrag<(ops), frag, pred, xform>;
57 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
58 def immZero : PatLeaf<(imm), [{ return N->isNullValue(); }]>;
60 def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
61 def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
63 // Other helper fragments.
65 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
66 def ineg : PatFrag<(ops node:$in), (sub immZero, node:$in)>;
68 // PowerPC-Specific predicates.
70 def immSExt16 : PatLeaf<(imm), [{
71 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
72 // field. Used by instructions like 'addi'.
73 return (int)N->getValue() == (short)N->getValue();
75 def imm16Shifted : PatLeaf<(imm), [{
76 // imm16Shifted predicate - True if only bits in the top 16-bits of the
77 // immediate are set. Used by instructions like 'addis'.
78 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
80 // Transformation predicate: shift the immediate value down into the low bits.
81 return getI32Imm((unsigned)N->getValue() >> 16);
85 class isPPC64 { bit PPC64 = 1; }
86 class isVMX { bit VMX = 1; }
88 list<Register> Defs = [CR0];
92 let isTerminator = 1 in {
94 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">;
95 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">;
98 def u5imm : Operand<i8> {
99 let PrintMethod = "printU5ImmOperand";
101 def u6imm : Operand<i8> {
102 let PrintMethod = "printU6ImmOperand";
104 def s16imm : Operand<i16> {
105 let PrintMethod = "printS16ImmOperand";
107 def u16imm : Operand<i16> {
108 let PrintMethod = "printU16ImmOperand";
110 def target : Operand<i32> {
111 let PrintMethod = "printBranchOperand";
113 def piclabel: Operand<i32> {
114 let PrintMethod = "printPICLabel";
116 def symbolHi: Operand<i32> {
117 let PrintMethod = "printSymbolHi";
119 def symbolLo: Operand<i32> {
120 let PrintMethod = "printSymbolLo";
122 def crbitm: Operand<i8> {
123 let PrintMethod = "printcrbitm";
126 // Pseudo-instructions:
127 def PHI : Pseudo<(ops variable_ops), "; PHI">;
129 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm), "; ADJCALLSTACKDOWN">;
130 def ADJCALLSTACKUP : Pseudo<(ops u16imm), "; ADJCALLSTACKUP">;
132 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
133 def IMPLICIT_DEF_FP : Pseudo<(ops FPRC:$rD), "; %rD = IMPLICIT_DEF_FP">;
135 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
136 // scheduler into a branch sequence.
137 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
138 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
139 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
140 def SELECT_CC_FP : Pseudo<(ops FPRC:$dst, CRRC:$cond, FPRC:$T, FPRC:$F,
141 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
146 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
148 let isBranch = 1, isTerminator = 1 in {
149 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm, target:$true, target:$false),
151 def B : IForm<18, 0, 0, (ops target:$func), "b $func">;
152 //def BA : IForm<18, 1, 0, (ops target:$func), "ba $func">;
153 def BL : IForm<18, 0, 1, (ops target:$func), "bl $func">;
154 //def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func">;
156 // FIXME: 4*CR# needs to be added to the BI field!
157 // This will only work for CR0 as it stands now
158 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
160 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
162 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
164 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
166 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
168 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
173 // All calls clobber the non-callee saved registers...
174 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
175 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
177 CR0,CR1,CR5,CR6,CR7] in {
178 // Convenient aliases for call instructions
179 def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops), "bl $func">;
180 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1,
181 (ops variable_ops), "bctrl">;
184 // D-Form instructions. Most instructions that perform an operation on a
185 // register and an immediate are of this type.
188 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
189 "lbz $rD, $disp($rA)">;
190 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
191 "lha $rD, $disp($rA)">;
192 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
193 "lhz $rD, $disp($rA)">;
194 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
195 "lmw $rD, $disp($rA)">;
196 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
197 "lwz $rD, $disp($rA)">;
198 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
199 "lwzu $rD, $disp($rA)">;
201 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
202 "addi $rD, $rA, $imm",
203 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
204 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
205 "addic $rD, $rA, $imm",
207 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
208 "addic. $rD, $rA, $imm",
210 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
211 "addis $rD, $rA, $imm",
212 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
213 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
216 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
217 "mulli $rD, $rA, $imm",
218 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
219 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
220 "subfic $rD, $rA, $imm",
222 def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
224 [(set GPRC:$rD, immSExt16:$imm)]>;
225 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
227 [(set GPRC:$rD, imm16Shifted:$imm)]>;
229 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
230 "stmw $rS, $disp($rA)">;
231 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
232 "stb $rS, $disp($rA)">;
233 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
234 "sth $rS, $disp($rA)">;
235 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
236 "stw $rS, $disp($rA)">;
237 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
238 "stwu $rS, $disp($rA)">;
240 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
241 "andi. $dst, $src1, $src2">, isDOT;
242 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
243 "andis. $dst, $src1, $src2">, isDOT;
244 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
245 "ori $dst, $src1, $src2">;
246 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
247 "oris $dst, $src1, $src2">;
248 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
249 "xori $dst, $src1, $src2">;
250 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
251 "xoris $dst, $src1, $src2">;
252 def NOP : DForm_4_zero<24, (ops), "nop">;
253 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
254 "cmpi $crD, $L, $rA, $imm">;
255 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
256 "cmpwi $crD, $rA, $imm">;
257 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
258 "cmpdi $crD, $rA, $imm">, isPPC64;
259 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
260 "cmpli $dst, $size, $src1, $src2">;
261 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
262 "cmplwi $dst, $src1, $src2">;
263 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
264 "cmpldi $dst, $src1, $src2">, isPPC64;
266 def LFS : DForm_8<48, (ops FPRC:$rD, symbolLo:$disp, GPRC:$rA),
267 "lfs $rD, $disp($rA)">;
268 def LFD : DForm_8<50, (ops FPRC:$rD, symbolLo:$disp, GPRC:$rA),
269 "lfd $rD, $disp($rA)">;
272 def STFS : DForm_9<52, (ops FPRC:$rS, symbolLo:$disp, GPRC:$rA),
273 "stfs $rS, $disp($rA)">;
274 def STFD : DForm_9<54, (ops FPRC:$rS, symbolLo:$disp, GPRC:$rA),
275 "stfd $rS, $disp($rA)">;
278 // DS-Form instructions. Load/Store instructions available in PPC-64
281 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
282 "lwa $rT, $DS($rA)">, isPPC64;
283 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
284 "ld $rT, $DS($rA)">, isPPC64;
287 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
288 "std $rT, $DS($rA)">, isPPC64;
289 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
290 "stdu $rT, $DS($rA)">, isPPC64;
293 // X-Form instructions. Most instructions that perform an operation on a
294 // register and another register are of this type.
297 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
298 "lbzx $dst, $base, $index">;
299 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
300 "lhax $dst, $base, $index">;
301 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
302 "lhzx $dst, $base, $index">;
303 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
304 "lwax $dst, $base, $index">, isPPC64;
305 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
306 "lwzx $dst, $base, $index">;
307 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
308 "ldx $dst, $base, $index">, isPPC64;
310 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
311 "nand $rA, $rS, $rB",
312 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
313 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
315 [(set GPRC:$rT, (and GPRC:$rA, GPRC:$rB))]>;
316 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
317 "and. $rA, $rS, $rB",
319 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
320 "andc $rA, $rS, $rB",
321 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
322 def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
324 [(set GPRC:$rT, (or GPRC:$rA, GPRC:$rB))]>;
325 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
327 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
328 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
331 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
333 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
334 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
336 [(set GPRC:$rT, (not (xor GPRC:$rA, GPRC:$rB)))]>;
337 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
339 [(set GPRC:$rT, (xor GPRC:$rA, GPRC:$rB))]>;
340 def SLD : XForm_6<31, 27, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
343 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
346 def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
349 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
352 def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
353 "srad $rA, $rS, $rB",
355 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
356 "sraw $rA, $rS, $rB",
359 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
360 "stbx $rS, $rA, $rB">;
361 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
362 "sthx $rS, $rA, $rB">;
363 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
364 "stwx $rS, $rA, $rB">;
365 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
366 "stwux $rS, $rA, $rB">;
367 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
368 "stdx $rS, $rA, $rB">, isPPC64;
369 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
370 "stdux $rS, $rA, $rB">, isPPC64;
372 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
373 "srawi $rA, $rS, $SH">;
374 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
376 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
377 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
379 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
380 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
382 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
383 def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
386 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
387 "cmp $crD, $long, $rA, $rB">;
388 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
389 "cmpl $crD, $long, $rA, $rB">;
390 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
391 "cmpw $crD, $rA, $rB">;
392 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
393 "cmpd $crD, $rA, $rB">, isPPC64;
394 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
395 "cmplw $crD, $rA, $rB">;
396 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
397 "cmpld $crD, $rA, $rB">, isPPC64;
398 def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
399 "fcmpo $crD, $fA, $fB">;
400 def FCMPU : XForm_17<63, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
401 "fcmpu $crD, $fA, $fB">;
403 def LFSX : XForm_25<31, 535, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
404 "lfsx $dst, $base, $index">;
405 def LFDX : XForm_25<31, 599, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
406 "lfdx $dst, $base, $index">;
408 def FCFID : XForm_26<63, 846, (ops FPRC:$frD, FPRC:$frB),
409 "fcfid $frD, $frB">, isPPC64;
410 def FCTIDZ : XForm_26<63, 815, (ops FPRC:$frD, FPRC:$frB),
411 "fctidz $frD, $frB">, isPPC64;
412 def FCTIWZ : XForm_26<63, 15, (ops FPRC:$frD, FPRC:$frB),
413 "fctiwz $frD, $frB">;
414 def FABS : XForm_26<63, 264, (ops FPRC:$frD, FPRC:$frB),
416 def FMR : XForm_26<63, 72, (ops FPRC:$frD, FPRC:$frB),
418 def FNABS : XForm_26<63, 136, (ops FPRC:$frD, FPRC:$frB),
420 def FNEG : XForm_26<63, 40, (ops FPRC:$frD, FPRC:$frB),
422 def FRSP : XForm_26<63, 12, (ops FPRC:$frD, FPRC:$frB),
424 def FSQRT : XForm_26<63, 22, (ops FPRC:$frD, FPRC:$frB),
426 def FSQRTS : XForm_26<59, 22, (ops FPRC:$frD, FPRC:$frB),
427 "fsqrts $frD, $frB">;
430 def STFSX : XForm_28<31, 663, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
431 "stfsx $frS, $rA, $rB">;
432 def STFDX : XForm_28<31, 727, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
433 "stfdx $frS, $rA, $rB">;
436 // XL-Form instructions. condition register logical ops.
438 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
441 // XFX-Form instructions. Instructions that deal with SPRs
443 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
444 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
445 // which means the SPR value needs to be multiplied by a factor of 32.
446 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT">;
447 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT">;
448 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">;
449 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
451 def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
453 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">;
454 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;
456 // XS-Form instructions. Just 'sradi'
458 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
459 "sradi $rA, $rS, $SH">, isPPC64;
461 // XO-Form instructions. Arithmetic instructions that can set overflow bit
463 def ADD : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
465 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
466 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
467 "addc $rT, $rA, $rB",
469 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
470 "adde $rT, $rA, $rB",
472 def DIVD : XOForm_1<31, 489, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
473 "divd $rT, $rA, $rB",
475 def DIVDU : XOForm_1<31, 457, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
476 "divdu $rT, $rA, $rB",
478 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
479 "divw $rT, $rA, $rB",
480 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
481 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
482 "divwu $rT, $rA, $rB",
483 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
484 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
485 "mulhw $rT, $rA, $rB",
486 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
487 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
488 "mulhwu $rT, $rA, $rB",
489 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
490 def MULLD : XOForm_1<31, 233, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
491 "mulld $rT, $rA, $rB",
493 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
494 "mullw $rT, $rA, $rB",
495 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
496 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
497 "subf $rT, $rA, $rB",
498 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
499 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
500 "subfc $rT, $rA, $rB",
502 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
503 "subfe $rT, $rA, $rB",
505 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
508 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
511 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
513 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
514 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
518 // A-Form instructions. Most of the instructions executed in the FPU are of
521 def FMADD : AForm_1<63, 29,
522 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
523 "fmadd $FRT, $FRA, $FRC, $FRB">;
524 def FMADDS : AForm_1<59, 29,
525 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
526 "fmadds $FRT, $FRA, $FRC, $FRB">;
527 def FMSUB : AForm_1<63, 28,
528 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
529 "fmsub $FRT, $FRA, $FRC, $FRB">;
530 def FMSUBS : AForm_1<59, 28,
531 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
532 "fmsubs $FRT, $FRA, $FRC, $FRB">;
533 def FNMADD : AForm_1<63, 31,
534 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
535 "fnmadd $FRT, $FRA, $FRC, $FRB">;
536 def FNMADDS : AForm_1<59, 31,
537 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
538 "fnmadds $FRT, $FRA, $FRC, $FRB">;
539 def FNMSUB : AForm_1<63, 30,
540 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
541 "fnmsub $FRT, $FRA, $FRC, $FRB">;
542 def FNMSUBS : AForm_1<59, 30,
543 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
544 "fnmsubs $FRT, $FRA, $FRC, $FRB">;
545 def FSEL : AForm_1<63, 23,
546 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
547 "fsel $FRT, $FRA, $FRC, $FRB">;
548 def FADD : AForm_2<63, 21,
549 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
550 "fadd $FRT, $FRA, $FRB">;
551 def FADDS : AForm_2<59, 21,
552 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
553 "fadds $FRT, $FRA, $FRB">;
554 def FDIV : AForm_2<63, 18,
555 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
556 "fdiv $FRT, $FRA, $FRB">;
557 def FDIVS : AForm_2<59, 18,
558 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
559 "fdivs $FRT, $FRA, $FRB">;
560 def FMUL : AForm_3<63, 25,
561 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
562 "fmul $FRT, $FRA, $FRB">;
563 def FMULS : AForm_3<59, 25,
564 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
565 "fmuls $FRT, $FRA, $FRB">;
566 def FSUB : AForm_2<63, 20,
567 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
568 "fsub $FRT, $FRA, $FRB">;
569 def FSUBS : AForm_2<59, 20,
570 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
571 "fsubs $FRT, $FRA, $FRB">;
573 // M-Form instructions. rotate and mask instructions.
575 let isTwoAddress = 1 in {
576 def RLWIMI : MForm_2<20,
577 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
578 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
580 def RLWINM : MForm_2<21,
581 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
582 "rlwinm $rA, $rS, $SH, $MB, $ME">;
583 def RLWINMo : MForm_2<21,
584 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
585 "rlwinm. $rA, $rS, $SH, $MB, $ME">, isDOT;
586 def RLWNM : MForm_2<23,
587 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
588 "rlwnm $rA, $rS, $rB, $MB, $ME">;
590 // MD-Form instructions. 64 bit rotate instructions.
592 def RLDICL : MDForm_1<30, 0,
593 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
594 "rldicl $rA, $rS, $SH, $MB">, isPPC64;
595 def RLDICR : MDForm_1<30, 1,
596 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
597 "rldicr $rA, $rS, $SH, $ME">, isPPC64;
599 def PowerPCInstrInfo : InstrInfo {
602 let TSFlagsFields = [ "VMX", "PPC64" ];
603 let TSFlagsShifts = [ 0, 1 ];
605 let isLittleEndianEncoding = 1;