1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific DAG Nodes.
21 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
22 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
23 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
25 def PPCfsel : SDNode<"PPCISD::FSEL",
26 // Type constraint for fsel.
27 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
28 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
30 //===----------------------------------------------------------------------===//
31 // PowerPC specific transformation functions and pattern fragments.
34 def SHL32 : SDNodeXForm<imm, [{
35 // Transformation function: 31 - imm
36 return getI32Imm(31 - N->getValue());
39 def SHL64 : SDNodeXForm<imm, [{
40 // Transformation function: 63 - imm
41 return getI32Imm(63 - N->getValue());
44 def SRL32 : SDNodeXForm<imm, [{
45 // Transformation function: 32 - imm
46 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
49 def SRL64 : SDNodeXForm<imm, [{
50 // Transformation function: 64 - imm
51 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
54 def LO16 : SDNodeXForm<imm, [{
55 // Transformation function: get the low 16 bits.
56 return getI32Imm((unsigned short)N->getValue());
59 def HI16 : SDNodeXForm<imm, [{
60 // Transformation function: shift the immediate value down into the low bits.
61 return getI32Imm((unsigned)N->getValue() >> 16);
64 def HA16 : SDNodeXForm<imm, [{
65 // Transformation function: shift the immediate value down into the low bits.
66 signed int Val = N->getValue();
67 return getI32Imm((Val - (signed short)Val) >> 16);
71 def immSExt16 : PatLeaf<(imm), [{
72 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
73 // field. Used by instructions like 'addi'.
74 return (int)N->getValue() == (short)N->getValue();
76 def immZExt16 : PatLeaf<(imm), [{
77 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
78 // field. Used by instructions like 'ori'.
79 return (unsigned)N->getValue() == (unsigned short)N->getValue();
82 def imm16Shifted : PatLeaf<(imm), [{
83 // imm16Shifted predicate - True if only bits in the top 16-bits of the
84 // immediate are set. Used by instructions like 'addis'.
85 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
89 // Example of a legalize expander: Only for PPC64.
90 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
91 [(set f64:$tmp , (FCTIDZ f64:$src)),
92 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
93 (store f64:$tmp, i32:$tmpFI),
94 (set i64:$dst, (load i32:$tmpFI))],
98 //===----------------------------------------------------------------------===//
99 // PowerPC Flag Definitions.
101 class isPPC64 { bit PPC64 = 1; }
102 class isVMX { bit VMX = 1; }
104 list<Register> Defs = [CR0];
110 //===----------------------------------------------------------------------===//
111 // PowerPC Operand Definitions.
113 def u5imm : Operand<i32> {
114 let PrintMethod = "printU5ImmOperand";
116 def u6imm : Operand<i32> {
117 let PrintMethod = "printU6ImmOperand";
119 def s16imm : Operand<i32> {
120 let PrintMethod = "printS16ImmOperand";
122 def u16imm : Operand<i32> {
123 let PrintMethod = "printU16ImmOperand";
125 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
126 let PrintMethod = "printS16X4ImmOperand";
128 def target : Operand<i32> {
129 let PrintMethod = "printBranchOperand";
131 def piclabel: Operand<i32> {
132 let PrintMethod = "printPICLabel";
134 def symbolHi: Operand<i32> {
135 let PrintMethod = "printSymbolHi";
137 def symbolLo: Operand<i32> {
138 let PrintMethod = "printSymbolLo";
140 def crbitm: Operand<i8> {
141 let PrintMethod = "printcrbitm";
146 //===----------------------------------------------------------------------===//
147 // PowerPC Instruction Definitions.
149 // Pseudo-instructions:
150 def PHI : Pseudo<(ops variable_ops), "; PHI", []>;
153 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN", []>;
154 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP", []>;
156 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC", []>;
157 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8", []>;
158 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4", []>;
160 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
161 // scheduler into a branch sequence.
162 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
163 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
164 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
165 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
166 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
167 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
168 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
172 let isTerminator = 1 in {
174 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB>;
175 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB>;
179 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>;
181 let isBranch = 1, isTerminator = 1 in {
182 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
183 target:$true, target:$false),
184 "; COND_BRANCH", []>;
185 def B : IForm<18, 0, 0, (ops target:$func), "b $func", BrB>;
186 //def BA : IForm<18, 1, 0, (ops target:$func), "ba $func", BrB>;
187 def BL : IForm<18, 0, 1, (ops target:$func), "bl $func", BrB>;
188 //def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func", BrB>;
190 // FIXME: 4*CR# needs to be added to the BI field!
191 // This will only work for CR0 as it stands now
192 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
193 "blt $crS, $block", BrB>;
194 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
195 "ble $crS, $block", BrB>;
196 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
197 "beq $crS, $block", BrB>;
198 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
199 "bge $crS, $block", BrB>;
200 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
201 "bgt $crS, $block", BrB>;
202 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
203 "bne $crS, $block", BrB>;
207 // All calls clobber the non-callee saved registers...
208 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
209 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
211 CR0,CR1,CR5,CR6,CR7] in {
212 // Convenient aliases for call instructions
213 def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops),
215 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1,
216 (ops variable_ops), "bctrl", BrB>;
219 // D-Form instructions. Most instructions that perform an operation on a
220 // register and an immediate are of this type.
223 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
224 "lbz $rD, $disp($rA)", LdStGeneral>;
225 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
226 "lha $rD, $disp($rA)", LdStLHA>;
227 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
228 "lhz $rD, $disp($rA)", LdStGeneral>;
229 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
230 "lmw $rD, $disp($rA)", LdStLMW>;
231 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
232 "lwz $rD, $disp($rA)", LdStGeneral>;
233 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
234 "lwzu $rD, $disp($rA)", LdStGeneral>;
236 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
237 "addi $rD, $rA, $imm", IntGeneral,
238 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
239 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
240 "addic $rD, $rA, $imm", IntGeneral,
242 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
243 "addic. $rD, $rA, $imm", IntGeneral,
245 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
246 "addis $rD, $rA, $imm", IntGeneral,
247 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
248 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
249 "la $rD, $sym($rA)", IntGeneral,
251 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
252 "mulli $rD, $rA, $imm", IntMulLI,
253 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
254 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
255 "subfic $rD, $rA, $imm", IntGeneral,
256 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
257 def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
258 "li $rD, $imm", IntGeneral,
259 [(set GPRC:$rD, immSExt16:$imm)]>;
260 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
261 "lis $rD, $imm", IntGeneral,
262 [(set GPRC:$rD, imm16Shifted:$imm)]>;
264 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
265 "stmw $rS, $disp($rA)", LdStLMW>;
266 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
267 "stb $rS, $disp($rA)", LdStGeneral>;
268 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
269 "sth $rS, $disp($rA)", LdStGeneral>;
270 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
271 "stw $rS, $disp($rA)", LdStGeneral>;
272 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
273 "stwu $rS, $disp($rA)", LdStGeneral>;
275 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
276 "andi. $dst, $src1, $src2", IntGeneral,
278 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
279 "andis. $dst, $src1, $src2", IntGeneral,
281 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
282 "ori $dst, $src1, $src2", IntGeneral,
283 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
284 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
285 "oris $dst, $src1, $src2", IntGeneral,
286 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
287 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
288 "xori $dst, $src1, $src2", IntGeneral,
289 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
290 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
291 "xoris $dst, $src1, $src2", IntGeneral,
292 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
293 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral>;
294 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
295 "cmpi $crD, $L, $rA, $imm", IntCompare>;
296 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
297 "cmpwi $crD, $rA, $imm", IntCompare>;
298 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
299 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
300 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
301 "cmpli $dst, $size, $src1, $src2", IntCompare>;
302 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
303 "cmplwi $dst, $src1, $src2", IntCompare>;
304 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
305 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
307 def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
308 "lfs $rD, $disp($rA)", LdStLFDU>;
309 def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
310 "lfd $rD, $disp($rA)", LdStLFD>;
313 def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
314 "stfs $rS, $disp($rA)", LdStUX>;
315 def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
316 "stfd $rS, $disp($rA)", LdStUX>;
319 // DS-Form instructions. Load/Store instructions available in PPC-64
322 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
323 "lwa $rT, $DS($rA)", LdStLWA>, isPPC64;
324 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
325 "ld $rT, $DS($rA)", LdStLD>, isPPC64;
328 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
329 "std $rT, $DS($rA)", LdStSTD>, isPPC64;
330 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
331 "stdu $rT, $DS($rA)", LdStSTD>, isPPC64;
334 // X-Form instructions. Most instructions that perform an operation on a
335 // register and another register are of this type.
338 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
339 "lbzx $dst, $base, $index", LdStGeneral>;
340 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
341 "lhax $dst, $base, $index", LdStLHA>;
342 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
343 "lhzx $dst, $base, $index", LdStGeneral>;
344 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
345 "lwax $dst, $base, $index", LdStLHA>, isPPC64;
346 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
347 "lwzx $dst, $base, $index", LdStGeneral>;
348 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
349 "ldx $dst, $base, $index", LdStLD>, isPPC64;
351 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
352 "nand $rA, $rS, $rB", IntGeneral,
353 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
354 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
355 "and $rA, $rS, $rB", IntGeneral,
356 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
357 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
358 "and. $rA, $rS, $rB", IntGeneral,
360 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
361 "andc $rA, $rS, $rB", IntGeneral,
362 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
363 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
364 "or $rA, $rS, $rB", IntGeneral,
365 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
366 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
367 "or $rA, $rS, $rB", IntGeneral,
368 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
369 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
370 "or $rA, $rS, $rB", IntGeneral,
372 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
373 "or $rA, $rS, $rB", IntGeneral,
375 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
376 "nor $rA, $rS, $rB", IntGeneral,
377 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
378 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
379 "or. $rA, $rS, $rB", IntGeneral,
381 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
382 "orc $rA, $rS, $rB", IntGeneral,
383 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
384 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
385 "eqv $rA, $rS, $rB", IntGeneral,
386 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
387 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
388 "xor $rA, $rS, $rB", IntGeneral,
389 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
390 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
391 "sld $rA, $rS, $rB", IntRotateD,
392 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
393 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
394 "slw $rA, $rS, $rB", IntGeneral,
395 [(set GPRC:$rA, (shl GPRC:$rS, GPRC:$rB))]>;
396 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
397 "srd $rA, $rS, $rB", IntRotateD,
398 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
399 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
400 "srw $rA, $rS, $rB", IntGeneral,
401 [(set GPRC:$rA, (srl GPRC:$rS, GPRC:$rB))]>;
402 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
403 "srad $rA, $rS, $rB", IntRotateD,
404 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
405 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
406 "sraw $rA, $rS, $rB", IntShift,
407 [(set GPRC:$rA, (sra GPRC:$rS, GPRC:$rB))]>;
409 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
410 "stbx $rS, $rA, $rB", LdStGeneral>;
411 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
412 "sthx $rS, $rA, $rB", LdStGeneral>;
413 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
414 "stwx $rS, $rA, $rB", LdStGeneral>;
415 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
416 "stwux $rS, $rA, $rB", LdStGeneral>;
417 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
418 "stdx $rS, $rA, $rB", LdStSTD>, isPPC64;
419 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
420 "stdux $rS, $rA, $rB", LdStSTD>, isPPC64;
422 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
423 "srawi $rA, $rS, $SH", IntShift,
424 [(set GPRC:$rA, (sra GPRC:$rS, imm:$SH))]>;
425 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
426 "cntlzw $rA, $rS", IntGeneral,
427 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
428 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
429 "extsb $rA, $rS", IntGeneral,
430 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
431 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
432 "extsh $rA, $rS", IntGeneral,
433 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
434 def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
435 "extsw $rA, $rS", IntRotateD,
437 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
438 "cmp $crD, $long, $rA, $rB", IntCompare>;
439 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
440 "cmpl $crD, $long, $rA, $rB", IntCompare>;
441 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
442 "cmpw $crD, $rA, $rB", IntCompare>;
443 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
444 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
445 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
446 "cmplw $crD, $rA, $rB", IntCompare>;
447 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
448 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
449 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
450 // "fcmpo $crD, $fA, $fB", FPCompare>;
451 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
452 "fcmpu $crD, $fA, $fB", FPCompare>;
453 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
454 "fcmpu $crD, $fA, $fB", FPCompare>;
457 def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
458 "lfsx $dst, $base, $index", LdStLFDU>;
459 def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
460 "lfdx $dst, $base, $index", LdStLFDU>;
462 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
463 "fcfid $frD, $frB", FPGeneral,
464 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
465 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
466 "fctidz $frD, $frB", FPGeneral,
467 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
468 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
469 "fctiwz $frD, $frB", FPGeneral,
470 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
471 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
472 "frsp $frD, $frB", FPGeneral,
473 [(set F4RC:$frD, (fround F8RC:$frB))]>;
474 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
475 "fsqrt $frD, $frB", FPSqrt,
476 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
477 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
478 "fsqrts $frD, $frB", FPSqrt,
479 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
481 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
482 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
483 "fmr $frD, $frB", FPGeneral,
484 []>; // (set F4RC:$frD, F4RC:$frB)
485 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
486 "fmr $frD, $frB", FPGeneral,
487 []>; // (set F8RC:$frD, F8RC:$frB)
488 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
489 "fmr $frD, $frB", FPGeneral,
490 [(set F8RC:$frD, (fextend F4RC:$frB))]>;
492 // These are artificially split into two different forms, for 4/8 byte FP.
493 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
494 "fabs $frD, $frB", FPGeneral,
495 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
496 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
497 "fabs $frD, $frB", FPGeneral,
498 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
499 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
500 "fnabs $frD, $frB", FPGeneral,
501 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
502 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
503 "fnabs $frD, $frB", FPGeneral,
504 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
505 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
506 "fneg $frD, $frB", FPGeneral,
507 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
508 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
509 "fneg $frD, $frB", FPGeneral,
510 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
514 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
515 "stfsx $frS, $rA, $rB", LdStUX>;
516 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
517 "stfdx $frS, $rA, $rB", LdStUX>;
520 // XL-Form instructions. condition register logical ops.
522 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
523 "mcrf $BF, $BFA", BrMCR>;
525 // XFX-Form instructions. Instructions that deal with SPRs
527 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
528 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
529 // which means the SPR value needs to be multiplied by a factor of 32.
530 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
531 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT", SprMFSPR>;
532 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>;
533 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
534 "mtcrf $FXM, $rS", BrMCRX>;
535 def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
536 "mfcr $rT, $FXM", SprMFCR>;
537 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
538 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
540 // XS-Form instructions. Just 'sradi'
542 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
543 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
545 // XO-Form instructions. Arithmetic instructions that can set overflow bit
547 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
548 "add $rT, $rA, $rB", IntGeneral,
549 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
550 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
551 "add $rT, $rA, $rB", IntGeneral,
552 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
553 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
554 "addc $rT, $rA, $rB", IntGeneral,
556 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
557 "adde $rT, $rA, $rB", IntGeneral,
559 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
560 "divd $rT, $rA, $rB", IntDivD,
561 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
562 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
563 "divdu $rT, $rA, $rB", IntDivD,
564 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
565 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
566 "divw $rT, $rA, $rB", IntDivW,
567 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
568 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
569 "divwu $rT, $rA, $rB", IntDivW,
570 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
571 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
572 "mulhd $rT, $rA, $rB", IntMulHW,
573 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
574 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
575 "mulhdu $rT, $rA, $rB", IntMulHWU,
576 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
577 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
578 "mulhw $rT, $rA, $rB", IntMulHW,
579 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
580 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
581 "mulhwu $rT, $rA, $rB", IntMulHWU,
582 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
583 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
584 "mulld $rT, $rA, $rB", IntMulHD,
585 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
586 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
587 "mullw $rT, $rA, $rB", IntMulHW,
588 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
589 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
590 "subf $rT, $rA, $rB", IntGeneral,
591 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
592 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
593 "subfc $rT, $rA, $rB", IntGeneral,
595 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
596 "subfe $rT, $rA, $rB", IntGeneral,
598 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
599 "addme $rT, $rA", IntGeneral,
601 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
602 "addze $rT, $rA", IntGeneral,
604 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
605 "neg $rT, $rA", IntGeneral,
606 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
607 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
608 "subfze $rT, $rA", IntGeneral,
611 // A-Form instructions. Most of the instructions executed in the FPU are of
614 def FMADD : AForm_1<63, 29,
615 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
616 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
617 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
619 def FMADDS : AForm_1<59, 29,
620 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
621 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
622 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
624 def FMSUB : AForm_1<63, 28,
625 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
626 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
627 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
629 def FMSUBS : AForm_1<59, 28,
630 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
631 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
632 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
634 def FNMADD : AForm_1<63, 31,
635 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
636 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
637 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
639 def FNMADDS : AForm_1<59, 31,
640 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
641 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
642 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
644 def FNMSUB : AForm_1<63, 30,
645 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
646 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
647 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
649 def FNMSUBS : AForm_1<59, 30,
650 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
651 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
652 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
654 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
655 // having 4 of these, force the comparison to always be an 8-byte double (code
656 // should use an FMRSD if the input comparison value really wants to be a float)
657 // and 4/8 byte forms for the result and operand type..
658 def FSELD : AForm_1<63, 23,
659 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
660 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
661 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
662 def FSELS : AForm_1<63, 23,
663 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
664 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
665 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
666 def FADD : AForm_2<63, 21,
667 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
668 "fadd $FRT, $FRA, $FRB", FPGeneral,
669 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
670 def FADDS : AForm_2<59, 21,
671 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
672 "fadds $FRT, $FRA, $FRB", FPGeneral,
673 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
674 def FDIV : AForm_2<63, 18,
675 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
676 "fdiv $FRT, $FRA, $FRB", FPDivD,
677 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
678 def FDIVS : AForm_2<59, 18,
679 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
680 "fdivs $FRT, $FRA, $FRB", FPDivS,
681 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
682 def FMUL : AForm_3<63, 25,
683 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
684 "fmul $FRT, $FRA, $FRB", FPFused,
685 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
686 def FMULS : AForm_3<59, 25,
687 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
688 "fmuls $FRT, $FRA, $FRB", FPGeneral,
689 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
690 def FSUB : AForm_2<63, 20,
691 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
692 "fsub $FRT, $FRA, $FRB", FPGeneral,
693 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
694 def FSUBS : AForm_2<59, 20,
695 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
696 "fsubs $FRT, $FRA, $FRB", FPGeneral,
697 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
699 // M-Form instructions. rotate and mask instructions.
701 let isTwoAddress = 1, isCommutable = 1 in {
702 // RLWIMI can be commuted if the rotate amount is zero.
703 def RLWIMI : MForm_2<20,
704 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
705 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
707 def RLDIMI : MDForm_1<30, 3,
708 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
709 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
712 def RLWINM : MForm_2<21,
713 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
714 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
716 def RLWINMo : MForm_2<21,
717 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
718 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
720 def RLWNM : MForm_2<23,
721 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
722 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
725 // MD-Form instructions. 64 bit rotate instructions.
727 def RLDICL : MDForm_1<30, 0,
728 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
729 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
731 def RLDICR : MDForm_1<30, 1,
732 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
733 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
736 //===----------------------------------------------------------------------===//
737 // PowerPC Instruction Patterns
740 // Arbitrary immediate support. Implement in terms of LIS/ORI.
741 def : Pat<(i32 imm:$imm),
742 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
744 // Implement the 'not' operation with the NOR instruction.
745 def NOT : Pat<(not GPRC:$in),
746 (NOR GPRC:$in, GPRC:$in)>;
748 // ADD an arbitrary immediate.
749 def : Pat<(add GPRC:$in, imm:$imm),
750 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
751 // OR an arbitrary immediate.
752 def : Pat<(or GPRC:$in, imm:$imm),
753 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
754 // XOR an arbitrary immediate.
755 def : Pat<(xor GPRC:$in, imm:$imm),
756 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
757 def : Pat<(or (shl GPRC:$rS, GPRC:$rB),
758 (srl GPRC:$rS, (sub 32, GPRC:$rB))),
759 (RLWNM GPRC:$rS, GPRC:$rB, 0, 31)>;
761 def : Pat<(zext GPRC:$in),
762 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
763 def : Pat<(anyext GPRC:$in),
764 (OR4To8 GPRC:$in, GPRC:$in)>;
765 def : Pat<(trunc G8RC:$in),
766 (OR8To4 G8RC:$in, G8RC:$in)>;
769 def : Pat<(shl GPRC:$in, imm:$imm),
770 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
771 def : Pat<(shl G8RC:$in, imm:$imm),
772 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
774 def : Pat<(srl GPRC:$in, imm:$imm),
775 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
776 def : Pat<(srl G8RC:$in, imm:$imm),
777 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
779 // Same as above, but using a temporary. FIXME: implement temporaries :)
781 def : Pattern<(xor GPRC:$in, imm:$imm),
782 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
783 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
786 //===----------------------------------------------------------------------===//
787 // PowerPCInstrInfo Definition
789 def PowerPCInstrInfo : InstrInfo {
792 let TSFlagsFields = [ "VMX", "PPC64" ];
793 let TSFlagsShifts = [ 0, 1 ];
795 let isLittleEndianEncoding = 1;