1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
26 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
27 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
29 def SDT_PPCvperm : SDTypeProfile<1, 3, [
30 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
33 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
34 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
37 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
38 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
41 def SDT_PPClbrx : SDTypeProfile<1, 3, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
44 def SDT_PPCstbrx : SDTypeProfile<0, 4, [
45 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
48 //===----------------------------------------------------------------------===//
49 // PowerPC specific DAG Nodes.
52 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
53 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
54 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
55 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
56 [SDNPHasChain, SDNPMayStore]>;
58 // This sequence is used for long double->int conversions. It changes the
59 // bits in the FPSCR which is not modelled.
60 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
62 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
63 [SDNPInFlag, SDNPOutFlag]>;
64 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
65 [SDNPInFlag, SDNPOutFlag]>;
66 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
67 [SDNPInFlag, SDNPOutFlag]>;
68 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
69 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
73 def PPCfsel : SDNode<"PPCISD::FSEL",
74 // Type constraint for fsel.
75 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
76 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
78 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
79 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
80 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
81 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
83 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
85 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
86 // amounts. These nodes are generated by the multi-precision shift code.
87 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
88 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
89 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
91 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
92 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
93 [SDNPHasChain, SDNPMayStore]>;
95 // These are target-independent nodes, but have target-specific formats.
96 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
97 [SDNPHasChain, SDNPOutFlag]>;
98 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
99 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
101 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
102 def PPCcall_Macho : SDNode<"PPCISD::CALL_Macho", SDT_PPCCall,
103 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
104 def PPCcall_ELF : SDNode<"PPCISD::CALL_ELF", SDT_PPCCall,
105 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
106 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
107 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
108 def PPCbctrl_Macho : SDNode<"PPCISD::BCTRL_Macho", SDTRet,
109 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
111 def PPCbctrl_ELF : SDNode<"PPCISD::BCTRL_ELF", SDTRet,
112 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
114 def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet,
115 [SDNPHasChain, SDNPOptInFlag]>;
117 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
118 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
120 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
121 [SDNPHasChain, SDNPOptInFlag]>;
123 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>;
124 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
125 [SDNPHasChain, SDNPMayStore]>;
127 // Instructions to support dynamic alloca.
128 def SDTDynOp : SDTypeProfile<1, 2, []>;
129 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
131 //===----------------------------------------------------------------------===//
132 // PowerPC specific transformation functions and pattern fragments.
135 def SHL32 : SDNodeXForm<imm, [{
136 // Transformation function: 31 - imm
137 return getI32Imm(31 - N->getValue());
140 def SRL32 : SDNodeXForm<imm, [{
141 // Transformation function: 32 - imm
142 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
145 def LO16 : SDNodeXForm<imm, [{
146 // Transformation function: get the low 16 bits.
147 return getI32Imm((unsigned short)N->getValue());
150 def HI16 : SDNodeXForm<imm, [{
151 // Transformation function: shift the immediate value down into the low bits.
152 return getI32Imm((unsigned)N->getValue() >> 16);
155 def HA16 : SDNodeXForm<imm, [{
156 // Transformation function: shift the immediate value down into the low bits.
157 signed int Val = N->getValue();
158 return getI32Imm((Val - (signed short)Val) >> 16);
160 def MB : SDNodeXForm<imm, [{
161 // Transformation function: get the start bit of a mask
163 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
164 return getI32Imm(mb);
167 def ME : SDNodeXForm<imm, [{
168 // Transformation function: get the end bit of a mask
170 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
171 return getI32Imm(me);
173 def maskimm32 : PatLeaf<(imm), [{
174 // maskImm predicate - True if immediate is a run of ones.
176 if (N->getValueType(0) == MVT::i32)
177 return isRunOfOnes((unsigned)N->getValue(), mb, me);
182 def immSExt16 : PatLeaf<(imm), [{
183 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
184 // field. Used by instructions like 'addi'.
185 if (N->getValueType(0) == MVT::i32)
186 return (int32_t)N->getValue() == (short)N->getValue();
188 return (int64_t)N->getValue() == (short)N->getValue();
190 def immZExt16 : PatLeaf<(imm), [{
191 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
192 // field. Used by instructions like 'ori'.
193 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
196 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
197 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
198 // identical in 32-bit mode, but in 64-bit mode, they return true if the
199 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
201 def imm16ShiftedZExt : PatLeaf<(imm), [{
202 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
203 // immediate are set. Used by instructions like 'xoris'.
204 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
207 def imm16ShiftedSExt : PatLeaf<(imm), [{
208 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
209 // immediate are set. Used by instructions like 'addis'. Identical to
210 // imm16ShiftedZExt in 32-bit mode.
211 if (N->getValue() & 0xFFFF) return false;
212 if (N->getValueType(0) == MVT::i32)
214 // For 64-bit, make sure it is sext right.
215 return N->getValue() == (uint64_t)(int)N->getValue();
219 //===----------------------------------------------------------------------===//
220 // PowerPC Flag Definitions.
222 class isPPC64 { bit PPC64 = 1; }
224 list<Register> Defs = [CR0];
228 class RegConstraint<string C> {
229 string Constraints = C;
231 class NoEncode<string E> {
232 string DisableEncoding = E;
236 //===----------------------------------------------------------------------===//
237 // PowerPC Operand Definitions.
239 def s5imm : Operand<i32> {
240 let PrintMethod = "printS5ImmOperand";
242 def u5imm : Operand<i32> {
243 let PrintMethod = "printU5ImmOperand";
245 def u6imm : Operand<i32> {
246 let PrintMethod = "printU6ImmOperand";
248 def s16imm : Operand<i32> {
249 let PrintMethod = "printS16ImmOperand";
251 def u16imm : Operand<i32> {
252 let PrintMethod = "printU16ImmOperand";
254 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
255 let PrintMethod = "printS16X4ImmOperand";
257 def target : Operand<OtherVT> {
258 let PrintMethod = "printBranchOperand";
260 def calltarget : Operand<iPTR> {
261 let PrintMethod = "printCallOperand";
263 def aaddr : Operand<iPTR> {
264 let PrintMethod = "printAbsAddrOperand";
266 def piclabel: Operand<iPTR> {
267 let PrintMethod = "printPICLabel";
269 def symbolHi: Operand<i32> {
270 let PrintMethod = "printSymbolHi";
272 def symbolLo: Operand<i32> {
273 let PrintMethod = "printSymbolLo";
275 def crbitm: Operand<i8> {
276 let PrintMethod = "printcrbitm";
279 def memri : Operand<iPTR> {
280 let PrintMethod = "printMemRegImm";
281 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
283 def memrr : Operand<iPTR> {
284 let PrintMethod = "printMemRegReg";
285 let MIOperandInfo = (ops ptr_rc, ptr_rc);
287 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
288 let PrintMethod = "printMemRegImmShifted";
289 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
292 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
293 // that doesn't matter.
294 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
295 (ops (i32 20), CR0)> {
296 let PrintMethod = "printPredicateOperand";
299 // Define PowerPC specific addressing mode.
300 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
301 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
302 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
303 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
305 /// This is just the offset part of iaddr, used for preinc.
306 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
308 //===----------------------------------------------------------------------===//
309 // PowerPC Instruction Predicate Definitions.
310 def FPContractions : Predicate<"!NoExcessFPPrecision">;
311 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
312 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
315 //===----------------------------------------------------------------------===//
316 // PowerPC Instruction Definitions.
318 // Pseudo-instructions:
320 let hasCtrlDep = 1 in {
321 let Defs = [R1], Uses = [R1] in {
322 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
323 "${:comment} ADJCALLSTACKDOWN",
324 [(callseq_start imm:$amt)]>;
325 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
326 "${:comment} ADJCALLSTACKUP",
327 [(callseq_end imm:$amt1, imm:$amt2)]>;
330 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
331 "UPDATE_VRSAVE $rD, $rS", []>;
334 let Defs = [R1], Uses = [R1] in
335 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi),
336 "${:comment} DYNALLOC $result, $negsize, $fpsi",
338 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
340 let isImplicitDef = 1 in {
341 def IMPLICIT_DEF_GPRC: Pseudo<(outs GPRC:$rD), (ins),
342 "${:comment}IMPLICIT_DEF_GPRC $rD",
343 [(set GPRC:$rD, (undef))]>;
344 def IMPLICIT_DEF_F8 : Pseudo<(outs F8RC:$rD), (ins),
345 "${:comment} IMPLICIT_DEF_F8 $rD",
346 [(set F8RC:$rD, (undef))]>;
347 def IMPLICIT_DEF_F4 : Pseudo<(outs F4RC:$rD), (ins),
348 "${:comment} IMPLICIT_DEF_F4 $rD",
349 [(set F4RC:$rD, (undef))]>;
352 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
353 // scheduler into a branch sequence.
354 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
355 PPC970_Single = 1 in {
356 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
357 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
359 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
360 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
362 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
363 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
365 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
366 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
368 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
369 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
373 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
375 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
376 "b${p:cc}lr ${p:reg}", BrB,
378 let isBranch = 1, isIndirectBranch = 1 in
379 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
385 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
388 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
389 let isBarrier = 1 in {
390 def B : IForm<18, 0, 0, (outs), (ins target:$dst),
395 // BCC represents an arbitrary conditional branch on a predicate.
396 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
397 // a two-value operand where a dag node expects two operands. :(
398 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst),
399 "b${cond:cc} ${cond:reg}, $dst"
400 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
404 let isCall = 1, PPC970_Unit = 7,
405 // All calls clobber the non-callee saved registers...
406 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
407 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
408 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
410 CR0,CR1,CR5,CR6,CR7] in {
411 // Convenient aliases for call instructions
412 def BL_Macho : IForm<18, 0, 1,
413 (outs), (ins calltarget:$func, variable_ops),
414 "bl $func", BrB, []>; // See Pat patterns below.
415 def BLA_Macho : IForm<18, 1, 1,
416 (outs), (ins aaddr:$func, variable_ops),
417 "bla $func", BrB, [(PPCcall_Macho (i32 imm:$func))]>;
418 def BCTRL_Macho : XLForm_2_ext<19, 528, 20, 0, 1,
419 (outs), (ins variable_ops),
421 [(PPCbctrl_Macho)]>, Requires<[In32BitMode]>;
425 let isCall = 1, PPC970_Unit = 7,
426 // All calls clobber the non-callee saved registers...
427 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
428 F0,F1,F2,F3,F4,F5,F6,F7,F8,
429 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
431 CR0,CR1,CR5,CR6,CR7] in {
432 // Convenient aliases for call instructions
433 def BL_ELF : IForm<18, 0, 1,
434 (outs), (ins calltarget:$func, variable_ops),
435 "bl $func", BrB, []>; // See Pat patterns below.
436 def BLA_ELF : IForm<18, 1, 1,
437 (outs), (ins aaddr:$func, variable_ops),
439 [(PPCcall_ELF (i32 imm:$func))]>;
440 def BCTRL_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
441 (outs), (ins variable_ops),
443 [(PPCbctrl_ELF)]>, Requires<[In32BitMode]>;
446 // DCB* instructions.
447 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
448 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
449 PPC970_DGroup_Single;
450 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
451 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
452 PPC970_DGroup_Single;
453 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
454 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
455 PPC970_DGroup_Single;
456 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
457 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
458 PPC970_DGroup_Single;
459 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
460 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
461 PPC970_DGroup_Single;
462 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
463 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
464 PPC970_DGroup_Single;
465 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
466 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
467 PPC970_DGroup_Single;
468 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
469 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
470 PPC970_DGroup_Single;
472 //===----------------------------------------------------------------------===//
473 // PPC32 Load Instructions.
476 // Unindexed (r+i) Loads.
477 let isLoad = 1, PPC970_Unit = 2 in {
478 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
479 "lbz $rD, $src", LdStGeneral,
480 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
481 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
482 "lha $rD, $src", LdStLHA,
483 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
484 PPC970_DGroup_Cracked;
485 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
486 "lhz $rD, $src", LdStGeneral,
487 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
488 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
489 "lwz $rD, $src", LdStGeneral,
490 [(set GPRC:$rD, (load iaddr:$src))]>;
492 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
493 "lfs $rD, $src", LdStLFDU,
494 [(set F4RC:$rD, (load iaddr:$src))]>;
495 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
496 "lfd $rD, $src", LdStLFD,
497 [(set F8RC:$rD, (load iaddr:$src))]>;
500 // Unindexed (r+i) Loads with Update (preinc).
501 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
502 "lbzu $rD, $addr", LdStGeneral,
503 []>, RegConstraint<"$addr.reg = $ea_result">,
504 NoEncode<"$ea_result">;
506 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
507 "lhau $rD, $addr", LdStGeneral,
508 []>, RegConstraint<"$addr.reg = $ea_result">,
509 NoEncode<"$ea_result">;
511 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
512 "lhzu $rD, $addr", LdStGeneral,
513 []>, RegConstraint<"$addr.reg = $ea_result">,
514 NoEncode<"$ea_result">;
516 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
517 "lwzu $rD, $addr", LdStGeneral,
518 []>, RegConstraint<"$addr.reg = $ea_result">,
519 NoEncode<"$ea_result">;
521 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
522 "lfs $rD, $addr", LdStLFDU,
523 []>, RegConstraint<"$addr.reg = $ea_result">,
524 NoEncode<"$ea_result">;
526 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
527 "lfd $rD, $addr", LdStLFD,
528 []>, RegConstraint<"$addr.reg = $ea_result">,
529 NoEncode<"$ea_result">;
532 // Indexed (r+r) Loads.
534 let isLoad = 1, PPC970_Unit = 2 in {
535 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
536 "lbzx $rD, $src", LdStGeneral,
537 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
538 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
539 "lhax $rD, $src", LdStLHA,
540 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
541 PPC970_DGroup_Cracked;
542 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
543 "lhzx $rD, $src", LdStGeneral,
544 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
545 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
546 "lwzx $rD, $src", LdStGeneral,
547 [(set GPRC:$rD, (load xaddr:$src))]>;
550 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
551 "lhbrx $rD, $src", LdStGeneral,
552 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
553 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
554 "lwbrx $rD, $src", LdStGeneral,
555 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
557 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
558 "lfsx $frD, $src", LdStLFDU,
559 [(set F4RC:$frD, (load xaddr:$src))]>;
560 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
561 "lfdx $frD, $src", LdStLFDU,
562 [(set F8RC:$frD, (load xaddr:$src))]>;
565 //===----------------------------------------------------------------------===//
566 // PPC32 Store Instructions.
569 // Unindexed (r+i) Stores.
570 let PPC970_Unit = 2 in {
571 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
572 "stb $rS, $src", LdStGeneral,
573 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
574 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
575 "sth $rS, $src", LdStGeneral,
576 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
577 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
578 "stw $rS, $src", LdStGeneral,
579 [(store GPRC:$rS, iaddr:$src)]>;
580 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
581 "stfs $rS, $dst", LdStUX,
582 [(store F4RC:$rS, iaddr:$dst)]>;
583 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
584 "stfd $rS, $dst", LdStUX,
585 [(store F8RC:$rS, iaddr:$dst)]>;
588 // Unindexed (r+i) Stores with Update (preinc).
589 let PPC970_Unit = 2 in {
590 def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
591 symbolLo:$ptroff, ptr_rc:$ptrreg),
592 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
593 [(set ptr_rc:$ea_res,
594 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
595 iaddroff:$ptroff))]>,
596 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
597 def STHU : DForm_1<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
598 symbolLo:$ptroff, ptr_rc:$ptrreg),
599 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
600 [(set ptr_rc:$ea_res,
601 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
602 iaddroff:$ptroff))]>,
603 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
604 def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
605 symbolLo:$ptroff, ptr_rc:$ptrreg),
606 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
607 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
608 iaddroff:$ptroff))]>,
609 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
610 def STFSU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
611 symbolLo:$ptroff, ptr_rc:$ptrreg),
612 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
613 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
614 iaddroff:$ptroff))]>,
615 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
616 def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
617 symbolLo:$ptroff, ptr_rc:$ptrreg),
618 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
619 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
620 iaddroff:$ptroff))]>,
621 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
625 // Indexed (r+r) Stores.
627 let PPC970_Unit = 2 in {
628 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
629 "stbx $rS, $dst", LdStGeneral,
630 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
631 PPC970_DGroup_Cracked;
632 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
633 "sthx $rS, $dst", LdStGeneral,
634 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
635 PPC970_DGroup_Cracked;
636 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
637 "stwx $rS, $dst", LdStGeneral,
638 [(store GPRC:$rS, xaddr:$dst)]>,
639 PPC970_DGroup_Cracked;
641 let mayStore = 1 in {
642 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
643 "stwux $rS, $rA, $rB", LdStGeneral,
646 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
647 "sthbrx $rS, $dst", LdStGeneral,
648 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
649 PPC970_DGroup_Cracked;
650 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
651 "stwbrx $rS, $dst", LdStGeneral,
652 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>,
653 PPC970_DGroup_Cracked;
655 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
656 "stfiwx $frS, $dst", LdStUX,
657 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
659 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
660 "stfsx $frS, $dst", LdStUX,
661 [(store F4RC:$frS, xaddr:$dst)]>;
662 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
663 "stfdx $frS, $dst", LdStUX,
664 [(store F8RC:$frS, xaddr:$dst)]>;
668 //===----------------------------------------------------------------------===//
669 // PPC32 Arithmetic Instructions.
672 let PPC970_Unit = 1 in { // FXU Operations.
673 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
674 "addi $rD, $rA, $imm", IntGeneral,
675 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
676 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
677 "addic $rD, $rA, $imm", IntGeneral,
678 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
679 PPC970_DGroup_Cracked;
680 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
681 "addic. $rD, $rA, $imm", IntGeneral,
683 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
684 "addis $rD, $rA, $imm", IntGeneral,
685 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
686 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
687 "la $rD, $sym($rA)", IntGeneral,
688 [(set GPRC:$rD, (add GPRC:$rA,
689 (PPClo tglobaladdr:$sym, 0)))]>;
690 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
691 "mulli $rD, $rA, $imm", IntMulLI,
692 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
693 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
694 "subfic $rD, $rA, $imm", IntGeneral,
695 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
697 let isReMaterializable = 1, neverHasSideEffects = 1 in {
698 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
699 "li $rD, $imm", IntGeneral,
700 [(set GPRC:$rD, immSExt16:$imm)]>;
701 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
702 "lis $rD, $imm", IntGeneral,
703 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
707 let PPC970_Unit = 1 in { // FXU Operations.
708 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
709 "andi. $dst, $src1, $src2", IntGeneral,
710 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
712 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
713 "andis. $dst, $src1, $src2", IntGeneral,
714 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
716 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
717 "ori $dst, $src1, $src2", IntGeneral,
718 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
719 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
720 "oris $dst, $src1, $src2", IntGeneral,
721 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
722 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
723 "xori $dst, $src1, $src2", IntGeneral,
724 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
725 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
726 "xoris $dst, $src1, $src2", IntGeneral,
727 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
728 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral,
730 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
731 "cmpwi $crD, $rA, $imm", IntCompare>;
732 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
733 "cmplwi $dst, $src1, $src2", IntCompare>;
737 let PPC970_Unit = 1 in { // FXU Operations.
738 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
739 "nand $rA, $rS, $rB", IntGeneral,
740 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
741 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
742 "and $rA, $rS, $rB", IntGeneral,
743 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
744 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
745 "andc $rA, $rS, $rB", IntGeneral,
746 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
747 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
748 "or $rA, $rS, $rB", IntGeneral,
749 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
750 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
751 "nor $rA, $rS, $rB", IntGeneral,
752 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
753 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
754 "orc $rA, $rS, $rB", IntGeneral,
755 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
756 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
757 "eqv $rA, $rS, $rB", IntGeneral,
758 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
759 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
760 "xor $rA, $rS, $rB", IntGeneral,
761 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
762 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
763 "slw $rA, $rS, $rB", IntGeneral,
764 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
765 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
766 "srw $rA, $rS, $rB", IntGeneral,
767 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
768 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
769 "sraw $rA, $rS, $rB", IntShift,
770 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
773 let PPC970_Unit = 1 in { // FXU Operations.
774 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
775 "srawi $rA, $rS, $SH", IntShift,
776 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
777 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
778 "cntlzw $rA, $rS", IntGeneral,
779 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
780 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
781 "extsb $rA, $rS", IntGeneral,
782 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
783 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
784 "extsh $rA, $rS", IntGeneral,
785 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
787 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
788 "cmpw $crD, $rA, $rB", IntCompare>;
789 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
790 "cmplw $crD, $rA, $rB", IntCompare>;
792 let PPC970_Unit = 3 in { // FPU Operations.
793 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
794 // "fcmpo $crD, $fA, $fB", FPCompare>;
795 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
796 "fcmpu $crD, $fA, $fB", FPCompare>;
797 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
798 "fcmpu $crD, $fA, $fB", FPCompare>;
800 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
801 "fctiwz $frD, $frB", FPGeneral,
802 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
803 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
804 "frsp $frD, $frB", FPGeneral,
805 [(set F4RC:$frD, (fround F8RC:$frB))]>;
806 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
807 "fsqrt $frD, $frB", FPSqrt,
808 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
809 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
810 "fsqrts $frD, $frB", FPSqrt,
811 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
814 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
816 /// Note that these are defined as pseudo-ops on the PPC970 because they are
817 /// often coalesced away and we don't want the dispatch group builder to think
818 /// that they will fill slots (which could cause the load of a LSU reject to
819 /// sneak into a d-group with a store).
820 def FMRS : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
821 "fmr $frD, $frB", FPGeneral,
822 []>, // (set F4RC:$frD, F4RC:$frB)
824 def FMRD : XForm_26<63, 72, (outs F8RC:$frD), (ins F8RC:$frB),
825 "fmr $frD, $frB", FPGeneral,
826 []>, // (set F8RC:$frD, F8RC:$frB)
828 def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB),
829 "fmr $frD, $frB", FPGeneral,
830 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
833 let PPC970_Unit = 3 in { // FPU Operations.
834 // These are artificially split into two different forms, for 4/8 byte FP.
835 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
836 "fabs $frD, $frB", FPGeneral,
837 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
838 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
839 "fabs $frD, $frB", FPGeneral,
840 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
841 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
842 "fnabs $frD, $frB", FPGeneral,
843 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
844 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
845 "fnabs $frD, $frB", FPGeneral,
846 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
847 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
848 "fneg $frD, $frB", FPGeneral,
849 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
850 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
851 "fneg $frD, $frB", FPGeneral,
852 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
856 // XL-Form instructions. condition register logical ops.
858 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
859 "mcrf $BF, $BFA", BrMCR>,
860 PPC970_DGroup_First, PPC970_Unit_CRU;
862 def CREQV : XLForm_1<19, 289, (outs CRRC:$CRD), (ins CRRC:$CRA, CRRC:$CRB),
863 "creqv $CRD, $CRA, $CRB", BrCR,
866 def SETCR : XLForm_1_ext<19, 289, (outs CRRC:$dst), (ins),
867 "creqv $dst, $dst, $dst", BrCR,
870 // XFX-Form instructions. Instructions that deal with SPRs.
872 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
873 "mfctr $rT", SprMFSPR>,
874 PPC970_DGroup_First, PPC970_Unit_FXU;
875 let Pattern = [(PPCmtctr GPRC:$rS)] in {
876 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
877 "mtctr $rS", SprMTSPR>,
878 PPC970_DGroup_First, PPC970_Unit_FXU;
881 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
882 "mtlr $rS", SprMTSPR>,
883 PPC970_DGroup_First, PPC970_Unit_FXU;
884 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
885 "mflr $rT", SprMFSPR>,
886 PPC970_DGroup_First, PPC970_Unit_FXU;
888 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
889 // a GPR on the PPC970. As such, copies in and out have the same performance
890 // characteristics as an OR instruction.
891 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
892 "mtspr 256, $rS", IntGeneral>,
893 PPC970_DGroup_Single, PPC970_Unit_FXU;
894 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
895 "mfspr $rT, 256", IntGeneral>,
896 PPC970_DGroup_First, PPC970_Unit_FXU;
898 def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
899 "mtcrf $FXM, $rS", BrMCRX>,
900 PPC970_MicroCode, PPC970_Unit_CRU;
901 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), "mfcr $rT", SprMFCR>,
902 PPC970_MicroCode, PPC970_Unit_CRU;
903 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
904 "mfcr $rT, $FXM", SprMFCR>,
905 PPC970_DGroup_First, PPC970_Unit_CRU;
907 // Instructions to manipulate FPSCR. Only long double handling uses these.
908 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
910 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
912 [(set F8RC:$rT, (PPCmffs))]>,
913 PPC970_DGroup_Single, PPC970_Unit_FPU;
914 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
915 "mtfsb0 $FM", IntMTFSB0,
916 [(PPCmtfsb0 (i32 imm:$FM))]>,
917 PPC970_DGroup_Single, PPC970_Unit_FPU;
918 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
919 "mtfsb1 $FM", IntMTFSB0,
920 [(PPCmtfsb1 (i32 imm:$FM))]>,
921 PPC970_DGroup_Single, PPC970_Unit_FPU;
922 def FADDrtz: AForm_2<63, 21,
923 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
924 "fadd $FRT, $FRA, $FRB", FPGeneral,
925 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
926 PPC970_DGroup_Single, PPC970_Unit_FPU;
927 // MTFSF does not actually produce an FP result. We pretend it copies
928 // input reg B to the output. If we didn't do this it would look like the
929 // instruction had no outputs (because we aren't modelling the FPSCR) and
930 // it would be deleted.
931 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
932 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
933 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
934 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
935 F8RC:$rT, F8RC:$FRB))]>,
936 PPC970_DGroup_Single, PPC970_Unit_FPU;
938 let PPC970_Unit = 1 in { // FXU Operations.
940 // XO-Form instructions. Arithmetic instructions that can set overflow bit
942 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
943 "add $rT, $rA, $rB", IntGeneral,
944 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
945 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
946 "addc $rT, $rA, $rB", IntGeneral,
947 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
948 PPC970_DGroup_Cracked;
949 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
950 "adde $rT, $rA, $rB", IntGeneral,
951 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
952 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
953 "divw $rT, $rA, $rB", IntDivW,
954 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
955 PPC970_DGroup_First, PPC970_DGroup_Cracked;
956 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
957 "divwu $rT, $rA, $rB", IntDivW,
958 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
959 PPC970_DGroup_First, PPC970_DGroup_Cracked;
960 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
961 "mulhw $rT, $rA, $rB", IntMulHW,
962 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
963 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
964 "mulhwu $rT, $rA, $rB", IntMulHWU,
965 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
966 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
967 "mullw $rT, $rA, $rB", IntMulHW,
968 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
969 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
970 "subf $rT, $rA, $rB", IntGeneral,
971 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
972 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
973 "subfc $rT, $rA, $rB", IntGeneral,
974 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
975 PPC970_DGroup_Cracked;
976 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
977 "subfe $rT, $rA, $rB", IntGeneral,
978 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
979 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
980 "addme $rT, $rA", IntGeneral,
981 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
982 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
983 "addze $rT, $rA", IntGeneral,
984 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
985 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
986 "neg $rT, $rA", IntGeneral,
987 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
988 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
989 "subfme $rT, $rA", IntGeneral,
990 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
991 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
992 "subfze $rT, $rA", IntGeneral,
993 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
996 // A-Form instructions. Most of the instructions executed in the FPU are of
999 let PPC970_Unit = 3 in { // FPU Operations.
1000 def FMADD : AForm_1<63, 29,
1001 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1002 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1003 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1005 Requires<[FPContractions]>;
1006 def FMADDS : AForm_1<59, 29,
1007 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1008 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1009 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1011 Requires<[FPContractions]>;
1012 def FMSUB : AForm_1<63, 28,
1013 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1014 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1015 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1017 Requires<[FPContractions]>;
1018 def FMSUBS : AForm_1<59, 28,
1019 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1020 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1021 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1023 Requires<[FPContractions]>;
1024 def FNMADD : AForm_1<63, 31,
1025 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1026 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1027 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1029 Requires<[FPContractions]>;
1030 def FNMADDS : AForm_1<59, 31,
1031 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1032 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1033 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1035 Requires<[FPContractions]>;
1036 def FNMSUB : AForm_1<63, 30,
1037 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1038 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1039 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1041 Requires<[FPContractions]>;
1042 def FNMSUBS : AForm_1<59, 30,
1043 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1044 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1045 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1047 Requires<[FPContractions]>;
1048 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1049 // having 4 of these, force the comparison to always be an 8-byte double (code
1050 // should use an FMRSD if the input comparison value really wants to be a float)
1051 // and 4/8 byte forms for the result and operand type..
1052 def FSELD : AForm_1<63, 23,
1053 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1054 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1055 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1056 def FSELS : AForm_1<63, 23,
1057 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1058 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1059 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1060 def FADD : AForm_2<63, 21,
1061 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1062 "fadd $FRT, $FRA, $FRB", FPGeneral,
1063 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1064 def FADDS : AForm_2<59, 21,
1065 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1066 "fadds $FRT, $FRA, $FRB", FPGeneral,
1067 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1068 def FDIV : AForm_2<63, 18,
1069 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1070 "fdiv $FRT, $FRA, $FRB", FPDivD,
1071 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1072 def FDIVS : AForm_2<59, 18,
1073 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1074 "fdivs $FRT, $FRA, $FRB", FPDivS,
1075 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1076 def FMUL : AForm_3<63, 25,
1077 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1078 "fmul $FRT, $FRA, $FRB", FPFused,
1079 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1080 def FMULS : AForm_3<59, 25,
1081 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1082 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1083 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1084 def FSUB : AForm_2<63, 20,
1085 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1086 "fsub $FRT, $FRA, $FRB", FPGeneral,
1087 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1088 def FSUBS : AForm_2<59, 20,
1089 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1090 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1091 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1094 let PPC970_Unit = 1 in { // FXU Operations.
1095 // M-Form instructions. rotate and mask instructions.
1097 let isCommutable = 1 in {
1098 // RLWIMI can be commuted if the rotate amount is zero.
1099 def RLWIMI : MForm_2<20,
1100 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1101 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1102 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1105 def RLWINM : MForm_2<21,
1106 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1107 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1109 def RLWINMo : MForm_2<21,
1110 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1111 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1112 []>, isDOT, PPC970_DGroup_Cracked;
1113 def RLWNM : MForm_2<23,
1114 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1115 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1120 //===----------------------------------------------------------------------===//
1121 // DWARF Pseudo Instructions
1124 def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
1125 "${:comment} .loc $file, $line, $col",
1126 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
1129 //===----------------------------------------------------------------------===//
1130 // PowerPC Instruction Patterns
1133 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1134 def : Pat<(i32 imm:$imm),
1135 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1137 // Implement the 'not' operation with the NOR instruction.
1138 def NOT : Pat<(not GPRC:$in),
1139 (NOR GPRC:$in, GPRC:$in)>;
1141 // ADD an arbitrary immediate.
1142 def : Pat<(add GPRC:$in, imm:$imm),
1143 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1144 // OR an arbitrary immediate.
1145 def : Pat<(or GPRC:$in, imm:$imm),
1146 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1147 // XOR an arbitrary immediate.
1148 def : Pat<(xor GPRC:$in, imm:$imm),
1149 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1151 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1152 (SUBFIC GPRC:$in, imm:$imm)>;
1155 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1156 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1157 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1158 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1161 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1162 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1163 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1164 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1167 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1168 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1171 def : Pat<(PPCcall_Macho (i32 tglobaladdr:$dst)),
1172 (BL_Macho tglobaladdr:$dst)>;
1173 def : Pat<(PPCcall_Macho (i32 texternalsym:$dst)),
1174 (BL_Macho texternalsym:$dst)>;
1175 def : Pat<(PPCcall_ELF (i32 tglobaladdr:$dst)),
1176 (BL_ELF tglobaladdr:$dst)>;
1177 def : Pat<(PPCcall_ELF (i32 texternalsym:$dst)),
1178 (BL_ELF texternalsym:$dst)>;
1180 // Hi and Lo for Darwin Global Addresses.
1181 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1182 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1183 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1184 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1185 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1186 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1187 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1188 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1189 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1190 (ADDIS GPRC:$in, tconstpool:$g)>;
1191 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1192 (ADDIS GPRC:$in, tjumptable:$g)>;
1194 // Fused negative multiply subtract, alternate pattern
1195 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1196 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1197 Requires<[FPContractions]>;
1198 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1199 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1200 Requires<[FPContractions]>;
1202 // Standard shifts. These are represented separately from the real shifts above
1203 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1205 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1206 (SRAW GPRC:$rS, GPRC:$rB)>;
1207 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1208 (SRW GPRC:$rS, GPRC:$rB)>;
1209 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1210 (SLW GPRC:$rS, GPRC:$rB)>;
1212 def : Pat<(zextloadi1 iaddr:$src),
1214 def : Pat<(zextloadi1 xaddr:$src),
1216 def : Pat<(extloadi1 iaddr:$src),
1218 def : Pat<(extloadi1 xaddr:$src),
1220 def : Pat<(extloadi8 iaddr:$src),
1222 def : Pat<(extloadi8 xaddr:$src),
1224 def : Pat<(extloadi16 iaddr:$src),
1226 def : Pat<(extloadi16 xaddr:$src),
1228 def : Pat<(extloadf32 iaddr:$src),
1229 (FMRSD (LFS iaddr:$src))>;
1230 def : Pat<(extloadf32 xaddr:$src),
1231 (FMRSD (LFSX xaddr:$src))>;
1233 include "PPCInstrAltivec.td"
1234 include "PPCInstr64Bit.td"