1 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PowerPCInstrFormats.td"
17 class isPPC64 { bit PPC64 = 1; }
18 class isVMX { bit VMX = 1; }
20 list<Register> Defs = [CR0];
24 let isTerminator = 1 in {
26 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">;
27 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">;
30 def u5imm : Operand<i8> {
31 let PrintMethod = "printU5ImmOperand";
33 def u6imm : Operand<i8> {
34 let PrintMethod = "printU6ImmOperand";
36 def s16imm : Operand<i16> {
37 let PrintMethod = "printS16ImmOperand";
39 def u16imm : Operand<i16> {
40 let PrintMethod = "printU16ImmOperand";
42 def target : Operand<i32> {
43 let PrintMethod = "printBranchOperand";
45 def piclabel: Operand<i32> {
46 let PrintMethod = "printPICLabel";
48 def symbolHi: Operand<i32> {
49 let PrintMethod = "printSymbolHi";
51 def symbolLo: Operand<i32> {
52 let PrintMethod = "printSymbolLo";
54 def crbit: Operand<i8> {
55 let PrintMethod = "printcrbit";
57 def crbitm: Operand<i8> {
58 let PrintMethod = "printcrbitm";
61 // Pseudo-instructions:
62 def PHI : Pseudo<(ops variable_ops), "; PHI">;
64 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm), "; ADJCALLSTACKDOWN">;
65 def ADJCALLSTACKUP : Pseudo<(ops u16imm), "; ADJCALLSTACKUP">;
67 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
68 def IMPLICIT_DEF_FP : Pseudo<(ops FPRC:$rD), "; %rD = IMPLICIT_DEF_FP">;
71 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
73 let isBranch = 1, isTerminator = 1 in {
74 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm, target:$true, target:$false),
76 def B : IForm<18, 0, 0, (ops target:$func), "b $func">;
77 //def BA : IForm<18, 1, 0, (ops target:$func), "ba $func">;
78 def BL : IForm<18, 0, 1, (ops target:$func), "bl $func">;
79 //def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func">;
81 // FIXME: 4*CR# needs to be added to the BI field!
82 // This will only work for CR0 as it stands now
83 def BLT : BForm_ext<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
85 def BLE : BForm_ext<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
87 def BEQ : BForm_ext<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
89 def BGE : BForm_ext<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
91 def BGT : BForm_ext<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
93 def BNE : BForm_ext<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
98 // All calls clobber the non-callee saved registers...
99 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
100 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
102 CR0,CR1,CR5,CR6,CR7] in {
103 // Convenient aliases for call instructions
104 def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops), "bl $func">;
105 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1,
106 (ops variable_ops), "bctrl">;
109 // D-Form instructions. Most instructions that perform an operation on a
110 // register and an immediate are of this type.
113 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
114 "lbz $rD, $disp($rA)">;
115 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
116 "lha $rD, $disp($rA)">;
117 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
118 "lhz $rD, $disp($rA)">;
119 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
120 "lmw $rD, $disp($rA)">;
121 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
122 "lwz $rD, $disp($rA)">;
123 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
124 "lwzu $rD, $disp($rA)">;
126 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
127 "addi $rD, $rA, $imm">;
128 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
129 "addic $rD, $rA, $imm">;
130 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
131 "addic. $rD, $rA, $imm">;
132 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
133 "addis $rD, $rA, $imm">;
134 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
135 "la $rD, $sym($rA)">;
136 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
137 "mulli $rD, $rA, $imm">;
138 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
139 "subfic $rD, $rA, $imm">;
140 def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
142 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
145 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
146 "stmw $rS, $disp($rA)">;
147 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
148 "stb $rS, $disp($rA)">;
149 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
150 "sth $rS, $disp($rA)">;
151 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
152 "stw $rS, $disp($rA)">;
153 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
154 "stwu $rS, $disp($rA)">;
156 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
157 "andi. $dst, $src1, $src2">, isDOT;
158 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
159 "andis. $dst, $src1, $src2">, isDOT;
160 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
161 "ori $dst, $src1, $src2">;
162 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
163 "oris $dst, $src1, $src2">;
164 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
165 "xori $dst, $src1, $src2">;
166 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
167 "xoris $dst, $src1, $src2">;
168 def NOP : DForm_4_zero<24, (ops), "nop">;
169 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
170 "cmpi $crD, $L, $rA, $imm">;
171 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
172 "cmpwi $crD, $rA, $imm">;
173 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
174 "cmpdi $crD, $rA, $imm">, isPPC64;
175 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
176 "cmpli $dst, $size, $src1, $src2">;
177 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
178 "cmplwi $dst, $src1, $src2">;
179 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
180 "cmpldi $dst, $src1, $src2">, isPPC64;
182 def LFS : DForm_8<48, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
183 "lfs $rD, $disp($rA)">;
184 def LFD : DForm_8<50, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
185 "lfd $rD, $disp($rA)">;
188 def STFS : DForm_9<52, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
189 "stfs $rS, $disp($rA)">;
190 def STFD : DForm_9<54, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
191 "stfd $rS, $disp($rA)">;
194 // DS-Form instructions. Load/Store instructions available in PPC-64
197 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
198 "lwa $rT, $DS($rA)">, isPPC64;
199 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
200 "ld $rT, $DS($rA)">, isPPC64;
203 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
204 "std $rT, $DS($rA)">, isPPC64;
205 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
206 "stdu $rT, $DS($rA)">, isPPC64;
209 // X-Form instructions. Most instructions that perform an operation on a
210 // register and another register are of this type.
213 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
214 "lbzx $dst, $base, $index">;
215 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
216 "lhax $dst, $base, $index">;
217 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
218 "lhzx $dst, $base, $index">;
219 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
220 "lwax $dst, $base, $index">, isPPC64;
221 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
222 "lwzx $dst, $base, $index">;
223 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
224 "ldx $dst, $base, $index">, isPPC64;
226 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
227 "and $rA, $rS, $rB">;
228 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
229 "and. $rA, $rS, $rB">, isDOT;
230 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
231 "andc $rA, $rS, $rB">;
232 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
233 "eqv $rA, $rS, $rB">;
234 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
235 "nand $rA, $rS, $rB">;
236 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
237 "nor $rA, $rS, $rB">;
238 def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
240 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
241 "or. $rA, $rS, $rB">, isDOT;
242 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
243 "orc $rA, $rS, $rB">;
244 def SLD : XForm_6<31, 27, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
245 "sld $rA, $rS, $rB">, isPPC64;
246 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
247 "slw $rA, $rS, $rB">;
248 def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
249 "srd $rA, $rS, $rB">, isPPC64;
250 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
251 "srw $rA, $rS, $rB">;
252 def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
253 "srad $rA, $rS, $rB">, isPPC64;
254 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
255 "sraw $rA, $rS, $rB">;
256 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
257 "xor $rA, $rS, $rB">;
259 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
260 "stbx $rS, $rA, $rB">;
261 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
262 "sthx $rS, $rA, $rB">;
263 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
264 "stwx $rS, $rA, $rB">;
265 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
266 "stwux $rS, $rA, $rB">;
267 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
268 "stdx $rS, $rA, $rB">, isPPC64;
269 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
270 "stdux $rS, $rA, $rB">, isPPC64;
272 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
273 "srawi $rA, $rS, $SH">;
274 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
276 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
278 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
280 def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
281 "extsw $rA, $rS">, isPPC64;
282 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
283 "cmp $crD, $long, $rA, $rB">;
284 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
285 "cmpl $crD, $long, $rA, $rB">;
286 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
287 "cmpw $crD, $rA, $rB">;
288 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
289 "cmpd $crD, $rA, $rB">, isPPC64;
290 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
291 "cmplw $crD, $rA, $rB">;
292 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
293 "cmpld $crD, $rA, $rB">, isPPC64;
294 def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
295 "fcmpo $crD, $fA, $fB">;
296 def FCMPU : XForm_17<63, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
297 "fcmpu $crD, $fA, $fB">;
299 def LFSX : XForm_25<31, 535, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
300 "lfsx $dst, $base, $index">;
301 def LFDX : XForm_25<31, 599, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
302 "lfdx $dst, $base, $index">;
304 def FCFID : XForm_26<63, 846, (ops FPRC:$frD, FPRC:$frB),
305 "fcfid $frD, $frB">, isPPC64;
306 def FCTIDZ : XForm_26<63, 815, (ops FPRC:$frD, FPRC:$frB),
307 "fctidz $frD, $frB">, isPPC64;
308 def FCTIWZ : XForm_26<63, 15, (ops FPRC:$frD, FPRC:$frB),
309 "fctiwz $frD, $frB">;
310 def FABS : XForm_26<63, 264, (ops FPRC:$frD, FPRC:$frB),
312 def FMR : XForm_26<63, 72, (ops FPRC:$frD, FPRC:$frB),
314 def FNABS : XForm_26<63, 136, (ops FPRC:$frD, FPRC:$frB),
316 def FNEG : XForm_26<63, 40, (ops FPRC:$frD, FPRC:$frB),
318 def FRSP : XForm_26<63, 12, (ops FPRC:$frD, FPRC:$frB),
320 def FSQRT : XForm_26<63, 22, (ops FPRC:$frD, FPRC:$frB),
322 def FSQRTS : XForm_26<59, 22, (ops FPRC:$frD, FPRC:$frB),
323 "fsqrts $frD, $frB">;
326 def STFSX : XForm_28<31, 663, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
327 "stfsx $frS, $rA, $rB">;
328 def STFDX : XForm_28<31, 727, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
329 "stfdx $frS, $rA, $rB">;
332 // XL-Form instructions. condition register logical ops.
334 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
337 // XFX-Form instructions. Instructions that deal with SPRs
339 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
340 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
341 // which means the SPR value needs to be multiplied by a factor of 32.
342 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT">;
343 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT">;
344 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">;
345 def MTCRF : XFXForm_5<31, 144, (ops CRRC:$FXM, GPRC:$rS),
347 def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
349 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">;
350 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;
352 // XS-Form instructions. Just 'sradi'
354 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
355 "sradi $rA, $rS, $SH">, isPPC64;
357 // XO-Form instructions. Arithmetic instructions that can set overflow bit
359 def ADD : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
360 "add $rT, $rA, $rB">;
361 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
362 "addc $rT, $rA, $rB">;
363 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
364 "adde $rT, $rA, $rB">;
365 def DIVD : XOForm_1<31, 489, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
366 "divd $rT, $rA, $rB">, isPPC64;
367 def DIVDU : XOForm_1<31, 457, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
368 "divdu $rT, $rA, $rB">, isPPC64;
369 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
370 "divw $rT, $rA, $rB">;
371 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
372 "divwu $rT, $rA, $rB">;
373 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
374 "mulhw $rT, $rA, $rB">;
375 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
376 "mulhwu $rT, $rA, $rB">;
377 def MULLD : XOForm_1<31, 233, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
378 "mulld $rT, $rA, $rB">, isPPC64;
379 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
380 "mullw $rT, $rA, $rB">;
381 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
382 "subf $rT, $rA, $rB">;
383 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
384 "subfc $rT, $rA, $rB">;
385 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
386 "subfe $rT, $rA, $rB">;
387 def SUB : XOForm_1r<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
388 "sub $rT, $rA, $rB">;
389 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
391 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
393 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
395 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
398 // A-Form instructions. Most of the instructions executed in the FPU are of
401 def FMADD : AForm_1<63, 29,
402 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
403 "fmadd $FRT, $FRA, $FRC, $FRB">;
404 def FMADDS : AForm_1<59, 29,
405 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
406 "fmadds $FRT, $FRA, $FRC, $FRB">;
407 def FMSUB : AForm_1<63, 28,
408 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
409 "fmsub $FRT, $FRA, $FRC, $FRB">;
410 def FMSUBS : AForm_1<59, 28,
411 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
412 "fmsubs $FRT, $FRA, $FRC, $FRB">;
413 def FNMADD : AForm_1<63, 31,
414 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
415 "fnmadd $FRT, $FRA, $FRC, $FRB">;
416 def FNMADDS : AForm_1<59, 31,
417 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
418 "fnmadds $FRT, $FRA, $FRC, $FRB">;
419 def FNMSUB : AForm_1<63, 30,
420 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
421 "fnmsub $FRT, $FRA, $FRC, $FRB">;
422 def FNMSUBS : AForm_1<59, 30,
423 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
424 "fnmsubs $FRT, $FRA, $FRC, $FRB">;
425 def FSEL : AForm_1<63, 23,
426 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
427 "fsel $FRT, $FRA, $FRC, $FRB">;
428 def FADD : AForm_2<63, 21,
429 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
430 "fadd $FRT, $FRA, $FRB">;
431 def FADDS : AForm_2<59, 21,
432 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
433 "fadds $FRT, $FRA, $FRB">;
434 def FDIV : AForm_2<63, 18,
435 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
436 "fdiv $FRT, $FRA, $FRB">;
437 def FDIVS : AForm_2<59, 18,
438 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
439 "fdivs $FRT, $FRA, $FRB">;
440 def FMUL : AForm_3<63, 25,
441 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
442 "fmul $FRT, $FRA, $FRB">;
443 def FMULS : AForm_3<59, 25,
444 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
445 "fmuls $FRT, $FRA, $FRB">;
446 def FSUB : AForm_2<63, 20,
447 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
448 "fsub $FRT, $FRA, $FRB">;
449 def FSUBS : AForm_2<59, 20,
450 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
451 "fsubs $FRT, $FRA, $FRB">;
453 // M-Form instructions. rotate and mask instructions.
455 let isTwoAddress = 1 in {
456 def RLWIMI : MForm_2<20,
457 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
458 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
460 def RLWINM : MForm_2<21,
461 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
462 "rlwinm $rA, $rS, $SH, $MB, $ME">;
463 def RLWINMo : MForm_2<21,
464 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
465 "rlwinm. $rA, $rS, $SH, $MB, $ME">, isDOT;
466 def RLWNM : MForm_2<23,
467 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
468 "rlwnm $rA, $rS, $rB, $MB, $ME">;
470 // MD-Form instructions. 64 bit rotate instructions.
472 def RLDICL : MDForm_1<30, 0,
473 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
474 "rldicl $rA, $rS, $SH, $MB">, isPPC64;
475 def RLDICR : MDForm_1<30, 1,
476 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
477 "rldicr $rA, $rS, $SH, $ME">, isPPC64;
479 def PowerPCInstrInfo : InstrInfo {
482 let TSFlagsFields = [ "VMX", "PPC64" ];
483 let TSFlagsShifts = [ 0, 1 ];
485 let isLittleEndianEncoding = 1;