2 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
4 // The LLVM Compiler Infrastructure
6 // This file was developed by the LLVM research group and is distributed under
7 // the University of Illinois Open Source License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the subset of the 32-bit PowerPC instruction set, as used
12 // by the PowerPC instruction selector.
14 //===----------------------------------------------------------------------===//
16 include "PowerPCInstrFormats.td"
18 let isTerminator = 1 in {
20 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, 0, 0, (ops), "blr">;
21 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, 0, 0, (ops), "bctr">;
24 def u5imm : Operand<i8> {
25 let PrintMethod = "printU5ImmOperand";
27 def u6imm : Operand<i8> {
28 let PrintMethod = "printU6ImmOperand";
30 def s16imm : Operand<i16> {
31 let PrintMethod = "printS16ImmOperand";
33 def u16imm : Operand<i16> {
34 let PrintMethod = "printU16ImmOperand";
36 def target : Operand<i32> {
37 let PrintMethod = "printBranchOperand";
39 def piclabel: Operand<i32> {
40 let PrintMethod = "printPICLabel";
42 def symbolHi: Operand<i32> {
43 let PrintMethod = "printSymbolHi";
45 def symbolLo: Operand<i32> {
46 let PrintMethod = "printSymbolLo";
48 def crbit: Operand<i8> {
49 let PrintMethod = "printcrbit";
52 // Pseudo-instructions:
53 def PHI : Pseudo<(ops), "; PHI">;
55 def ADJCALLSTACKDOWN : Pseudo<(ops), "; ADJCALLSTACKDOWN">;
56 def ADJCALLSTACKUP : Pseudo<(ops), "; ADJCALLSTACKUP">;
58 def IMPLICIT_DEF : Pseudo<(ops), "; IMPLICIT_DEF">;
61 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
63 let isBranch = 1, isTerminator = 1 in {
64 def COND_BRANCH : Pseudo<(ops), "; COND_BRANCH">;
65 def B : IForm<18, 0, 0, 0, 0, (ops target:$func), "b $func">;
66 //def BA : IForm<18, 1, 0, 0, 0, (ops target:$func), "ba $func">;
67 def BL : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
68 //def BLA : IForm<18, 1, 1, 0, 0, (ops target:$func), "bla $func">;
70 // FIXME: 4*CR# needs to be added to the BI field!
71 // This will only work for CR0 as it stands now
72 def BLT : BForm_ext<16, 0, 0, 12, 0, 0, 0, (ops CRRC:$crS, target:$block),
74 def BLE : BForm_ext<16, 0, 0, 4, 1, 0, 0, (ops CRRC:$crS, target:$block),
76 def BEQ : BForm_ext<16, 0, 0, 12, 2, 0, 0, (ops CRRC:$crS, target:$block),
78 def BGE : BForm_ext<16, 0, 0, 4, 0, 0, 0, (ops CRRC:$crS, target:$block),
80 def BGT : BForm_ext<16, 0, 0, 12, 1, 0, 0, (ops CRRC:$crS, target:$block),
82 def BNE : BForm_ext<16, 0, 0, 4, 2, 0, 0, (ops CRRC:$crS, target:$block),
86 let isBranch = 1, isTerminator = 1, isCall = 1,
87 // All calls clobber the non-callee saved registers...
88 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
89 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
91 CR0,CR1,CR5,CR6,CR7] in {
92 // Convenient aliases for call instructions
93 def CALLpcrel : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
94 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1, 0, 0, (ops), "bctrl">;
97 // D-Form instructions. Most instructions that perform an operation on a
98 // register and an immediate are of this type.
101 def LBZ : DForm_1<34, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
102 "lbz $rD, $disp($rA)">;
103 def LHA : DForm_1<42, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
104 "lha $rD, $disp($rA)">;
105 def LHZ : DForm_1<40, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
106 "lhz $rD, $disp($rA)">;
107 def LMW : DForm_1<46, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
108 "lmw $rD, $disp($rA)">;
109 def LWZ : DForm_1<32, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
110 "lwz $rD, $disp($rA)">;
111 def LWZU : DForm_1<35, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
112 "lwzu $rD, $disp($rA)">;
114 def ADDI : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
115 "addi $rD, $rA, $imm">;
116 def ADDIC : DForm_2<12, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
117 "addic $rD, $rA, $imm">;
118 def ADDICo : DForm_2<13, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
119 "addic. $rD, $rA, $imm">;
120 def ADDIS : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
121 "addis $rD, $rA, $imm">;
122 def LA : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
123 "la $rD, $sym($rA)">;
124 def LOADHiAddr : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolHi:$sym),
125 "addis $rD, $rA, $sym">;
126 def MULLI : DForm_2< 7, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
127 "mulli $rD, $rA, $imm">;
128 def SUBFIC : DForm_2< 8, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
129 "subfic $rD, $rA, $imm">;
130 def LI : DForm_2_r0<14, 0, 0, (ops GPRC:$rD, s16imm:$imm),
132 def LIS : DForm_2_r0<15, 0, 0, (ops GPRC:$rD, s16imm:$imm),
135 def STMW : DForm_3<47, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
136 "stmw $rS, $disp($rA)">;
137 def STB : DForm_3<38, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
138 "stb $rS, $disp($rA)">;
139 def STH : DForm_3<44, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
140 "sth $rS, $disp($rA)">;
141 def STW : DForm_3<36, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
142 "stw $rS, $disp($rA)">;
143 def STWU : DForm_3<37, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
144 "stwu $rS, $disp($rA)">;
146 let Defs = [CR0] in {
147 def ANDIo : DForm_4<28, 0, 0,
148 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
149 "andi. $dst, $src1, $src2">;
150 def ANDISo : DForm_4<29, 0, 0,
151 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
152 "andis. $dst, $src1, $src2">;
154 def ORI : DForm_4<24, 0, 0,
155 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
156 "ori $dst, $src1, $src2">;
157 def ORIS : DForm_4<25, 0, 0,
158 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
159 "oris $dst, $src1, $src2">;
160 def XORI : DForm_4<26, 0, 0,
161 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
162 "xori $dst, $src1, $src2">;
163 def XORIS : DForm_4<27, 0, 0,
164 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
165 "xoris $dst, $src1, $src2">;
166 def NOP : DForm_4_zero<24, 0, 0, (ops), "nop">;
167 def CMPI : DForm_5<11, 0, 0, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
168 "cmpi $crD, $L, $rA, $imm">;
169 def CMPWI : DForm_5_ext<11, 0, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
170 "cmpwi $crD, $rA, $imm">;
171 def CMPDI : DForm_5_ext<11, 1, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
172 "cmpdi $crD, $rA, $imm">;
173 def CMPLI : DForm_6<10, 0, 0,
174 (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
175 "cmpli $dst, $size, $src1, $src2">;
176 def CMPLWI : DForm_6_ext<10, 0, 0,
177 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
178 "cmplwi $dst, $src1, $src2">;
179 def CMPLDI : DForm_6_ext<10, 1, 0,
180 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
181 "cmpldi $dst, $src1, $src2">;
183 def LFS : DForm_8<48, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
184 "lfs $rD, $disp($rA)">;
185 def LFD : DForm_8<50, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
186 "lfd $rD, $disp($rA)">;
189 def STFS : DForm_9<52, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
190 "stfs $rS, $disp($rA)">;
191 def STFD : DForm_9<54, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
192 "stfd $rS, $disp($rA)">;
195 // DS-Form instructions. Load/Store instructions available in PPC-64
198 def LWA : DSForm_1<58, 2, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
199 "lwa $rT, $DS($rA)">;
200 def LD : DSForm_2<58, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
204 def STD : DSForm_2<62, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
205 "std $rT, $DS($rA)">;
206 def STDU : DSForm_2<62, 1, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
207 "stdu $rT, $DS($rA)">;
210 // X-Form instructions. Most instructions that perform an operation on a
211 // register and another register are of this type.
214 def LBZX : XForm_1<31, 87, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
215 "lbzx $dst, $base, $index">;
216 def LHAX : XForm_1<31, 343, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
217 "lhax $dst, $base, $index">;
218 def LHZX : XForm_1<31, 279, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
219 "lhzx $dst, $base, $index">;
220 def LWAX : XForm_1<31, 341, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
221 "lwax $dst, $base, $index">;
222 def LWZX : XForm_1<31, 23, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
223 "lwzx $dst, $base, $index">;
224 def LDX : XForm_1<31, 21, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
225 "ldx $dst, $base, $index">;
227 def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
228 "and $rA, $rS, $rB">;
230 def ANDo : XForm_6<31, 28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
231 "and. $rA, $rS, $rB">;
232 def ANDC : XForm_6<31, 60, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
233 "andc $rA, $rS, $rB">;
234 def EQV : XForm_6<31, 284, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
235 "eqv $rA, $rS, $rB">;
236 def NAND : XForm_6<31, 476, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
237 "nand $rA, $rS, $rB">;
238 def NOR : XForm_6<31, 124, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
239 "nor $rA, $rS, $rB">;
240 def OR : XForm_6<31, 444, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
243 def ORo : XForm_6<31, 444, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
244 "or. $rA, $rS, $rB">;
245 def ORC : XForm_6<31, 412, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
246 "orc $rA, $rS, $rB">;
247 def SLD : XForm_6<31, 27, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
248 "sld $rA, $rS, $rB">;
249 def SLW : XForm_6<31, 24, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
250 "slw $rA, $rS, $rB">;
251 def SRD : XForm_6<31, 539, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
252 "srd $rA, $rS, $rB">;
253 def SRW : XForm_6<31, 536, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
254 "srw $rA, $rS, $rB">;
255 def SRAD : XForm_6<31, 794, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
256 "srad $rA, $rS, $rB">;
257 def SRAW : XForm_6<31, 792, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
258 "sraw $rA, $rS, $rB">;
259 def XOR : XForm_6<31, 316, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
260 "xor $rA, $rS, $rB">;
262 def STBX : XForm_8<31, 215, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
263 "stbx $rS, $rA, $rB">;
264 def STHX : XForm_8<31, 407, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
265 "sthx $rS, $rA, $rB">;
266 def STWX : XForm_8<31, 151, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
267 "stwx $rS, $rA, $rB">;
268 def STWUX : XForm_8<31, 183, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
269 "stwux $rS, $rA, $rB">;
270 def STDX : XForm_8<31, 149, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
271 "stdx $rS, $rA, $rB">;
272 def STDUX : XForm_8<31, 181, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
273 "stdux $rS, $rA, $rB">;
275 def SRAWI : XForm_10<31, 824, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
276 "srawi $rA, $rS, $SH">;
277 def CNTLZW : XForm_11<31, 26, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
279 def EXTSB : XForm_11<31, 954, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
281 def EXTSH : XForm_11<31, 922, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
283 def EXTSW : XForm_11<31, 986, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS),
285 def CMP : XForm_16<31, 0, 0, 0,
286 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
287 "cmp $crD, $long, $rA, $rB">;
288 def CMPL : XForm_16<31, 32, 0, 0,
289 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
290 "cmpl $crD, $long, $rA, $rB">;
291 def CMPW : XForm_16_ext<31, 0, 0, 0,
292 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
293 "cmpw $crD, $rA, $rB">;
294 def CMPD : XForm_16_ext<31, 0, 1, 0,
295 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
296 "cmpd $crD, $rA, $rB">;
297 def CMPLW : XForm_16_ext<31, 32, 0, 0,
298 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
299 "cmplw $crD, $rA, $rB">;
300 def CMPLD : XForm_16_ext<31, 32, 1, 0,
301 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
302 "cmpld $crD, $rA, $rB">;
303 def FCMPO : XForm_17<63, 32, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
304 "fcmpo $crD, $fA, $fB">;
305 def FCMPU : XForm_17<63, 0, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
306 "fcmpu $crD, $fA, $fB">;
308 def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
309 "lfsx $dst, $base, $index">;
310 def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
311 "lfdx $dst, $base, $index">;
313 def FCFID : XForm_26<63, 846, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
315 def FCTIDZ : XForm_26<63, 815, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
316 "fctidz $frD, $frB">;
317 def FCTIWZ : XForm_26<63, 15, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
318 "fctiwz $frD, $frB">;
319 def FABS : XForm_26<63, 264, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
321 def FMR : XForm_26<63, 72, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
323 def FNABS : XForm_26<63, 136, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
325 def FNEG : XForm_26<63, 40, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
327 def FRSP : XForm_26<63, 12, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
330 def STFSX : XForm_28<31, 663, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
331 "stfsx $frS, $rA, $rB">;
332 def STFDX : XForm_28<31, 727, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
333 "stfdx $frS, $rA, $rB">;
336 // XL-Form instructions. condition register logical ops.
338 def CRAND : XLForm_1<19, 257, 0, 0, (ops CRRC:$D, crbit:$Db,
339 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
340 "crand $Db, $Ab, $Bb">;
341 def CRANDC : XLForm_1<19, 129, 0, 0, (ops CRRC:$D, crbit:$Db,
342 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
343 "crandc $Db, $Ab, $Bb">;
344 def CREQV : XLForm_1<19, 289, 0, 0, (ops CRRC:$D, crbit:$Db,
345 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
346 "creqv $Db, $Ab, $Bb">;
347 def CRNAND : XLForm_1<19, 225, 0, 0, (ops CRRC:$D, crbit:$Db,
348 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
349 "crnand $Db, $Ab, $Bb">;
350 def CRNOR : XLForm_1<19, 33, 0, 0, (ops CRRC:$D, crbit:$Db,
351 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
352 "crnor $Db, $Ab, $Bb">;
353 def CROR : XLForm_1<19, 449, 0, 0, (ops CRRC:$D, crbit:$Db,
354 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
355 "cror $Db, $Ab, $Bb">;
356 def CRORC : XLForm_1<19, 417, 0, 0, (ops CRRC:$D, crbit:$Db,
357 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
358 "crorc $Db, $Ab, $Bb">;
359 def CRXOR : XLForm_1<19, 193, 0, 0, (ops CRRC:$D, crbit:$Db,
360 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
361 "crxor $Db, $Ab, $Bb">;
362 def MCRF : XLForm_3<19, 0, 0, 0, (ops CRRC:$BF, CRRC:$BFA),
365 // XFX-Form instructions. Instructions that deal with SPRs
367 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
368 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
369 // which means the SPR value needs to be multiplied by a factor of 32.
370 def MFCTR : XFXForm_1_ext<31, 339, 288, 0, 0, (ops GPRC:$rT), "mfctr $rT">;
371 def MFLR : XFXForm_1_ext<31, 339, 256, 0, 0, (ops GPRC:$rT), "mflr $rT">;
372 def MFCR : XFXForm_3<31, 19, 0, 0, (ops GPRC:$rT), "mfcr $rT">;
373 def MTCRF : XFXForm_5<31, 0, 144, 0, 0, (ops CRRC:$FXM, GPRC:$rS),
375 def MFCRF : XFXForm_5<31, 1, 19, 0, 0, (ops GPRC:$rT, CRRC:$FXM),
377 def MTCTR : XFXForm_7_ext<31, 467, 288, 0, 0, (ops GPRC:$rS), "mtctr $rS">;
378 def MTLR : XFXForm_7_ext<31, 467, 256, 0, 0, (ops GPRC:$rS), "mtlr $rS">;
380 // XS-Form instructions. Just 'sradi'
382 def SRADI : XSForm_1<31, 413, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
383 "sradi $rA, $rS, $SH">;
385 // XO-Form instructions. Arithmetic instructions that can set overflow bit
387 def ADD : XOForm_1<31, 266, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
388 "add $rT, $rA, $rB">;
389 def ADDC : XOForm_1<31, 10, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
390 "addc $rT, $rA, $rB">;
391 def ADDE : XOForm_1<31, 138, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
392 "adde $rT, $rA, $rB">;
393 def DIVD : XOForm_1<31, 489, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
394 "divd $rT, $rA, $rB">;
395 def DIVDU : XOForm_1<31, 457, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
396 "divdu $rT, $rA, $rB">;
397 def DIVW : XOForm_1<31, 491, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
398 "divw $rT, $rA, $rB">;
399 def DIVWU : XOForm_1<31, 459, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
400 "divwu $rT, $rA, $rB">;
401 def MULHW : XOForm_1<31, 75, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
402 "mulhw $rT, $rA, $rB">;
403 def MULHWU : XOForm_1<31, 11, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
404 "mulhwu $rT, $rA, $rB">;
405 def MULLD : XOForm_1<31, 233, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
406 "mulld $rT, $rA, $rB">;
407 def MULLW : XOForm_1<31, 235, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
408 "mullw $rT, $rA, $rB">;
409 def SUBF : XOForm_1<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
410 "subf $rT, $rA, $rB">;
411 def SUBFC : XOForm_1<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
412 "subfc $rT, $rA, $rB">;
413 def SUBFE : XOForm_1<31, 136, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
414 "subfe $rT, $rA, $rB">;
415 def SUB : XOForm_1r<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
416 "sub $rT, $rA, $rB">;
417 def ADDME : XOForm_3<31, 234, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
419 def ADDZE : XOForm_3<31, 202, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
421 def NEG : XOForm_3<31, 104, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
423 def SUBFZE : XOForm_3<31, 200, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
426 // A-Form instructions. Most of the instructions executed in the FPU are of
429 def FMADD : AForm_1<63, 29, 0, 0, 0,
430 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
431 "fmadd $FRT, $FRA, $FRC, $FRB">;
432 def FMADDS : AForm_1<59, 29, 0, 0, 0,
433 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
434 "fmadds $FRT, $FRA, $FRC, $FRB">;
435 def FMSUB : AForm_1<63, 28, 0, 0, 0,
436 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
437 "fmsub $FRT, $FRA, $FRC, $FRB">;
438 def FMSUBS : AForm_1<59, 28, 0, 0, 0,
439 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
440 "fmsubs $FRT, $FRA, $FRC, $FRB">;
441 def FNMADD : AForm_1<63, 31, 0, 0, 0,
442 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
443 "fnmadd $FRT, $FRA, $FRC, $FRB">;
444 def FNMADDS : AForm_1<59, 31, 0, 0, 0,
445 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
446 "fnmadds $FRT, $FRA, $FRC, $FRB">;
447 def FNMSUB : AForm_1<63, 30, 0, 0, 0,
448 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
449 "fnmsub $FRT, $FRA, $FRC, $FRB">;
450 def FNMSUBS : AForm_1<59, 30, 0, 0, 0,
451 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
452 "fnmsubs $FRT, $FRA, $FRC, $FRB">;
453 def FSEL : AForm_1<63, 23, 0, 0, 0,
454 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
455 "fsel $FRT, $FRA, $FRC, $FRB">;
456 def FADD : AForm_2<63, 21, 0, 0, 0,
457 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
458 "fadd $FRT, $FRA, $FRB">;
459 def FADDS : AForm_2<59, 21, 0, 0, 0,
460 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
461 "fadds $FRT, $FRA, $FRB">;
462 def FDIV : AForm_2<63, 18, 0, 0, 0,
463 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
464 "fdiv $FRT, $FRA, $FRB">;
465 def FDIVS : AForm_2<59, 18, 0, 0, 0,
466 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
467 "fdivs $FRT, $FRA, $FRB">;
468 def FMUL : AForm_3<63, 25, 0, 0, 0,
469 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
470 "fmul $FRT, $FRA, $FRB">;
471 def FMULS : AForm_3<59, 25, 0, 0, 0,
472 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
473 "fmuls $FRT, $FRA, $FRB">;
474 def FSUB : AForm_2<63, 20, 0, 0, 0,
475 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
476 "fsub $FRT, $FRA, $FRB">;
477 def FSUBS : AForm_2<59, 20, 0, 0, 0,
478 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
479 "fsubs $FRT, $FRA, $FRB">;
481 // M-Form instructions. rotate and mask instructions.
483 let isTwoAddress = 1 in {
484 def RLWIMI : MForm_2<20, 0, 0, 0,
485 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
486 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
488 def RLWINM : MForm_2<21, 0, 0, 0,
489 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
490 "rlwinm $rA, $rS, $SH, $MB, $ME">;
492 def RLWINMo : MForm_2<21, 1, 0, 0,
493 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
494 "rlwinm. $rA, $rS, $SH, $MB, $ME">;
495 def RLWNM : MForm_2<23, 0, 0, 0,
496 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
497 "rlwnm $rA, $rS, $rB, $MB, $ME">;
499 // MD-Form instructions. 64 bit rotate instructions.
501 def RLDICL : MDForm_1<30, 0, 0, 1, 0,
502 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
503 "rldicl $rA, $rS, $SH, $MB">;
504 def RLDICR : MDForm_1<30, 1, 0, 1, 0,
505 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
506 "rldicr $rA, $rS, $SH, $ME">;
508 def PowerPCInstrInfo : InstrInfo {
511 let TSFlagsFields = [ "VMX", "PPC64" ];
512 let TSFlagsShifts = [ 0, 1 ];
514 let isLittleEndianEncoding = 1;