1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
26 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
28 def SDT_PPCvperm : SDTypeProfile<1, 3, [
29 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
32 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
33 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
36 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
37 SDTCisVT<1, i32>, SDTCisVT<2, OtherVT>
40 def SDT_PPClbrx : SDTypeProfile<1, 3, [
41 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
43 def SDT_PPCstbrx : SDTypeProfile<0, 4, [
44 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
47 //===----------------------------------------------------------------------===//
48 // PowerPC specific DAG Nodes.
51 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
52 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
53 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
54 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
56 def PPCfsel : SDNode<"PPCISD::FSEL",
57 // Type constraint for fsel.
58 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
59 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
61 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
62 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
63 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
64 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
66 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
68 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
69 // amounts. These nodes are generated by the multi-precision shift code.
70 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
71 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
72 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
74 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
75 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
77 // These are target-independent nodes, but have target-specific formats.
78 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,
79 [SDNPHasChain, SDNPOutFlag]>;
80 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,
81 [SDNPHasChain, SDNPOutFlag]>;
83 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
84 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
85 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
86 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
87 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
88 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTRet,
89 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
91 def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet,
92 [SDNPHasChain, SDNPOptInFlag]>;
94 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
95 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
97 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
98 [SDNPHasChain, SDNPOptInFlag]>;
100 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>;
101 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain]>;
103 //===----------------------------------------------------------------------===//
104 // PowerPC specific transformation functions and pattern fragments.
107 def SHL32 : SDNodeXForm<imm, [{
108 // Transformation function: 31 - imm
109 return getI32Imm(31 - N->getValue());
112 def SRL32 : SDNodeXForm<imm, [{
113 // Transformation function: 32 - imm
114 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
117 def LO16 : SDNodeXForm<imm, [{
118 // Transformation function: get the low 16 bits.
119 return getI32Imm((unsigned short)N->getValue());
122 def HI16 : SDNodeXForm<imm, [{
123 // Transformation function: shift the immediate value down into the low bits.
124 return getI32Imm((unsigned)N->getValue() >> 16);
127 def HA16 : SDNodeXForm<imm, [{
128 // Transformation function: shift the immediate value down into the low bits.
129 signed int Val = N->getValue();
130 return getI32Imm((Val - (signed short)Val) >> 16);
132 def MB : SDNodeXForm<imm, [{
133 // Transformation function: get the start bit of a mask
135 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
136 return getI32Imm(mb);
139 def ME : SDNodeXForm<imm, [{
140 // Transformation function: get the end bit of a mask
142 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
143 return getI32Imm(me);
145 def maskimm32 : PatLeaf<(imm), [{
146 // maskImm predicate - True if immediate is a run of ones.
148 if (N->getValueType(0) == MVT::i32)
149 return isRunOfOnes((unsigned)N->getValue(), mb, me);
154 def immSExt16 : PatLeaf<(imm), [{
155 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
156 // field. Used by instructions like 'addi'.
157 if (N->getValueType(0) == MVT::i32)
158 return (int32_t)N->getValue() == (short)N->getValue();
160 return (int64_t)N->getValue() == (short)N->getValue();
162 def immZExt16 : PatLeaf<(imm), [{
163 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
164 // field. Used by instructions like 'ori'.
165 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
168 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
169 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
170 // identical in 32-bit mode, but in 64-bit mode, they return true if the
171 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
173 def imm16ShiftedZExt : PatLeaf<(imm), [{
174 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
175 // immediate are set. Used by instructions like 'xoris'.
176 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
179 def imm16ShiftedSExt : PatLeaf<(imm), [{
180 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
181 // immediate are set. Used by instructions like 'addis'. Identical to
182 // imm16ShiftedZExt in 32-bit mode.
183 if (N->getValue() & 0xFFFF) return false;
184 if (N->getValueType(0) == MVT::i32)
186 // For 64-bit, make sure it is sext right.
187 return N->getValue() == (uint64_t)(int)N->getValue();
191 //===----------------------------------------------------------------------===//
192 // PowerPC Flag Definitions.
194 class isPPC64 { bit PPC64 = 1; }
196 list<Register> Defs = [CR0];
200 class RegConstraint<string C> {
201 string Constraints = C;
205 //===----------------------------------------------------------------------===//
206 // PowerPC Operand Definitions.
208 def s5imm : Operand<i32> {
209 let PrintMethod = "printS5ImmOperand";
211 def u5imm : Operand<i32> {
212 let PrintMethod = "printU5ImmOperand";
214 def u6imm : Operand<i32> {
215 let PrintMethod = "printU6ImmOperand";
217 def s16imm : Operand<i32> {
218 let PrintMethod = "printS16ImmOperand";
220 def u16imm : Operand<i32> {
221 let PrintMethod = "printU16ImmOperand";
223 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
224 let PrintMethod = "printS16X4ImmOperand";
226 def target : Operand<OtherVT> {
227 let PrintMethod = "printBranchOperand";
229 def calltarget : Operand<iPTR> {
230 let PrintMethod = "printCallOperand";
232 def aaddr : Operand<iPTR> {
233 let PrintMethod = "printAbsAddrOperand";
235 def piclabel: Operand<iPTR> {
236 let PrintMethod = "printPICLabel";
238 def symbolHi: Operand<i32> {
239 let PrintMethod = "printSymbolHi";
241 def symbolLo: Operand<i32> {
242 let PrintMethod = "printSymbolLo";
244 def crbitm: Operand<i8> {
245 let PrintMethod = "printcrbitm";
248 def memri : Operand<iPTR> {
249 let PrintMethod = "printMemRegImm";
250 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
252 def memrr : Operand<iPTR> {
253 let PrintMethod = "printMemRegReg";
254 let MIOperandInfo = (ops ptr_rc, ptr_rc);
256 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
257 let PrintMethod = "printMemRegImmShifted";
258 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
261 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
262 // that doesn't matter.
263 def pred : PredicateOperand<(ops imm, CRRC), (ops (i32 20), CR0)> {
264 let PrintMethod = "printPredicateOperand";
267 // Define PowerPC specific addressing mode.
268 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
269 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
270 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
271 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
274 //===----------------------------------------------------------------------===//
275 // PowerPC Instruction Predicate Definitions.
276 def FPContractions : Predicate<"!NoExcessFPPrecision">;
279 //===----------------------------------------------------------------------===//
280 // PowerPC Instruction Definitions.
282 // Pseudo-instructions:
284 let hasCtrlDep = 1 in {
285 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
286 "${:comment} ADJCALLSTACKDOWN",
287 [(callseq_start imm:$amt)]>, Imp<[R1],[R1]>;
288 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
289 "${:comment} ADJCALLSTACKUP",
290 [(callseq_end imm:$amt)]>, Imp<[R1],[R1]>;
292 def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS),
293 "UPDATE_VRSAVE $rD, $rS", []>;
295 def IMPLICIT_DEF_GPRC: Pseudo<(ops GPRC:$rD),"${:comment}IMPLICIT_DEF_GPRC $rD",
296 [(set GPRC:$rD, (undef))]>;
297 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "${:comment} IMPLICIT_DEF_F8 $rD",
298 [(set F8RC:$rD, (undef))]>;
299 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "${:comment} IMPLICIT_DEF_F4 $rD",
300 [(set F4RC:$rD, (undef))]>;
302 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
303 // scheduler into a branch sequence.
304 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
305 PPC970_Single = 1 in {
306 def SELECT_CC_I4 : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
307 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
309 def SELECT_CC_I8 : Pseudo<(ops G8RC:$dst, CRRC:$cond, G8RC:$T, G8RC:$F,
310 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
312 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
313 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
315 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
316 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
318 def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F,
319 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
323 let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in {
325 def BLR : XLForm_2_br<19, 16, 0,
327 "b${p:cc}lr ${p:reg}", BrB,
329 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
335 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
338 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
339 noResults = 1, PPC970_Unit = 7 in {
340 // COND_BRANCH is formed before branch selection, it is turned into Bcc below.
341 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst),
342 "${:comment} COND_BRANCH $crS, $opc, $dst",
343 [(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>;
344 let isBarrier = 1 in {
345 def B : IForm<18, 0, 0, (ops target:$dst),
350 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
351 "blt $crS, $block", BrB>;
352 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
353 "ble $crS, $block", BrB>;
354 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
355 "beq $crS, $block", BrB>;
356 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
357 "bge $crS, $block", BrB>;
358 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
359 "bgt $crS, $block", BrB>;
360 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
361 "bne $crS, $block", BrB>;
362 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
363 "bun $crS, $block", BrB>;
364 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
365 "bnu $crS, $block", BrB>;
368 let isCall = 1, noResults = 1, PPC970_Unit = 7,
369 // All calls clobber the non-callee saved registers...
370 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
371 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
372 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
374 CR0,CR1,CR5,CR6,CR7] in {
375 // Convenient aliases for call instructions
376 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
377 "bl $func", BrB, []>; // See Pat patterns below.
378 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
379 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
380 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB,
384 // DCB* instructions.
385 def DCBA : DCB_Form<758, 0, (ops memrr:$dst),
386 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
387 PPC970_DGroup_Single;
388 def DCBF : DCB_Form<86, 0, (ops memrr:$dst),
389 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
390 PPC970_DGroup_Single;
391 def DCBI : DCB_Form<470, 0, (ops memrr:$dst),
392 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
393 PPC970_DGroup_Single;
394 def DCBST : DCB_Form<54, 0, (ops memrr:$dst),
395 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
396 PPC970_DGroup_Single;
397 def DCBT : DCB_Form<278, 0, (ops memrr:$dst),
398 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
399 PPC970_DGroup_Single;
400 def DCBTST : DCB_Form<246, 0, (ops memrr:$dst),
401 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
402 PPC970_DGroup_Single;
403 def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst),
404 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
405 PPC970_DGroup_Single;
406 def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst),
407 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
408 PPC970_DGroup_Single;
410 //===----------------------------------------------------------------------===//
411 // PPC32 Load Instructions.
414 // Unindexed (r+i) Loads.
415 let isLoad = 1, PPC970_Unit = 2 in {
416 def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
417 "lbz $rD, $src", LdStGeneral,
418 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
419 def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
420 "lha $rD, $src", LdStLHA,
421 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
422 PPC970_DGroup_Cracked;
423 def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
424 "lhz $rD, $src", LdStGeneral,
425 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
426 def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
427 "lwz $rD, $src", LdStGeneral,
428 [(set GPRC:$rD, (load iaddr:$src))]>;
430 def LFS : DForm_1<48, (ops F4RC:$rD, memri:$src),
431 "lfs $rD, $src", LdStLFDU,
432 [(set F4RC:$rD, (load iaddr:$src))]>;
433 def LFD : DForm_1<50, (ops F8RC:$rD, memri:$src),
434 "lfd $rD, $src", LdStLFD,
435 [(set F8RC:$rD, (load iaddr:$src))]>;
438 // Unindexed (r+i) Loads with Update (preinc).
439 def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
440 "lbzu $rD, $addr", LdStGeneral,
441 []>, RegConstraint<"$addr.reg = $ea_result">;
443 def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
444 "lhau $rD, $addr", LdStGeneral,
445 []>, RegConstraint<"$addr.reg = $ea_result">;
447 def LHZU : DForm_1<41, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
448 "lhzu $rD, $addr", LdStGeneral,
449 []>, RegConstraint<"$addr.reg = $ea_result">;
451 def LWZU : DForm_1<33, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
452 "lwzu $rD, $addr", LdStGeneral,
453 []>, RegConstraint<"$addr.reg = $ea_result">;
455 def LFSU : DForm_1<49, (ops F4RC:$rD, ptr_rc:$ea_result, memri:$addr),
456 "lfs $rD, $addr", LdStLFDU,
457 []>, RegConstraint<"$addr.reg = $ea_result">;
458 def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$ea_result, memri:$addr),
459 "lfd $rD, $addr", LdStLFD,
460 []>, RegConstraint<"$addr.reg = $ea_result">;
463 // Indexed (r+r) Loads.
465 let isLoad = 1, PPC970_Unit = 2 in {
466 def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
467 "lbzx $rD, $src", LdStGeneral,
468 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
469 def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
470 "lhax $rD, $src", LdStLHA,
471 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
472 PPC970_DGroup_Cracked;
473 def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
474 "lhzx $rD, $src", LdStGeneral,
475 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
476 def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
477 "lwzx $rD, $src", LdStGeneral,
478 [(set GPRC:$rD, (load xaddr:$src))]>;
481 def LHBRX : XForm_1<31, 790, (ops GPRC:$rD, memrr:$src),
482 "lhbrx $rD, $src", LdStGeneral,
483 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
484 def LWBRX : XForm_1<31, 534, (ops GPRC:$rD, memrr:$src),
485 "lwbrx $rD, $src", LdStGeneral,
486 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
488 def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src),
489 "lfsx $frD, $src", LdStLFDU,
490 [(set F4RC:$frD, (load xaddr:$src))]>;
491 def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
492 "lfdx $frD, $src", LdStLFDU,
493 [(set F8RC:$frD, (load xaddr:$src))]>;
496 //===----------------------------------------------------------------------===//
497 // PPC32 Store Instructions.
500 // Unindexed (r+i) Stores.
501 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
502 def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
503 "stb $rS, $src", LdStGeneral,
504 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
505 def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
506 "sth $rS, $src", LdStGeneral,
507 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
508 def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
509 "stw $rS, $src", LdStGeneral,
510 [(store GPRC:$rS, iaddr:$src)]>;
511 def STFS : DForm_1<52, (ops F4RC:$rS, memri:$dst),
512 "stfs $rS, $dst", LdStUX,
513 [(store F4RC:$rS, iaddr:$dst)]>;
514 def STFD : DForm_1<54, (ops F8RC:$rS, memri:$dst),
515 "stfd $rS, $dst", LdStUX,
516 [(store F8RC:$rS, iaddr:$dst)]>;
519 // Unindexed (r+i) Stores with Update (preinc).
520 let isStore = 1, PPC970_Unit = 2 in {
521 def STBU : DForm_3<39, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
522 "stbu $rS, $addr", LdStGeneral,
523 [/*(set ptr_rc:$ea_res,
524 (pre_truncsti8 GPRC:$rS, iaddr:$addr))*/]>,
525 RegConstraint<"$addr.reg = $ea_res">;
526 def STHU : DForm_3<37, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
527 "sthu $rS, $addr", LdStGeneral,
528 [/*(set ptr_rc:$ea_res,
529 (pre_truncsti16 GPRC:$rS, iaddr:$addr))*/]>,
530 RegConstraint<"$addr.reg = $ea_res">;
531 def STWU : DForm_3<37, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
532 "stwu $rS, $addr", LdStGeneral,
533 [/*(set ptr_rc:$ea_res, (pre_store GPRC:$rS, iaddr:$addr))*/]>,
534 RegConstraint<"$addr.reg = $ea_res">;
535 def STFSU : DForm_3<37, (ops ptr_rc:$ea_res, F4RC:$rS, memri:$addr),
536 "stfsu $rS, $addr", LdStGeneral,
537 [/*(set ptr_rc:$ea_res, (pre_store F4RC:$rS, iaddr:$addr))*/]>,
538 RegConstraint<"$addr.reg = $ea_res">;
539 def STFDU : DForm_3<37, (ops ptr_rc:$ea_res, F8RC:$rS, memri:$addr),
540 "stfdu $rS, $addr", LdStGeneral,
541 [/*(set ptr_rc:$ea_res, (pre_store F8RC:$rS, iaddr:$addr))*/]>,
542 RegConstraint<"$addr.reg = $ea_res">;
546 // Indexed (r+r) Stores.
548 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
549 def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
550 "stbx $rS, $dst", LdStGeneral,
551 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
552 PPC970_DGroup_Cracked;
553 def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
554 "sthx $rS, $dst", LdStGeneral,
555 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
556 PPC970_DGroup_Cracked;
557 def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
558 "stwx $rS, $dst", LdStGeneral,
559 [(store GPRC:$rS, xaddr:$dst)]>,
560 PPC970_DGroup_Cracked;
561 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
562 "stwux $rS, $rA, $rB", LdStGeneral,
564 def STHBRX: XForm_8<31, 918, (ops GPRC:$rS, memrr:$dst),
565 "sthbrx $rS, $dst", LdStGeneral,
566 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
567 PPC970_DGroup_Cracked;
568 def STWBRX: XForm_8<31, 662, (ops GPRC:$rS, memrr:$dst),
569 "stwbrx $rS, $dst", LdStGeneral,
570 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>,
571 PPC970_DGroup_Cracked;
573 def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst),
574 "stfiwx $frS, $dst", LdStUX,
575 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
576 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst),
577 "stfsx $frS, $dst", LdStUX,
578 [(store F4RC:$frS, xaddr:$dst)]>;
579 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst),
580 "stfdx $frS, $dst", LdStUX,
581 [(store F8RC:$frS, xaddr:$dst)]>;
585 //===----------------------------------------------------------------------===//
586 // PPC32 Arithmetic Instructions.
589 let PPC970_Unit = 1 in { // FXU Operations.
590 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
591 "addi $rD, $rA, $imm", IntGeneral,
592 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
593 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
594 "addic $rD, $rA, $imm", IntGeneral,
595 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
596 PPC970_DGroup_Cracked;
597 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
598 "addic. $rD, $rA, $imm", IntGeneral,
600 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
601 "addis $rD, $rA, $imm", IntGeneral,
602 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
603 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
604 "la $rD, $sym($rA)", IntGeneral,
605 [(set GPRC:$rD, (add GPRC:$rA,
606 (PPClo tglobaladdr:$sym, 0)))]>;
607 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
608 "mulli $rD, $rA, $imm", IntMulLI,
609 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
610 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
611 "subfic $rD, $rA, $imm", IntGeneral,
612 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
613 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
614 "li $rD, $imm", IntGeneral,
615 [(set GPRC:$rD, immSExt16:$imm)]>;
616 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
617 "lis $rD, $imm", IntGeneral,
618 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
621 let PPC970_Unit = 1 in { // FXU Operations.
622 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
623 "andi. $dst, $src1, $src2", IntGeneral,
624 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
626 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
627 "andis. $dst, $src1, $src2", IntGeneral,
628 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
630 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
631 "ori $dst, $src1, $src2", IntGeneral,
632 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
633 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
634 "oris $dst, $src1, $src2", IntGeneral,
635 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
636 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
637 "xori $dst, $src1, $src2", IntGeneral,
638 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
639 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
640 "xoris $dst, $src1, $src2", IntGeneral,
641 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
642 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
644 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
645 "cmpwi $crD, $rA, $imm", IntCompare>;
646 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
647 "cmplwi $dst, $src1, $src2", IntCompare>;
651 let PPC970_Unit = 1 in { // FXU Operations.
652 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
653 "nand $rA, $rS, $rB", IntGeneral,
654 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
655 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
656 "and $rA, $rS, $rB", IntGeneral,
657 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
658 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
659 "andc $rA, $rS, $rB", IntGeneral,
660 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
661 def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
662 "or $rA, $rS, $rB", IntGeneral,
663 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
664 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
665 "nor $rA, $rS, $rB", IntGeneral,
666 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
667 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
668 "orc $rA, $rS, $rB", IntGeneral,
669 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
670 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
671 "eqv $rA, $rS, $rB", IntGeneral,
672 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
673 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
674 "xor $rA, $rS, $rB", IntGeneral,
675 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
676 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
677 "slw $rA, $rS, $rB", IntGeneral,
678 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
679 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
680 "srw $rA, $rS, $rB", IntGeneral,
681 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
682 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
683 "sraw $rA, $rS, $rB", IntShift,
684 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
687 let PPC970_Unit = 1 in { // FXU Operations.
688 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
689 "srawi $rA, $rS, $SH", IntShift,
690 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
691 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
692 "cntlzw $rA, $rS", IntGeneral,
693 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
694 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
695 "extsb $rA, $rS", IntGeneral,
696 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
697 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
698 "extsh $rA, $rS", IntGeneral,
699 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
701 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
702 "cmpw $crD, $rA, $rB", IntCompare>;
703 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
704 "cmplw $crD, $rA, $rB", IntCompare>;
706 let PPC970_Unit = 3 in { // FPU Operations.
707 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
708 // "fcmpo $crD, $fA, $fB", FPCompare>;
709 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
710 "fcmpu $crD, $fA, $fB", FPCompare>;
711 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
712 "fcmpu $crD, $fA, $fB", FPCompare>;
714 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
715 "fctiwz $frD, $frB", FPGeneral,
716 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
717 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
718 "frsp $frD, $frB", FPGeneral,
719 [(set F4RC:$frD, (fround F8RC:$frB))]>;
720 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
721 "fsqrt $frD, $frB", FPSqrt,
722 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
723 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
724 "fsqrts $frD, $frB", FPSqrt,
725 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
728 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
730 /// Note that these are defined as pseudo-ops on the PPC970 because they are
731 /// often coalesced away and we don't want the dispatch group builder to think
732 /// that they will fill slots (which could cause the load of a LSU reject to
733 /// sneak into a d-group with a store).
734 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
735 "fmr $frD, $frB", FPGeneral,
736 []>, // (set F4RC:$frD, F4RC:$frB)
738 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
739 "fmr $frD, $frB", FPGeneral,
740 []>, // (set F8RC:$frD, F8RC:$frB)
742 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
743 "fmr $frD, $frB", FPGeneral,
744 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
747 let PPC970_Unit = 3 in { // FPU Operations.
748 // These are artificially split into two different forms, for 4/8 byte FP.
749 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
750 "fabs $frD, $frB", FPGeneral,
751 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
752 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
753 "fabs $frD, $frB", FPGeneral,
754 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
755 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
756 "fnabs $frD, $frB", FPGeneral,
757 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
758 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
759 "fnabs $frD, $frB", FPGeneral,
760 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
761 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
762 "fneg $frD, $frB", FPGeneral,
763 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
764 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
765 "fneg $frD, $frB", FPGeneral,
766 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
770 // XL-Form instructions. condition register logical ops.
772 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
773 "mcrf $BF, $BFA", BrMCR>,
774 PPC970_DGroup_First, PPC970_Unit_CRU;
776 // XFX-Form instructions. Instructions that deal with SPRs.
778 def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>,
779 PPC970_DGroup_First, PPC970_Unit_FXU;
780 let Pattern = [(PPCmtctr GPRC:$rS)] in {
781 def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>,
782 PPC970_DGroup_First, PPC970_Unit_FXU;
785 def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>,
786 PPC970_DGroup_First, PPC970_Unit_FXU;
787 def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>,
788 PPC970_DGroup_First, PPC970_Unit_FXU;
790 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
791 // a GPR on the PPC970. As such, copies in and out have the same performance
792 // characteristics as an OR instruction.
793 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS),
794 "mtspr 256, $rS", IntGeneral>,
795 PPC970_DGroup_Single, PPC970_Unit_FXU;
796 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT),
797 "mfspr $rT, 256", IntGeneral>,
798 PPC970_DGroup_First, PPC970_Unit_FXU;
800 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
801 "mtcrf $FXM, $rS", BrMCRX>,
802 PPC970_MicroCode, PPC970_Unit_CRU;
803 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>,
804 PPC970_MicroCode, PPC970_Unit_CRU;
805 def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
806 "mfcr $rT, $FXM", SprMFCR>,
807 PPC970_DGroup_First, PPC970_Unit_CRU;
809 let PPC970_Unit = 1 in { // FXU Operations.
811 // XO-Form instructions. Arithmetic instructions that can set overflow bit
813 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
814 "add $rT, $rA, $rB", IntGeneral,
815 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
816 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
817 "addc $rT, $rA, $rB", IntGeneral,
818 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
819 PPC970_DGroup_Cracked;
820 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
821 "adde $rT, $rA, $rB", IntGeneral,
822 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
823 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
824 "divw $rT, $rA, $rB", IntDivW,
825 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
826 PPC970_DGroup_First, PPC970_DGroup_Cracked;
827 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
828 "divwu $rT, $rA, $rB", IntDivW,
829 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
830 PPC970_DGroup_First, PPC970_DGroup_Cracked;
831 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
832 "mulhw $rT, $rA, $rB", IntMulHW,
833 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
834 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
835 "mulhwu $rT, $rA, $rB", IntMulHWU,
836 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
837 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
838 "mullw $rT, $rA, $rB", IntMulHW,
839 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
840 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
841 "subf $rT, $rA, $rB", IntGeneral,
842 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
843 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
844 "subfc $rT, $rA, $rB", IntGeneral,
845 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
846 PPC970_DGroup_Cracked;
847 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
848 "subfe $rT, $rA, $rB", IntGeneral,
849 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
850 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
851 "addme $rT, $rA", IntGeneral,
852 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
853 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
854 "addze $rT, $rA", IntGeneral,
855 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
856 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
857 "neg $rT, $rA", IntGeneral,
858 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
859 def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA),
860 "subfme $rT, $rA", IntGeneral,
861 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
862 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
863 "subfze $rT, $rA", IntGeneral,
864 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
867 // A-Form instructions. Most of the instructions executed in the FPU are of
870 let PPC970_Unit = 3 in { // FPU Operations.
871 def FMADD : AForm_1<63, 29,
872 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
873 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
874 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
876 Requires<[FPContractions]>;
877 def FMADDS : AForm_1<59, 29,
878 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
879 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
880 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
882 Requires<[FPContractions]>;
883 def FMSUB : AForm_1<63, 28,
884 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
885 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
886 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
888 Requires<[FPContractions]>;
889 def FMSUBS : AForm_1<59, 28,
890 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
891 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
892 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
894 Requires<[FPContractions]>;
895 def FNMADD : AForm_1<63, 31,
896 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
897 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
898 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
900 Requires<[FPContractions]>;
901 def FNMADDS : AForm_1<59, 31,
902 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
903 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
904 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
906 Requires<[FPContractions]>;
907 def FNMSUB : AForm_1<63, 30,
908 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
909 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
910 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
912 Requires<[FPContractions]>;
913 def FNMSUBS : AForm_1<59, 30,
914 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
915 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
916 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
918 Requires<[FPContractions]>;
919 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
920 // having 4 of these, force the comparison to always be an 8-byte double (code
921 // should use an FMRSD if the input comparison value really wants to be a float)
922 // and 4/8 byte forms for the result and operand type..
923 def FSELD : AForm_1<63, 23,
924 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
925 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
926 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
927 def FSELS : AForm_1<63, 23,
928 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
929 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
930 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
931 def FADD : AForm_2<63, 21,
932 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
933 "fadd $FRT, $FRA, $FRB", FPGeneral,
934 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
935 def FADDS : AForm_2<59, 21,
936 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
937 "fadds $FRT, $FRA, $FRB", FPGeneral,
938 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
939 def FDIV : AForm_2<63, 18,
940 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
941 "fdiv $FRT, $FRA, $FRB", FPDivD,
942 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
943 def FDIVS : AForm_2<59, 18,
944 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
945 "fdivs $FRT, $FRA, $FRB", FPDivS,
946 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
947 def FMUL : AForm_3<63, 25,
948 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
949 "fmul $FRT, $FRA, $FRB", FPFused,
950 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
951 def FMULS : AForm_3<59, 25,
952 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
953 "fmuls $FRT, $FRA, $FRB", FPGeneral,
954 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
955 def FSUB : AForm_2<63, 20,
956 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
957 "fsub $FRT, $FRA, $FRB", FPGeneral,
958 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
959 def FSUBS : AForm_2<59, 20,
960 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
961 "fsubs $FRT, $FRA, $FRB", FPGeneral,
962 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
965 let PPC970_Unit = 1 in { // FXU Operations.
966 // M-Form instructions. rotate and mask instructions.
968 let isTwoAddress = 1, isCommutable = 1 in {
969 // RLWIMI can be commuted if the rotate amount is zero.
970 def RLWIMI : MForm_2<20,
971 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
972 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
973 []>, PPC970_DGroup_Cracked;
975 def RLWINM : MForm_2<21,
976 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
977 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
979 def RLWINMo : MForm_2<21,
980 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
981 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
982 []>, isDOT, PPC970_DGroup_Cracked;
983 def RLWNM : MForm_2<23,
984 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
985 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
990 //===----------------------------------------------------------------------===//
991 // DWARF Pseudo Instructions
994 def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
995 "${:comment} .loc $file, $line, $col",
996 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
999 def DWARF_LABEL : Pseudo<(ops i32imm:$id),
1000 "\n${:private}debug_loc$id:",
1001 [(dwarf_label (i32 imm:$id))]>;
1003 //===----------------------------------------------------------------------===//
1004 // PowerPC Instruction Patterns
1007 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1008 def : Pat<(i32 imm:$imm),
1009 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1011 // Implement the 'not' operation with the NOR instruction.
1012 def NOT : Pat<(not GPRC:$in),
1013 (NOR GPRC:$in, GPRC:$in)>;
1015 // ADD an arbitrary immediate.
1016 def : Pat<(add GPRC:$in, imm:$imm),
1017 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1018 // OR an arbitrary immediate.
1019 def : Pat<(or GPRC:$in, imm:$imm),
1020 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1021 // XOR an arbitrary immediate.
1022 def : Pat<(xor GPRC:$in, imm:$imm),
1023 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1025 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1026 (SUBFIC GPRC:$in, imm:$imm)>;
1028 // Return void support.
1029 def : Pat<(ret), (BLR)>;
1032 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1033 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1034 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1035 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1038 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1039 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1040 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1041 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1044 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1045 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1048 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
1049 (BL tglobaladdr:$dst)>;
1050 def : Pat<(PPCcall (i32 texternalsym:$dst)),
1051 (BL texternalsym:$dst)>;
1053 // Hi and Lo for Darwin Global Addresses.
1054 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1055 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1056 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1057 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1058 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1059 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1060 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1061 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1062 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1063 (ADDIS GPRC:$in, tconstpool:$g)>;
1064 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1065 (ADDIS GPRC:$in, tjumptable:$g)>;
1067 // Fused negative multiply subtract, alternate pattern
1068 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1069 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1070 Requires<[FPContractions]>;
1071 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1072 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1073 Requires<[FPContractions]>;
1075 // Standard shifts. These are represented separately from the real shifts above
1076 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1078 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1079 (SRAW GPRC:$rS, GPRC:$rB)>;
1080 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1081 (SRW GPRC:$rS, GPRC:$rB)>;
1082 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1083 (SLW GPRC:$rS, GPRC:$rB)>;
1085 def : Pat<(zextloadi1 iaddr:$src),
1087 def : Pat<(zextloadi1 xaddr:$src),
1089 def : Pat<(extloadi1 iaddr:$src),
1091 def : Pat<(extloadi1 xaddr:$src),
1093 def : Pat<(extloadi8 iaddr:$src),
1095 def : Pat<(extloadi8 xaddr:$src),
1097 def : Pat<(extloadi16 iaddr:$src),
1099 def : Pat<(extloadi16 xaddr:$src),
1101 def : Pat<(extloadf32 iaddr:$src),
1102 (FMRSD (LFS iaddr:$src))>;
1103 def : Pat<(extloadf32 xaddr:$src),
1104 (FMRSD (LFSX xaddr:$src))>;
1106 include "PPCInstrAltivec.td"
1107 include "PPCInstr64Bit.td"