1 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PowerPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // Selection DAG Type Constraint definitions.
20 // Note that the semantics of these constraints are hard coded into tblgen. To
21 // modify or add constraints, you have to hack tblgen.
24 class SDTypeConstraint<int opnum> {
25 int OperandNum = opnum;
28 // SDTCisVT - The specified operand has exactly this VT.
29 class SDTCisVT <int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP <int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 //===----------------------------------------------------------------------===//
51 // Selection DAG Type Profile definitions.
53 // These use the constraints defined above to describe the type requirements of
54 // the various nodes. These are not hard coded into tblgen, allowing targets to
55 // add their own if needed.
58 // SDTypeProfile - This profile describes the type requirements of a Selection
60 class SDTypeProfile<int numresults, int numoperands,
61 list<SDTypeConstraint> constraints> {
62 int NumResults = numresults;
63 int NumOperands = numoperands;
64 list<SDTypeConstraint> Constraints = constraints;
68 def SDTImm : SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
69 def SDTVT : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'
70 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
71 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
73 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
74 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
76 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
77 SDTCisSameAs<0, 1>, SDTCisInt<0>
79 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
80 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
81 SDTCisVTSmallerThanOp<2, 1>
84 //===----------------------------------------------------------------------===//
85 // Selection DAG Node Properties.
87 // Note: These are hard coded into tblgen.
90 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
91 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
93 //===----------------------------------------------------------------------===//
94 // Selection DAG Node definitions.
96 class SDNode<string opcode, SDTypeProfile typeprof,
97 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
98 string Opcode = opcode;
99 string SDClass = sdclass;
100 list<SDNodeProperty> Properties = props;
101 SDTypeProfile TypeProfile = typeprof;
107 def imm : SDNode<"ISD::Constant" , SDTImm , [], "ConstantSDNode">;
108 def vt : SDNode<"ISD::VALUETYPE" , SDTVT , [], "VTSDNode">;
109 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
110 [SDNPCommutative, SDNPAssociative]>;
111 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
112 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
113 [SDNPCommutative, SDNPAssociative]>;
114 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
115 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
116 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
117 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
118 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
119 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
120 def and : SDNode<"ISD::AND" , SDTIntBinOp,
121 [SDNPCommutative, SDNPAssociative]>;
122 def or : SDNode<"ISD::OR" , SDTIntBinOp,
123 [SDNPCommutative, SDNPAssociative]>;
124 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
125 [SDNPCommutative, SDNPAssociative]>;
126 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
127 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
128 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
129 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
130 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
132 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
133 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
135 //===----------------------------------------------------------------------===//
136 // Selection DAG Node Transformation Functions.
138 // This mechanism allows targets to manipulate nodes in the output DAG once a
139 // match has been formed. This is typically used to manipulate immediate
142 class SDNodeXForm<SDNode opc, code xformFunction> {
144 code XFormFunction = xformFunction;
147 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
150 //===----------------------------------------------------------------------===//
151 // Selection DAG Pattern Fragments.
153 // Pattern fragments are reusable chunks of dags that match specific things.
154 // They can take arguments and have C++ predicates that control whether they
155 // match. They are intended to make the patterns for common instructions more
156 // compact and readable.
159 /// PatFrag - Represents a pattern fragment. This can match something on the
160 /// DAG, frame a single node to multiply nested other fragments.
162 class PatFrag<dag ops, dag frag, code pred = [{}],
163 SDNodeXForm xform = NOOP_SDNodeXForm> {
166 code Predicate = pred;
167 SDNodeXForm OperandTransform = xform;
170 // PatLeaf's are pattern fragments that have no operands. This is just a helper
171 // to define immediates and other common things concisely.
172 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
173 : PatFrag<(ops), frag, pred, xform>;
177 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
178 def immZero : PatLeaf<(imm), [{ return N->isNullValue(); }]>;
180 def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
181 def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
183 // Other helper fragments.
185 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
186 def ineg : PatFrag<(ops node:$in), (sub immZero, node:$in)>;
188 //===----------------------------------------------------------------------===//
189 // Selection DAG Pattern Support.
191 // Patterns are what are actually matched against the target-flavored
192 // instruction selection DAG. Instructions defined by the target implicitly
193 // define patterns in most cases, but patterns can also be explicitly added when
194 // an operation is defined by a sequence of instructions (e.g. loading a large
195 // immediate value on RISC targets that do not support immediates as large as
199 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
200 dag PatternToMatch = patternToMatch;
201 list<dag> ResultInstrs = resultInstrs;
204 // Pat - A simple (but common) form of a pattern, which produces a simple result
205 // not needing a full list.
206 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
208 //===----------------------------------------------------------------------===//
209 // PowerPC specific transformation functions and pattern fragments.
211 def LO16 : SDNodeXForm<imm, [{
212 // Transformation function: get the low 16 bits.
213 return getI32Imm((unsigned short)N->getValue());
216 def HI16 : SDNodeXForm<imm, [{
217 // Transformation function: shift the immediate value down into the low bits.
218 return getI32Imm((unsigned)N->getValue() >> 16);
221 def immSExt16 : PatLeaf<(imm), [{
222 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
223 // field. Used by instructions like 'addi'.
224 return (int)N->getValue() == (short)N->getValue();
226 def immZExt16 : PatLeaf<(imm), [{
227 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
228 // field. Used by instructions like 'ori'.
229 return (unsigned)N->getValue() == (unsigned short)N->getValue();
232 def imm16Shifted : PatLeaf<(imm), [{
233 // imm16Shifted predicate - True if only bits in the top 16-bits of the
234 // immediate are set. Used by instructions like 'addis'.
235 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
239 // Example of a legalize expander: Only for PPC64.
240 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
241 [(set f64:$tmp , (FCTIDZ f64:$src)),
242 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
243 (store f64:$tmp, i32:$tmpFI),
244 (set i64:$dst, (load i32:$tmpFI))],
248 //===----------------------------------------------------------------------===//
249 // PowerPC Flag Definitions.
251 class isPPC64 { bit PPC64 = 1; }
252 class isVMX { bit VMX = 1; }
254 list<Register> Defs = [CR0];
260 //===----------------------------------------------------------------------===//
261 // PowerPC Operand Definitions.
263 def u5imm : Operand<i32> {
264 let PrintMethod = "printU5ImmOperand";
266 def u6imm : Operand<i32> {
267 let PrintMethod = "printU6ImmOperand";
269 def s16imm : Operand<i32> {
270 let PrintMethod = "printS16ImmOperand";
272 def u16imm : Operand<i32> {
273 let PrintMethod = "printU16ImmOperand";
275 def target : Operand<i32> {
276 let PrintMethod = "printBranchOperand";
278 def piclabel: Operand<i32> {
279 let PrintMethod = "printPICLabel";
281 def symbolHi: Operand<i32> {
282 let PrintMethod = "printSymbolHi";
284 def symbolLo: Operand<i32> {
285 let PrintMethod = "printSymbolLo";
287 def crbitm: Operand<i8> {
288 let PrintMethod = "printcrbitm";
293 //===----------------------------------------------------------------------===//
294 // PowerPC Instruction Definitions.
296 // Pseudo-instructions:
297 def PHI : Pseudo<(ops variable_ops), "; PHI">;
300 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN">;
301 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP">;
303 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
304 def IMPLICIT_DEF_FP : Pseudo<(ops FPRC:$rD), "; %rD = IMPLICIT_DEF_FP">;
306 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
307 // scheduler into a branch sequence.
308 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
309 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
310 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
311 def SELECT_CC_FP : Pseudo<(ops FPRC:$dst, CRRC:$cond, FPRC:$T, FPRC:$F,
312 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
316 let isTerminator = 1 in {
318 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">;
319 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">;
323 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
325 let isBranch = 1, isTerminator = 1 in {
326 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
327 target:$true, target:$false),
329 def B : IForm<18, 0, 0, (ops target:$func), "b $func">;
330 //def BA : IForm<18, 1, 0, (ops target:$func), "ba $func">;
331 def BL : IForm<18, 0, 1, (ops target:$func), "bl $func">;
332 //def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func">;
334 // FIXME: 4*CR# needs to be added to the BI field!
335 // This will only work for CR0 as it stands now
336 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
338 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
340 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
342 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
344 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
346 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
351 // All calls clobber the non-callee saved registers...
352 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
353 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
355 CR0,CR1,CR5,CR6,CR7] in {
356 // Convenient aliases for call instructions
357 def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops), "bl $func">;
358 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1,
359 (ops variable_ops), "bctrl">;
362 // D-Form instructions. Most instructions that perform an operation on a
363 // register and an immediate are of this type.
366 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
367 "lbz $rD, $disp($rA)">;
368 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
369 "lha $rD, $disp($rA)">;
370 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
371 "lhz $rD, $disp($rA)">;
372 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
373 "lmw $rD, $disp($rA)">;
374 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
375 "lwz $rD, $disp($rA)">;
376 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
377 "lwzu $rD, $disp($rA)">;
379 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
380 "addi $rD, $rA, $imm",
381 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
382 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
383 "addic $rD, $rA, $imm",
385 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
386 "addic. $rD, $rA, $imm",
388 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
389 "addis $rD, $rA, $imm",
390 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
391 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
394 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
395 "mulli $rD, $rA, $imm",
396 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
397 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
398 "subfic $rD, $rA, $imm",
400 def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
402 [(set GPRC:$rD, immSExt16:$imm)]>;
403 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
405 [(set GPRC:$rD, imm16Shifted:$imm)]>;
407 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
408 "stmw $rS, $disp($rA)">;
409 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
410 "stb $rS, $disp($rA)">;
411 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
412 "sth $rS, $disp($rA)">;
413 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
414 "stw $rS, $disp($rA)">;
415 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
416 "stwu $rS, $disp($rA)">;
418 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
419 "andi. $dst, $src1, $src2",
421 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
422 "andis. $dst, $src1, $src2",
424 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
425 "ori $dst, $src1, $src2",
426 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
427 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
428 "oris $dst, $src1, $src2",
429 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
430 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
431 "xori $dst, $src1, $src2",
432 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
433 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
434 "xoris $dst, $src1, $src2",
435 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
436 def NOP : DForm_4_zero<24, (ops), "nop">;
437 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
438 "cmpi $crD, $L, $rA, $imm">;
439 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
440 "cmpwi $crD, $rA, $imm">;
441 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
442 "cmpdi $crD, $rA, $imm">, isPPC64;
443 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
444 "cmpli $dst, $size, $src1, $src2">;
445 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
446 "cmplwi $dst, $src1, $src2">;
447 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
448 "cmpldi $dst, $src1, $src2">, isPPC64;
450 def LFS : DForm_8<48, (ops FPRC:$rD, symbolLo:$disp, GPRC:$rA),
451 "lfs $rD, $disp($rA)">;
452 def LFD : DForm_8<50, (ops FPRC:$rD, symbolLo:$disp, GPRC:$rA),
453 "lfd $rD, $disp($rA)">;
456 def STFS : DForm_9<52, (ops FPRC:$rS, symbolLo:$disp, GPRC:$rA),
457 "stfs $rS, $disp($rA)">;
458 def STFD : DForm_9<54, (ops FPRC:$rS, symbolLo:$disp, GPRC:$rA),
459 "stfd $rS, $disp($rA)">;
462 // DS-Form instructions. Load/Store instructions available in PPC-64
465 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
466 "lwa $rT, $DS($rA)">, isPPC64;
467 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
468 "ld $rT, $DS($rA)">, isPPC64;
471 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
472 "std $rT, $DS($rA)">, isPPC64;
473 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
474 "stdu $rT, $DS($rA)">, isPPC64;
477 // X-Form instructions. Most instructions that perform an operation on a
478 // register and another register are of this type.
481 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
482 "lbzx $dst, $base, $index">;
483 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
484 "lhax $dst, $base, $index">;
485 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
486 "lhzx $dst, $base, $index">;
487 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
488 "lwax $dst, $base, $index">, isPPC64;
489 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
490 "lwzx $dst, $base, $index">;
491 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
492 "ldx $dst, $base, $index">, isPPC64;
494 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
495 "nand $rA, $rS, $rB",
496 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
497 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
499 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
500 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
501 "and. $rA, $rS, $rB",
503 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
504 "andc $rA, $rS, $rB",
505 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
506 def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
508 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
509 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
511 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
512 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
515 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
517 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
518 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
520 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
521 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
523 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
524 def SLD : XForm_6<31, 27, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
527 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
530 def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
533 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
536 def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
537 "srad $rA, $rS, $rB",
539 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
540 "sraw $rA, $rS, $rB",
543 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
544 "stbx $rS, $rA, $rB">;
545 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
546 "sthx $rS, $rA, $rB">;
547 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
548 "stwx $rS, $rA, $rB">;
549 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
550 "stwux $rS, $rA, $rB">;
551 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
552 "stdx $rS, $rA, $rB">, isPPC64;
553 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
554 "stdux $rS, $rA, $rB">, isPPC64;
556 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
557 "srawi $rA, $rS, $SH">;
558 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
560 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
561 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
563 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
564 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
566 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
567 def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
570 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
571 "cmp $crD, $long, $rA, $rB">;
572 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
573 "cmpl $crD, $long, $rA, $rB">;
574 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
575 "cmpw $crD, $rA, $rB">;
576 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
577 "cmpd $crD, $rA, $rB">, isPPC64;
578 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
579 "cmplw $crD, $rA, $rB">;
580 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
581 "cmpld $crD, $rA, $rB">, isPPC64;
582 def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
583 "fcmpo $crD, $fA, $fB">;
584 def FCMPU : XForm_17<63, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
585 "fcmpu $crD, $fA, $fB">;
587 def LFSX : XForm_25<31, 535, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
588 "lfsx $dst, $base, $index">;
589 def LFDX : XForm_25<31, 599, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
590 "lfdx $dst, $base, $index">;
592 def FCFID : XForm_26<63, 846, (ops FPRC:$frD, FPRC:$frB),
593 "fcfid $frD, $frB">, isPPC64;
594 def FCTIDZ : XForm_26<63, 815, (ops FPRC:$frD, FPRC:$frB),
595 "fctidz $frD, $frB">, isPPC64;
596 def FCTIWZ : XForm_26<63, 15, (ops FPRC:$frD, FPRC:$frB),
597 "fctiwz $frD, $frB">;
598 def FABS : XForm_26<63, 264, (ops FPRC:$frD, FPRC:$frB),
600 def FMR : XForm_26<63, 72, (ops FPRC:$frD, FPRC:$frB),
602 def FNABS : XForm_26<63, 136, (ops FPRC:$frD, FPRC:$frB),
604 def FNEG : XForm_26<63, 40, (ops FPRC:$frD, FPRC:$frB),
606 def FRSP : XForm_26<63, 12, (ops FPRC:$frD, FPRC:$frB),
608 def FSQRT : XForm_26<63, 22, (ops FPRC:$frD, FPRC:$frB),
610 def FSQRTS : XForm_26<59, 22, (ops FPRC:$frD, FPRC:$frB),
611 "fsqrts $frD, $frB">;
614 def STFSX : XForm_28<31, 663, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
615 "stfsx $frS, $rA, $rB">;
616 def STFDX : XForm_28<31, 727, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
617 "stfdx $frS, $rA, $rB">;
620 // XL-Form instructions. condition register logical ops.
622 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
625 // XFX-Form instructions. Instructions that deal with SPRs
627 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
628 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
629 // which means the SPR value needs to be multiplied by a factor of 32.
630 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT">;
631 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT">;
632 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">;
633 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
635 def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
637 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">;
638 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;
640 // XS-Form instructions. Just 'sradi'
642 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
643 "sradi $rA, $rS, $SH">, isPPC64;
645 // XO-Form instructions. Arithmetic instructions that can set overflow bit
647 def ADD : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
649 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
650 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
651 "addc $rT, $rA, $rB",
653 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
654 "adde $rT, $rA, $rB",
656 def DIVD : XOForm_1<31, 489, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
657 "divd $rT, $rA, $rB",
659 def DIVDU : XOForm_1<31, 457, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
660 "divdu $rT, $rA, $rB",
662 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
663 "divw $rT, $rA, $rB",
664 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
665 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
666 "divwu $rT, $rA, $rB",
667 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
668 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
669 "mulhw $rT, $rA, $rB",
670 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
671 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
672 "mulhwu $rT, $rA, $rB",
673 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
674 def MULLD : XOForm_1<31, 233, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
675 "mulld $rT, $rA, $rB",
677 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
678 "mullw $rT, $rA, $rB",
679 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
680 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
681 "subf $rT, $rA, $rB",
682 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
683 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
684 "subfc $rT, $rA, $rB",
686 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
687 "subfe $rT, $rA, $rB",
689 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
692 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
695 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
697 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
698 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
702 // A-Form instructions. Most of the instructions executed in the FPU are of
705 def FMADD : AForm_1<63, 29,
706 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
707 "fmadd $FRT, $FRA, $FRC, $FRB">;
708 def FMADDS : AForm_1<59, 29,
709 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
710 "fmadds $FRT, $FRA, $FRC, $FRB">;
711 def FMSUB : AForm_1<63, 28,
712 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
713 "fmsub $FRT, $FRA, $FRC, $FRB">;
714 def FMSUBS : AForm_1<59, 28,
715 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
716 "fmsubs $FRT, $FRA, $FRC, $FRB">;
717 def FNMADD : AForm_1<63, 31,
718 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
719 "fnmadd $FRT, $FRA, $FRC, $FRB">;
720 def FNMADDS : AForm_1<59, 31,
721 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
722 "fnmadds $FRT, $FRA, $FRC, $FRB">;
723 def FNMSUB : AForm_1<63, 30,
724 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
725 "fnmsub $FRT, $FRA, $FRC, $FRB">;
726 def FNMSUBS : AForm_1<59, 30,
727 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
728 "fnmsubs $FRT, $FRA, $FRC, $FRB">;
729 def FSEL : AForm_1<63, 23,
730 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
731 "fsel $FRT, $FRA, $FRC, $FRB">;
732 def FADD : AForm_2<63, 21,
733 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
734 "fadd $FRT, $FRA, $FRB">;
735 def FADDS : AForm_2<59, 21,
736 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
737 "fadds $FRT, $FRA, $FRB">;
738 def FDIV : AForm_2<63, 18,
739 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
740 "fdiv $FRT, $FRA, $FRB">;
741 def FDIVS : AForm_2<59, 18,
742 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
743 "fdivs $FRT, $FRA, $FRB">;
744 def FMUL : AForm_3<63, 25,
745 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
746 "fmul $FRT, $FRA, $FRB">;
747 def FMULS : AForm_3<59, 25,
748 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
749 "fmuls $FRT, $FRA, $FRB">;
750 def FSUB : AForm_2<63, 20,
751 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
752 "fsub $FRT, $FRA, $FRB">;
753 def FSUBS : AForm_2<59, 20,
754 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
755 "fsubs $FRT, $FRA, $FRB">;
757 // M-Form instructions. rotate and mask instructions.
759 let isTwoAddress = 1, isCommutable = 1 in {
760 // RLWIMI can be commuted if the rotate amount is zero.
761 def RLWIMI : MForm_2<20,
762 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
763 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
765 def RLWINM : MForm_2<21,
766 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
767 "rlwinm $rA, $rS, $SH, $MB, $ME">;
768 def RLWINMo : MForm_2<21,
769 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
770 "rlwinm. $rA, $rS, $SH, $MB, $ME">, isDOT;
771 def RLWNM : MForm_2<23,
772 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
773 "rlwnm $rA, $rS, $rB, $MB, $ME">;
775 // MD-Form instructions. 64 bit rotate instructions.
777 def RLDICL : MDForm_1<30, 0,
778 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
779 "rldicl $rA, $rS, $SH, $MB">, isPPC64;
780 def RLDICR : MDForm_1<30, 1,
781 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
782 "rldicr $rA, $rS, $SH, $ME">, isPPC64;
784 //===----------------------------------------------------------------------===//
785 // PowerPC Instruction Patterns
788 // Arbitrary immediate support. Implement in terms of LIS/ORI.
789 def : Pat<(i32 imm:$imm),
790 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
793 // Implement the 'not' operation with the NOR instruction.
794 def NOT : Pat<(not GPRC:$in),
795 (NOR GPRC:$in, GPRC:$in)>;
798 def EQV1 : Pat<(xor (not GPRC:$in1), GPRC:$in2),
799 (EQV GPRC:$in1, GPRC:$in2)>;
800 // FIXME: This should be autogenerated from the above due to xor commutativity.
801 def EQV2 : Pat<(xor GPRC:$in1, (not GPRC:$in2)),
802 (EQV GPRC:$in1, GPRC:$in2)>;
804 // or by an arbitrary immediate.
805 def : Pat<(or GPRC:$in, imm:$imm),
806 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
807 // xor by an arbitrary immediate.
808 def : Pat<(xor GPRC:$in, imm:$imm),
809 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
813 // Same as above, but using a temporary. FIXME: implement temporaries :)
815 def : Pattern<(xor GPRC:$in, imm:$imm),
816 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
817 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
821 //===----------------------------------------------------------------------===//
822 // PowerPCInstrInfo Definition
824 def PowerPCInstrInfo : InstrInfo {
827 let TSFlagsFields = [ "VMX", "PPC64" ];
828 let TSFlagsShifts = [ 0, 1 ];
830 let isLittleEndianEncoding = 1;