1 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PowerPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // Selection DAG Type Constraint definitions.
20 // Note that the semantics of these constraints are hard coded into tblgen. To
21 // modify or add constraints, you have to hack tblgen.
24 class SDTypeConstraint<int opnum> {
25 int OperandNum = opnum;
28 // SDTCisVT - The specified operand has exactly this VT.
29 class SDTCisVT <int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP <int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 //===----------------------------------------------------------------------===//
51 // Selection DAG Type Profile definitions.
53 // These use the constraints defined above to describe the type requirements of
54 // the various nodes. These are not hard coded into tblgen, allowing targets to
55 // add their own if needed.
58 // SDTypeProfile - This profile describes the type requirements of a Selection
60 class SDTypeProfile<int numresults, int numoperands,
61 list<SDTypeConstraint> constraints> {
62 int NumResults = numresults;
63 int NumOperands = numoperands;
64 list<SDTypeConstraint> Constraints = constraints;
68 def SDTImm : SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
69 def SDTVT : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'
70 def SDTBinOp : SDTypeProfile<1, 2, [ // add, mul, etc.
71 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
73 def SDTIntBinOp : SDTypeProfile<1, 2, [ // and, or, xor, udiv, etc.
74 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
76 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
77 SDTCisSameAs<0, 1>, SDTCisInt<0>
79 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
80 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
81 SDTCisVTSmallerThanOp<2, 1>
85 //===----------------------------------------------------------------------===//
86 // Selection DAG Node definitions.
88 class SDNode<string opcode, SDTypeProfile typeprof, string sdclass = "SDNode"> {
89 string Opcode = opcode;
90 string SDClass = sdclass;
91 SDTypeProfile TypeProfile = typeprof;
97 def imm : SDNode<"ISD::Constant" , SDTImm , "ConstantSDNode">;
98 def vt : SDNode<"ISD::VALUETYPE" , SDTVT , "VTSDNode">;
99 def and : SDNode<"ISD::AND" , SDTIntBinOp>;
100 def or : SDNode<"ISD::OR" , SDTIntBinOp>;
101 def xor : SDNode<"ISD::XOR" , SDTIntBinOp>;
102 def add : SDNode<"ISD::ADD" , SDTBinOp>;
103 def sub : SDNode<"ISD::SUB" , SDTBinOp>;
104 def mul : SDNode<"ISD::MUL" , SDTBinOp>;
105 def sdiv : SDNode<"ISD::SDIV" , SDTBinOp>;
106 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
107 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp>;
108 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp>;
109 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
110 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
112 //===----------------------------------------------------------------------===//
113 // Selection DAG Node Transformation Functions.
115 // This mechanism allows targets to manipulate nodes in the output DAG once a
116 // match has been formed. This is typically used to manipulate immediate
119 class SDNodeXForm<SDNode opc, code xformFunction> {
121 code XFormFunction = xformFunction;
124 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
127 //===----------------------------------------------------------------------===//
128 // Selection DAG Pattern Fragments.
130 // Pattern fragments are reusable chunks of dags that match specific things.
131 // They can take arguments and have C++ predicates that control whether they
132 // match. They are intended to make the patterns for common instructions more
133 // compact and readable.
136 /// PatFrag - Represents a pattern fragment. This can match something on the
137 /// DAG, frame a single node to multiply nested other fragments.
139 class PatFrag<dag ops, dag frag, code pred = [{}],
140 SDNodeXForm xform = NOOP_SDNodeXForm> {
143 code Predicate = pred;
144 SDNodeXForm OperandTransform = xform;
147 // PatLeaf's are pattern fragments that have no operands. This is just a helper
148 // to define immediates and other common things concisely.
149 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
150 : PatFrag<(ops), frag, pred, xform>;
154 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
155 def immZero : PatLeaf<(imm), [{ return N->isNullValue(); }]>;
157 def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
158 def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
160 // Other helper fragments.
162 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
163 def ineg : PatFrag<(ops node:$in), (sub immZero, node:$in)>;
165 //===----------------------------------------------------------------------===//
166 // Selection DAG Pattern Support.
168 // Patterns are what are actually matched against the target-flavored
169 // instruction selection DAG. Instructions defined by the target implicitly
170 // define patterns in most cases, but patterns can also be explicitly added when
171 // an operation is defined by a sequence of instructions (e.g. loading a large
172 // immediate value on RISC targets that do not support immediates as large as
176 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
177 dag PatternToMatch = patternToMatch;
178 list<dag> ResultInstrs = resultInstrs;
181 // Pat - A simple (but common) form of a pattern, which produces a simple result
182 // not needing a full list.
183 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
186 //===----------------------------------------------------------------------===//
187 // PowerPC specific transformation functions and pattern fragments.
189 def LO16 : SDNodeXForm<imm, [{
190 // Transformation function: get the low 16 bits.
191 return getI32Imm((unsigned short)N->getValue());
194 def HI16 : SDNodeXForm<imm, [{
195 // Transformation function: shift the immediate value down into the low bits.
196 return getI32Imm((unsigned)N->getValue() >> 16);
199 def immSExt16 : PatLeaf<(imm), [{
200 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
201 // field. Used by instructions like 'addi'.
202 return (int)N->getValue() == (short)N->getValue();
204 def immZExt16 : PatLeaf<(imm), [{
205 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
206 // field. Used by instructions like 'ori'.
207 return (unsigned)N->getValue() == (unsigned short)N->getValue();
210 def imm16Shifted : PatLeaf<(imm), [{
211 // imm16Shifted predicate - True if only bits in the top 16-bits of the
212 // immediate are set. Used by instructions like 'addis'.
213 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
217 // Example of a legalize expander: Only for PPC64.
218 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
219 [(set f64:$tmp , (FCTIDZ f64:$src)),
220 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
221 (store f64:$tmp, i32:$tmpFI),
222 (set i64:$dst, (load i32:$tmpFI))],
226 //===----------------------------------------------------------------------===//
227 // PowerPC Flag Definitions.
229 class isPPC64 { bit PPC64 = 1; }
230 class isVMX { bit VMX = 1; }
232 list<Register> Defs = [CR0];
238 //===----------------------------------------------------------------------===//
239 // PowerPC Operand Definitions.
241 def u5imm : Operand<i8> {
242 let PrintMethod = "printU5ImmOperand";
244 def u6imm : Operand<i8> {
245 let PrintMethod = "printU6ImmOperand";
247 def s16imm : Operand<i16> {
248 let PrintMethod = "printS16ImmOperand";
250 def u16imm : Operand<i16> {
251 let PrintMethod = "printU16ImmOperand";
253 def target : Operand<i32> {
254 let PrintMethod = "printBranchOperand";
256 def piclabel: Operand<i32> {
257 let PrintMethod = "printPICLabel";
259 def symbolHi: Operand<i32> {
260 let PrintMethod = "printSymbolHi";
262 def symbolLo: Operand<i32> {
263 let PrintMethod = "printSymbolLo";
265 def crbitm: Operand<i8> {
266 let PrintMethod = "printcrbitm";
271 //===----------------------------------------------------------------------===//
272 // PowerPC Instruction Definitions.
274 // Pseudo-instructions:
275 def PHI : Pseudo<(ops variable_ops), "; PHI">;
278 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm), "; ADJCALLSTACKDOWN">;
279 def ADJCALLSTACKUP : Pseudo<(ops u16imm), "; ADJCALLSTACKUP">;
281 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
282 def IMPLICIT_DEF_FP : Pseudo<(ops FPRC:$rD), "; %rD = IMPLICIT_DEF_FP">;
284 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
285 // scheduler into a branch sequence.
286 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
287 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
288 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
289 def SELECT_CC_FP : Pseudo<(ops FPRC:$dst, CRRC:$cond, FPRC:$T, FPRC:$F,
290 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
294 let isTerminator = 1 in {
296 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">;
297 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">;
301 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
303 let isBranch = 1, isTerminator = 1 in {
304 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm, target:$true, target:$false),
306 def B : IForm<18, 0, 0, (ops target:$func), "b $func">;
307 //def BA : IForm<18, 1, 0, (ops target:$func), "ba $func">;
308 def BL : IForm<18, 0, 1, (ops target:$func), "bl $func">;
309 //def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func">;
311 // FIXME: 4*CR# needs to be added to the BI field!
312 // This will only work for CR0 as it stands now
313 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
315 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
317 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
319 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
321 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
323 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
328 // All calls clobber the non-callee saved registers...
329 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
330 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
332 CR0,CR1,CR5,CR6,CR7] in {
333 // Convenient aliases for call instructions
334 def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops), "bl $func">;
335 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1,
336 (ops variable_ops), "bctrl">;
339 // D-Form instructions. Most instructions that perform an operation on a
340 // register and an immediate are of this type.
343 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
344 "lbz $rD, $disp($rA)">;
345 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
346 "lha $rD, $disp($rA)">;
347 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
348 "lhz $rD, $disp($rA)">;
349 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
350 "lmw $rD, $disp($rA)">;
351 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
352 "lwz $rD, $disp($rA)">;
353 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
354 "lwzu $rD, $disp($rA)">;
356 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
357 "addi $rD, $rA, $imm",
358 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
359 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
360 "addic $rD, $rA, $imm",
362 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
363 "addic. $rD, $rA, $imm",
365 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
366 "addis $rD, $rA, $imm",
367 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
368 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
371 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
372 "mulli $rD, $rA, $imm",
373 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
374 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
375 "subfic $rD, $rA, $imm",
377 def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
379 [(set GPRC:$rD, immSExt16:$imm)]>;
380 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
382 [(set GPRC:$rD, imm16Shifted:$imm)]>;
384 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
385 "stmw $rS, $disp($rA)">;
386 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
387 "stb $rS, $disp($rA)">;
388 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
389 "sth $rS, $disp($rA)">;
390 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
391 "stw $rS, $disp($rA)">;
392 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
393 "stwu $rS, $disp($rA)">;
395 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
396 "andi. $dst, $src1, $src2",
398 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
399 "andis. $dst, $src1, $src2",
401 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
402 "ori $dst, $src1, $src2",
403 [(set GPRC:$rD, (or GPRC:$rA, immZExt16:$imm))]>;
404 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
405 "oris $dst, $src1, $src2",
406 [(set GPRC:$rD, (or GPRC:$rA, imm16Shifted:$imm))]>;
407 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
408 "xori $dst, $src1, $src2",
409 [(set GPRC:$rD, (xor GPRC:$rA, immZExt16:$imm))]>;
410 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
411 "xoris $dst, $src1, $src2",
412 [(set GPRC:$rD, (xor GPRC:$rA, imm16Shifted:$imm))]>;
413 def NOP : DForm_4_zero<24, (ops), "nop">;
414 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
415 "cmpi $crD, $L, $rA, $imm">;
416 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
417 "cmpwi $crD, $rA, $imm">;
418 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
419 "cmpdi $crD, $rA, $imm">, isPPC64;
420 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
421 "cmpli $dst, $size, $src1, $src2">;
422 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
423 "cmplwi $dst, $src1, $src2">;
424 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
425 "cmpldi $dst, $src1, $src2">, isPPC64;
427 def LFS : DForm_8<48, (ops FPRC:$rD, symbolLo:$disp, GPRC:$rA),
428 "lfs $rD, $disp($rA)">;
429 def LFD : DForm_8<50, (ops FPRC:$rD, symbolLo:$disp, GPRC:$rA),
430 "lfd $rD, $disp($rA)">;
433 def STFS : DForm_9<52, (ops FPRC:$rS, symbolLo:$disp, GPRC:$rA),
434 "stfs $rS, $disp($rA)">;
435 def STFD : DForm_9<54, (ops FPRC:$rS, symbolLo:$disp, GPRC:$rA),
436 "stfd $rS, $disp($rA)">;
439 // DS-Form instructions. Load/Store instructions available in PPC-64
442 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
443 "lwa $rT, $DS($rA)">, isPPC64;
444 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
445 "ld $rT, $DS($rA)">, isPPC64;
448 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
449 "std $rT, $DS($rA)">, isPPC64;
450 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
451 "stdu $rT, $DS($rA)">, isPPC64;
454 // X-Form instructions. Most instructions that perform an operation on a
455 // register and another register are of this type.
458 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
459 "lbzx $dst, $base, $index">;
460 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
461 "lhax $dst, $base, $index">;
462 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
463 "lhzx $dst, $base, $index">;
464 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
465 "lwax $dst, $base, $index">, isPPC64;
466 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
467 "lwzx $dst, $base, $index">;
468 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
469 "ldx $dst, $base, $index">, isPPC64;
471 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
472 "nand $rA, $rS, $rB",
473 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
474 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
476 [(set GPRC:$rT, (and GPRC:$rA, GPRC:$rB))]>;
477 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
478 "and. $rA, $rS, $rB",
480 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
481 "andc $rA, $rS, $rB",
482 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
483 def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
485 [(set GPRC:$rT, (or GPRC:$rA, GPRC:$rB))]>;
486 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
488 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
489 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
492 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
494 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
495 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
497 [(set GPRC:$rT, (not (xor GPRC:$rA, GPRC:$rB)))]>;
498 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
500 [(set GPRC:$rT, (xor GPRC:$rA, GPRC:$rB))]>;
501 def SLD : XForm_6<31, 27, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
504 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
507 def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
510 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
513 def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
514 "srad $rA, $rS, $rB",
516 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
517 "sraw $rA, $rS, $rB",
520 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
521 "stbx $rS, $rA, $rB">;
522 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
523 "sthx $rS, $rA, $rB">;
524 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
525 "stwx $rS, $rA, $rB">;
526 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
527 "stwux $rS, $rA, $rB">;
528 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
529 "stdx $rS, $rA, $rB">, isPPC64;
530 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
531 "stdux $rS, $rA, $rB">, isPPC64;
533 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
534 "srawi $rA, $rS, $SH">;
535 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
537 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
538 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
540 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
541 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
543 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
544 def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
547 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
548 "cmp $crD, $long, $rA, $rB">;
549 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
550 "cmpl $crD, $long, $rA, $rB">;
551 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
552 "cmpw $crD, $rA, $rB">;
553 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
554 "cmpd $crD, $rA, $rB">, isPPC64;
555 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
556 "cmplw $crD, $rA, $rB">;
557 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
558 "cmpld $crD, $rA, $rB">, isPPC64;
559 def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
560 "fcmpo $crD, $fA, $fB">;
561 def FCMPU : XForm_17<63, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
562 "fcmpu $crD, $fA, $fB">;
564 def LFSX : XForm_25<31, 535, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
565 "lfsx $dst, $base, $index">;
566 def LFDX : XForm_25<31, 599, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
567 "lfdx $dst, $base, $index">;
569 def FCFID : XForm_26<63, 846, (ops FPRC:$frD, FPRC:$frB),
570 "fcfid $frD, $frB">, isPPC64;
571 def FCTIDZ : XForm_26<63, 815, (ops FPRC:$frD, FPRC:$frB),
572 "fctidz $frD, $frB">, isPPC64;
573 def FCTIWZ : XForm_26<63, 15, (ops FPRC:$frD, FPRC:$frB),
574 "fctiwz $frD, $frB">;
575 def FABS : XForm_26<63, 264, (ops FPRC:$frD, FPRC:$frB),
577 def FMR : XForm_26<63, 72, (ops FPRC:$frD, FPRC:$frB),
579 def FNABS : XForm_26<63, 136, (ops FPRC:$frD, FPRC:$frB),
581 def FNEG : XForm_26<63, 40, (ops FPRC:$frD, FPRC:$frB),
583 def FRSP : XForm_26<63, 12, (ops FPRC:$frD, FPRC:$frB),
585 def FSQRT : XForm_26<63, 22, (ops FPRC:$frD, FPRC:$frB),
587 def FSQRTS : XForm_26<59, 22, (ops FPRC:$frD, FPRC:$frB),
588 "fsqrts $frD, $frB">;
591 def STFSX : XForm_28<31, 663, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
592 "stfsx $frS, $rA, $rB">;
593 def STFDX : XForm_28<31, 727, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
594 "stfdx $frS, $rA, $rB">;
597 // XL-Form instructions. condition register logical ops.
599 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
602 // XFX-Form instructions. Instructions that deal with SPRs
604 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
605 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
606 // which means the SPR value needs to be multiplied by a factor of 32.
607 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT">;
608 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT">;
609 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">;
610 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
612 def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
614 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">;
615 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;
617 // XS-Form instructions. Just 'sradi'
619 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
620 "sradi $rA, $rS, $SH">, isPPC64;
622 // XO-Form instructions. Arithmetic instructions that can set overflow bit
624 def ADD : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
626 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
627 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
628 "addc $rT, $rA, $rB",
630 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
631 "adde $rT, $rA, $rB",
633 def DIVD : XOForm_1<31, 489, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
634 "divd $rT, $rA, $rB",
636 def DIVDU : XOForm_1<31, 457, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
637 "divdu $rT, $rA, $rB",
639 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
640 "divw $rT, $rA, $rB",
641 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
642 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
643 "divwu $rT, $rA, $rB",
644 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
645 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
646 "mulhw $rT, $rA, $rB",
647 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
648 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
649 "mulhwu $rT, $rA, $rB",
650 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
651 def MULLD : XOForm_1<31, 233, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
652 "mulld $rT, $rA, $rB",
654 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
655 "mullw $rT, $rA, $rB",
656 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
657 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
658 "subf $rT, $rA, $rB",
659 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
660 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
661 "subfc $rT, $rA, $rB",
663 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
664 "subfe $rT, $rA, $rB",
666 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
669 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
672 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
674 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
675 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
679 // A-Form instructions. Most of the instructions executed in the FPU are of
682 def FMADD : AForm_1<63, 29,
683 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
684 "fmadd $FRT, $FRA, $FRC, $FRB">;
685 def FMADDS : AForm_1<59, 29,
686 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
687 "fmadds $FRT, $FRA, $FRC, $FRB">;
688 def FMSUB : AForm_1<63, 28,
689 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
690 "fmsub $FRT, $FRA, $FRC, $FRB">;
691 def FMSUBS : AForm_1<59, 28,
692 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
693 "fmsubs $FRT, $FRA, $FRC, $FRB">;
694 def FNMADD : AForm_1<63, 31,
695 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
696 "fnmadd $FRT, $FRA, $FRC, $FRB">;
697 def FNMADDS : AForm_1<59, 31,
698 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
699 "fnmadds $FRT, $FRA, $FRC, $FRB">;
700 def FNMSUB : AForm_1<63, 30,
701 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
702 "fnmsub $FRT, $FRA, $FRC, $FRB">;
703 def FNMSUBS : AForm_1<59, 30,
704 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
705 "fnmsubs $FRT, $FRA, $FRC, $FRB">;
706 def FSEL : AForm_1<63, 23,
707 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
708 "fsel $FRT, $FRA, $FRC, $FRB">;
709 def FADD : AForm_2<63, 21,
710 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
711 "fadd $FRT, $FRA, $FRB">;
712 def FADDS : AForm_2<59, 21,
713 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
714 "fadds $FRT, $FRA, $FRB">;
715 def FDIV : AForm_2<63, 18,
716 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
717 "fdiv $FRT, $FRA, $FRB">;
718 def FDIVS : AForm_2<59, 18,
719 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
720 "fdivs $FRT, $FRA, $FRB">;
721 def FMUL : AForm_3<63, 25,
722 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
723 "fmul $FRT, $FRA, $FRB">;
724 def FMULS : AForm_3<59, 25,
725 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
726 "fmuls $FRT, $FRA, $FRB">;
727 def FSUB : AForm_2<63, 20,
728 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
729 "fsub $FRT, $FRA, $FRB">;
730 def FSUBS : AForm_2<59, 20,
731 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
732 "fsubs $FRT, $FRA, $FRB">;
734 // M-Form instructions. rotate and mask instructions.
736 let isTwoAddress = 1, isCommutable = 1 in {
737 // RLWIMI can be commuted if the rotate amount is zero.
738 def RLWIMI : MForm_2<20,
739 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
740 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
742 def RLWINM : MForm_2<21,
743 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
744 "rlwinm $rA, $rS, $SH, $MB, $ME">;
745 def RLWINMo : MForm_2<21,
746 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
747 "rlwinm. $rA, $rS, $SH, $MB, $ME">, isDOT;
748 def RLWNM : MForm_2<23,
749 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
750 "rlwnm $rA, $rS, $rB, $MB, $ME">;
752 // MD-Form instructions. 64 bit rotate instructions.
754 def RLDICL : MDForm_1<30, 0,
755 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
756 "rldicl $rA, $rS, $SH, $MB">, isPPC64;
757 def RLDICR : MDForm_1<30, 1,
758 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
759 "rldicr $rA, $rS, $SH, $ME">, isPPC64;
761 //===----------------------------------------------------------------------===//
762 // PowerPC Instruction Patterns
765 // REDUNDANT WITH INSTRUCTION DEFINITION, ONLY FOR TESTING.
766 def : Pat<(sext_inreg GPRC:$in, i8),
769 // or by an arbitrary immediate.
770 def : Pat<(or GPRC:$in, imm:$imm),
771 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
772 // xor by an arbitrary immediate.
773 def : Pat<(xor GPRC:$in, imm:$imm),
774 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
776 //===----------------------------------------------------------------------===//
777 // PowerPCInstrInfo Definition
779 def PowerPCInstrInfo : InstrInfo {
782 let TSFlagsFields = [ "VMX", "PPC64" ];
783 let TSFlagsShifts = [ 0, 1 ];
785 let isLittleEndianEncoding = 1;