1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 3, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 4, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
45 //===----------------------------------------------------------------------===//
46 // PowerPC specific DAG Nodes.
49 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
50 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
51 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
52 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
53 [SDNPHasChain, SDNPMayStore]>;
55 // This sequence is used for long double->int conversions. It changes the
56 // bits in the FPSCR which is not modelled.
57 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
59 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
60 [SDNPInFlag, SDNPOutFlag]>;
61 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
62 [SDNPInFlag, SDNPOutFlag]>;
63 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
64 [SDNPInFlag, SDNPOutFlag]>;
65 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
66 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
70 def PPCfsel : SDNode<"PPCISD::FSEL",
71 // Type constraint for fsel.
72 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
73 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
75 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
76 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
77 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
78 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
80 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
82 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
83 // amounts. These nodes are generated by the multi-precision shift code.
84 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
85 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
86 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
88 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
89 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
90 [SDNPHasChain, SDNPMayStore]>;
92 // These are target-independent nodes, but have target-specific formats.
93 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
94 [SDNPHasChain, SDNPOutFlag]>;
95 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
96 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
98 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
99 def PPCcall_Macho : SDNode<"PPCISD::CALL_Macho", SDT_PPCCall,
100 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
101 def PPCcall_ELF : SDNode<"PPCISD::CALL_ELF", SDT_PPCCall,
102 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
103 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
104 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
105 def PPCbctrl_Macho : SDNode<"PPCISD::BCTRL_Macho", SDTNone,
106 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
108 def PPCbctrl_ELF : SDNode<"PPCISD::BCTRL_ELF", SDTNone,
109 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
111 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
112 [SDNPHasChain, SDNPOptInFlag]>;
114 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
115 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
117 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
118 [SDNPHasChain, SDNPOptInFlag]>;
120 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
121 [SDNPHasChain, SDNPMayLoad]>;
122 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
123 [SDNPHasChain, SDNPMayStore]>;
125 // Instructions to support dynamic alloca.
126 def SDTDynOp : SDTypeProfile<1, 2, []>;
127 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
129 //===----------------------------------------------------------------------===//
130 // PowerPC specific transformation functions and pattern fragments.
133 def SHL32 : SDNodeXForm<imm, [{
134 // Transformation function: 31 - imm
135 return getI32Imm(31 - N->getValue());
138 def SRL32 : SDNodeXForm<imm, [{
139 // Transformation function: 32 - imm
140 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
143 def LO16 : SDNodeXForm<imm, [{
144 // Transformation function: get the low 16 bits.
145 return getI32Imm((unsigned short)N->getValue());
148 def HI16 : SDNodeXForm<imm, [{
149 // Transformation function: shift the immediate value down into the low bits.
150 return getI32Imm((unsigned)N->getValue() >> 16);
153 def HA16 : SDNodeXForm<imm, [{
154 // Transformation function: shift the immediate value down into the low bits.
155 signed int Val = N->getValue();
156 return getI32Imm((Val - (signed short)Val) >> 16);
158 def MB : SDNodeXForm<imm, [{
159 // Transformation function: get the start bit of a mask
161 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
162 return getI32Imm(mb);
165 def ME : SDNodeXForm<imm, [{
166 // Transformation function: get the end bit of a mask
168 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
169 return getI32Imm(me);
171 def maskimm32 : PatLeaf<(imm), [{
172 // maskImm predicate - True if immediate is a run of ones.
174 if (N->getValueType(0) == MVT::i32)
175 return isRunOfOnes((unsigned)N->getValue(), mb, me);
180 def immSExt16 : PatLeaf<(imm), [{
181 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
182 // field. Used by instructions like 'addi'.
183 if (N->getValueType(0) == MVT::i32)
184 return (int32_t)N->getValue() == (short)N->getValue();
186 return (int64_t)N->getValue() == (short)N->getValue();
188 def immZExt16 : PatLeaf<(imm), [{
189 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
190 // field. Used by instructions like 'ori'.
191 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
194 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
195 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
196 // identical in 32-bit mode, but in 64-bit mode, they return true if the
197 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
199 def imm16ShiftedZExt : PatLeaf<(imm), [{
200 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
201 // immediate are set. Used by instructions like 'xoris'.
202 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
205 def imm16ShiftedSExt : PatLeaf<(imm), [{
206 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
207 // immediate are set. Used by instructions like 'addis'. Identical to
208 // imm16ShiftedZExt in 32-bit mode.
209 if (N->getValue() & 0xFFFF) return false;
210 if (N->getValueType(0) == MVT::i32)
212 // For 64-bit, make sure it is sext right.
213 return N->getValue() == (uint64_t)(int)N->getValue();
217 //===----------------------------------------------------------------------===//
218 // PowerPC Flag Definitions.
220 class isPPC64 { bit PPC64 = 1; }
222 list<Register> Defs = [CR0];
226 class RegConstraint<string C> {
227 string Constraints = C;
229 class NoEncode<string E> {
230 string DisableEncoding = E;
234 //===----------------------------------------------------------------------===//
235 // PowerPC Operand Definitions.
237 def s5imm : Operand<i32> {
238 let PrintMethod = "printS5ImmOperand";
240 def u5imm : Operand<i32> {
241 let PrintMethod = "printU5ImmOperand";
243 def u6imm : Operand<i32> {
244 let PrintMethod = "printU6ImmOperand";
246 def s16imm : Operand<i32> {
247 let PrintMethod = "printS16ImmOperand";
249 def u16imm : Operand<i32> {
250 let PrintMethod = "printU16ImmOperand";
252 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
253 let PrintMethod = "printS16X4ImmOperand";
255 def target : Operand<OtherVT> {
256 let PrintMethod = "printBranchOperand";
258 def calltarget : Operand<iPTR> {
259 let PrintMethod = "printCallOperand";
261 def aaddr : Operand<iPTR> {
262 let PrintMethod = "printAbsAddrOperand";
264 def piclabel: Operand<iPTR> {
265 let PrintMethod = "printPICLabel";
267 def symbolHi: Operand<i32> {
268 let PrintMethod = "printSymbolHi";
270 def symbolLo: Operand<i32> {
271 let PrintMethod = "printSymbolLo";
273 def crbitm: Operand<i8> {
274 let PrintMethod = "printcrbitm";
277 def memri : Operand<iPTR> {
278 let PrintMethod = "printMemRegImm";
279 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
281 def memrr : Operand<iPTR> {
282 let PrintMethod = "printMemRegReg";
283 let MIOperandInfo = (ops ptr_rc, ptr_rc);
285 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
286 let PrintMethod = "printMemRegImmShifted";
287 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
290 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
291 // that doesn't matter.
292 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
293 (ops (i32 20), (i32 zero_reg))> {
294 let PrintMethod = "printPredicateOperand";
297 // Define PowerPC specific addressing mode.
298 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
299 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
300 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
301 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
303 /// This is just the offset part of iaddr, used for preinc.
304 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
306 //===----------------------------------------------------------------------===//
307 // PowerPC Instruction Predicate Definitions.
308 def FPContractions : Predicate<"!NoExcessFPPrecision">;
309 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
310 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
313 //===----------------------------------------------------------------------===//
314 // PowerPC Instruction Definitions.
316 // Pseudo-instructions:
318 let hasCtrlDep = 1 in {
319 let Defs = [R1], Uses = [R1] in {
320 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
321 "${:comment} ADJCALLSTACKDOWN",
322 [(callseq_start imm:$amt)]>;
323 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
324 "${:comment} ADJCALLSTACKUP",
325 [(callseq_end imm:$amt1, imm:$amt2)]>;
328 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
329 "UPDATE_VRSAVE $rD, $rS", []>;
332 let Defs = [R1], Uses = [R1] in
333 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi),
334 "${:comment} DYNALLOC $result, $negsize, $fpsi",
336 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
338 let isImplicitDef = 1 in {
339 def IMPLICIT_DEF_GPRC: Pseudo<(outs GPRC:$rD), (ins),
340 "${:comment}IMPLICIT_DEF_GPRC $rD",
341 [(set GPRC:$rD, (undef))]>;
342 def IMPLICIT_DEF_F8 : Pseudo<(outs F8RC:$rD), (ins),
343 "${:comment} IMPLICIT_DEF_F8 $rD",
344 [(set F8RC:$rD, (undef))]>;
345 def IMPLICIT_DEF_F4 : Pseudo<(outs F4RC:$rD), (ins),
346 "${:comment} IMPLICIT_DEF_F4 $rD",
347 [(set F4RC:$rD, (undef))]>;
350 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
351 // scheduler into a branch sequence.
352 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
353 PPC970_Single = 1 in {
354 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
355 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
357 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
358 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
360 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
361 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
363 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
364 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
366 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
367 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
371 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
372 // scavenge a register for it.
373 def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F),
374 "${:comment} SPILL_CR $cond $F", []>;
376 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
378 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
379 "b${p:cc}lr ${p:reg}", BrB,
381 let isBranch = 1, isIndirectBranch = 1 in
382 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
386 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
389 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
390 let isBarrier = 1 in {
391 def B : IForm<18, 0, 0, (outs), (ins target:$dst),
396 // BCC represents an arbitrary conditional branch on a predicate.
397 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
398 // a two-value operand where a dag node expects two operands. :(
399 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst),
400 "b${cond:cc} ${cond:reg}, $dst"
401 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
405 let isCall = 1, PPC970_Unit = 7,
406 // All calls clobber the non-callee saved registers...
407 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
408 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
409 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
412 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
413 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
414 // Convenient aliases for call instructions
415 def BL_Macho : IForm<18, 0, 1,
416 (outs), (ins calltarget:$func, variable_ops),
417 "bl $func", BrB, []>; // See Pat patterns below.
418 def BLA_Macho : IForm<18, 1, 1,
419 (outs), (ins aaddr:$func, variable_ops),
420 "bla $func", BrB, [(PPCcall_Macho (i32 imm:$func))]>;
421 def BCTRL_Macho : XLForm_2_ext<19, 528, 20, 0, 1,
422 (outs), (ins variable_ops),
424 [(PPCbctrl_Macho)]>, Requires<[In32BitMode]>;
428 let isCall = 1, PPC970_Unit = 7,
429 // All calls clobber the non-callee saved registers...
430 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
431 F0,F1,F2,F3,F4,F5,F6,F7,F8,
432 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
435 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
436 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
437 // Convenient aliases for call instructions
438 def BL_ELF : IForm<18, 0, 1,
439 (outs), (ins calltarget:$func, variable_ops),
440 "bl $func", BrB, []>; // See Pat patterns below.
441 def BLA_ELF : IForm<18, 1, 1,
442 (outs), (ins aaddr:$func, variable_ops),
444 [(PPCcall_ELF (i32 imm:$func))]>;
445 def BCTRL_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
446 (outs), (ins variable_ops),
448 [(PPCbctrl_ELF)]>, Requires<[In32BitMode]>;
451 // DCB* instructions.
452 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
453 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
454 PPC970_DGroup_Single;
455 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
456 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
457 PPC970_DGroup_Single;
458 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
459 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
460 PPC970_DGroup_Single;
461 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
462 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
463 PPC970_DGroup_Single;
464 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
465 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
466 PPC970_DGroup_Single;
467 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
468 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
469 PPC970_DGroup_Single;
470 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
471 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
472 PPC970_DGroup_Single;
473 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
474 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
475 PPC970_DGroup_Single;
477 //===----------------------------------------------------------------------===//
478 // PPC32 Load Instructions.
481 // Unindexed (r+i) Loads.
482 let isSimpleLoad = 1, PPC970_Unit = 2 in {
483 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
484 "lbz $rD, $src", LdStGeneral,
485 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
486 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
487 "lha $rD, $src", LdStLHA,
488 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
489 PPC970_DGroup_Cracked;
490 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
491 "lhz $rD, $src", LdStGeneral,
492 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
493 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
494 "lwz $rD, $src", LdStGeneral,
495 [(set GPRC:$rD, (load iaddr:$src))]>;
497 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
498 "lfs $rD, $src", LdStLFDU,
499 [(set F4RC:$rD, (load iaddr:$src))]>;
500 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
501 "lfd $rD, $src", LdStLFD,
502 [(set F8RC:$rD, (load iaddr:$src))]>;
505 // Unindexed (r+i) Loads with Update (preinc).
506 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
507 "lbzu $rD, $addr", LdStGeneral,
508 []>, RegConstraint<"$addr.reg = $ea_result">,
509 NoEncode<"$ea_result">;
511 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
512 "lhau $rD, $addr", LdStGeneral,
513 []>, RegConstraint<"$addr.reg = $ea_result">,
514 NoEncode<"$ea_result">;
516 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
517 "lhzu $rD, $addr", LdStGeneral,
518 []>, RegConstraint<"$addr.reg = $ea_result">,
519 NoEncode<"$ea_result">;
521 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
522 "lwzu $rD, $addr", LdStGeneral,
523 []>, RegConstraint<"$addr.reg = $ea_result">,
524 NoEncode<"$ea_result">;
526 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
527 "lfs $rD, $addr", LdStLFDU,
528 []>, RegConstraint<"$addr.reg = $ea_result">,
529 NoEncode<"$ea_result">;
531 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
532 "lfd $rD, $addr", LdStLFD,
533 []>, RegConstraint<"$addr.reg = $ea_result">,
534 NoEncode<"$ea_result">;
537 // Indexed (r+r) Loads.
539 let isSimpleLoad = 1, PPC970_Unit = 2 in {
540 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
541 "lbzx $rD, $src", LdStGeneral,
542 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
543 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
544 "lhax $rD, $src", LdStLHA,
545 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
546 PPC970_DGroup_Cracked;
547 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
548 "lhzx $rD, $src", LdStGeneral,
549 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
550 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
551 "lwzx $rD, $src", LdStGeneral,
552 [(set GPRC:$rD, (load xaddr:$src))]>;
555 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
556 "lhbrx $rD, $src", LdStGeneral,
557 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
558 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
559 "lwbrx $rD, $src", LdStGeneral,
560 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
562 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
563 "lfsx $frD, $src", LdStLFDU,
564 [(set F4RC:$frD, (load xaddr:$src))]>;
565 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
566 "lfdx $frD, $src", LdStLFDU,
567 [(set F8RC:$frD, (load xaddr:$src))]>;
570 //===----------------------------------------------------------------------===//
571 // PPC32 Store Instructions.
574 // Unindexed (r+i) Stores.
575 let PPC970_Unit = 2 in {
576 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
577 "stb $rS, $src", LdStGeneral,
578 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
579 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
580 "sth $rS, $src", LdStGeneral,
581 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
582 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
583 "stw $rS, $src", LdStGeneral,
584 [(store GPRC:$rS, iaddr:$src)]>;
585 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
586 "stfs $rS, $dst", LdStUX,
587 [(store F4RC:$rS, iaddr:$dst)]>;
588 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
589 "stfd $rS, $dst", LdStUX,
590 [(store F8RC:$rS, iaddr:$dst)]>;
593 // Unindexed (r+i) Stores with Update (preinc).
594 let PPC970_Unit = 2 in {
595 def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
596 symbolLo:$ptroff, ptr_rc:$ptrreg),
597 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
598 [(set ptr_rc:$ea_res,
599 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
600 iaddroff:$ptroff))]>,
601 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
602 def STHU : DForm_1<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
603 symbolLo:$ptroff, ptr_rc:$ptrreg),
604 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
605 [(set ptr_rc:$ea_res,
606 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
607 iaddroff:$ptroff))]>,
608 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
609 def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
610 symbolLo:$ptroff, ptr_rc:$ptrreg),
611 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
612 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
613 iaddroff:$ptroff))]>,
614 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
615 def STFSU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
616 symbolLo:$ptroff, ptr_rc:$ptrreg),
617 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
618 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
619 iaddroff:$ptroff))]>,
620 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
621 def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
622 symbolLo:$ptroff, ptr_rc:$ptrreg),
623 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
624 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
625 iaddroff:$ptroff))]>,
626 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
630 // Indexed (r+r) Stores.
632 let PPC970_Unit = 2 in {
633 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
634 "stbx $rS, $dst", LdStGeneral,
635 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
636 PPC970_DGroup_Cracked;
637 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
638 "sthx $rS, $dst", LdStGeneral,
639 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
640 PPC970_DGroup_Cracked;
641 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
642 "stwx $rS, $dst", LdStGeneral,
643 [(store GPRC:$rS, xaddr:$dst)]>,
644 PPC970_DGroup_Cracked;
646 let mayStore = 1 in {
647 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
648 "stwux $rS, $rA, $rB", LdStGeneral,
651 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
652 "sthbrx $rS, $dst", LdStGeneral,
653 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
654 PPC970_DGroup_Cracked;
655 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
656 "stwbrx $rS, $dst", LdStGeneral,
657 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>,
658 PPC970_DGroup_Cracked;
660 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
661 "stfiwx $frS, $dst", LdStUX,
662 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
664 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
665 "stfsx $frS, $dst", LdStUX,
666 [(store F4RC:$frS, xaddr:$dst)]>;
667 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
668 "stfdx $frS, $dst", LdStUX,
669 [(store F8RC:$frS, xaddr:$dst)]>;
673 //===----------------------------------------------------------------------===//
674 // PPC32 Arithmetic Instructions.
677 let PPC970_Unit = 1 in { // FXU Operations.
678 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
679 "addi $rD, $rA, $imm", IntGeneral,
680 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
681 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
682 "addic $rD, $rA, $imm", IntGeneral,
683 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
684 PPC970_DGroup_Cracked;
685 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
686 "addic. $rD, $rA, $imm", IntGeneral,
688 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
689 "addis $rD, $rA, $imm", IntGeneral,
690 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
691 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
692 "la $rD, $sym($rA)", IntGeneral,
693 [(set GPRC:$rD, (add GPRC:$rA,
694 (PPClo tglobaladdr:$sym, 0)))]>;
695 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
696 "mulli $rD, $rA, $imm", IntMulLI,
697 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
698 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
699 "subfic $rD, $rA, $imm", IntGeneral,
700 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
702 let isReMaterializable = 1 in {
703 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
704 "li $rD, $imm", IntGeneral,
705 [(set GPRC:$rD, immSExt16:$imm)]>;
706 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
707 "lis $rD, $imm", IntGeneral,
708 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
712 let PPC970_Unit = 1 in { // FXU Operations.
713 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
714 "andi. $dst, $src1, $src2", IntGeneral,
715 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
717 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
718 "andis. $dst, $src1, $src2", IntGeneral,
719 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
721 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
722 "ori $dst, $src1, $src2", IntGeneral,
723 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
724 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
725 "oris $dst, $src1, $src2", IntGeneral,
726 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
727 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
728 "xori $dst, $src1, $src2", IntGeneral,
729 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
730 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
731 "xoris $dst, $src1, $src2", IntGeneral,
732 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
733 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral,
735 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
736 "cmpwi $crD, $rA, $imm", IntCompare>;
737 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
738 "cmplwi $dst, $src1, $src2", IntCompare>;
742 let PPC970_Unit = 1 in { // FXU Operations.
743 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
744 "nand $rA, $rS, $rB", IntGeneral,
745 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
746 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
747 "and $rA, $rS, $rB", IntGeneral,
748 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
749 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
750 "andc $rA, $rS, $rB", IntGeneral,
751 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
752 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
753 "or $rA, $rS, $rB", IntGeneral,
754 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
755 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
756 "nor $rA, $rS, $rB", IntGeneral,
757 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
758 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
759 "orc $rA, $rS, $rB", IntGeneral,
760 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
761 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
762 "eqv $rA, $rS, $rB", IntGeneral,
763 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
764 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
765 "xor $rA, $rS, $rB", IntGeneral,
766 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
767 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
768 "slw $rA, $rS, $rB", IntGeneral,
769 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
770 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
771 "srw $rA, $rS, $rB", IntGeneral,
772 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
773 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
774 "sraw $rA, $rS, $rB", IntShift,
775 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
778 let PPC970_Unit = 1 in { // FXU Operations.
779 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
780 "srawi $rA, $rS, $SH", IntShift,
781 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
782 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
783 "cntlzw $rA, $rS", IntGeneral,
784 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
785 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
786 "extsb $rA, $rS", IntGeneral,
787 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
788 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
789 "extsh $rA, $rS", IntGeneral,
790 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
792 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
793 "cmpw $crD, $rA, $rB", IntCompare>;
794 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
795 "cmplw $crD, $rA, $rB", IntCompare>;
797 let PPC970_Unit = 3 in { // FPU Operations.
798 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
799 // "fcmpo $crD, $fA, $fB", FPCompare>;
800 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
801 "fcmpu $crD, $fA, $fB", FPCompare>;
802 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
803 "fcmpu $crD, $fA, $fB", FPCompare>;
805 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
806 "fctiwz $frD, $frB", FPGeneral,
807 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
808 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
809 "frsp $frD, $frB", FPGeneral,
810 [(set F4RC:$frD, (fround F8RC:$frB))]>;
811 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
812 "fsqrt $frD, $frB", FPSqrt,
813 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
814 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
815 "fsqrts $frD, $frB", FPSqrt,
816 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
819 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
821 /// Note that these are defined as pseudo-ops on the PPC970 because they are
822 /// often coalesced away and we don't want the dispatch group builder to think
823 /// that they will fill slots (which could cause the load of a LSU reject to
824 /// sneak into a d-group with a store).
825 def FMRS : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
826 "fmr $frD, $frB", FPGeneral,
827 []>, // (set F4RC:$frD, F4RC:$frB)
829 def FMRD : XForm_26<63, 72, (outs F8RC:$frD), (ins F8RC:$frB),
830 "fmr $frD, $frB", FPGeneral,
831 []>, // (set F8RC:$frD, F8RC:$frB)
833 def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB),
834 "fmr $frD, $frB", FPGeneral,
835 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
838 let PPC970_Unit = 3 in { // FPU Operations.
839 // These are artificially split into two different forms, for 4/8 byte FP.
840 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
841 "fabs $frD, $frB", FPGeneral,
842 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
843 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
844 "fabs $frD, $frB", FPGeneral,
845 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
846 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
847 "fnabs $frD, $frB", FPGeneral,
848 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
849 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
850 "fnabs $frD, $frB", FPGeneral,
851 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
852 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
853 "fneg $frD, $frB", FPGeneral,
854 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
855 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
856 "fneg $frD, $frB", FPGeneral,
857 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
861 // XL-Form instructions. condition register logical ops.
863 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
864 "mcrf $BF, $BFA", BrMCR>,
865 PPC970_DGroup_First, PPC970_Unit_CRU;
867 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
868 (ins CRBITRC:$CRA, CRBITRC:$CRB),
869 "creqv $CRD, $CRA, $CRB", BrCR,
872 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
873 (ins CRBITRC:$CRA, CRBITRC:$CRB),
874 "cror $CRD, $CRA, $CRB", BrCR,
877 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
878 "creqv $dst, $dst, $dst", BrCR,
881 // XFX-Form instructions. Instructions that deal with SPRs.
883 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
884 "mfctr $rT", SprMFSPR>,
885 PPC970_DGroup_First, PPC970_Unit_FXU;
886 let Pattern = [(PPCmtctr GPRC:$rS)] in {
887 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
888 "mtctr $rS", SprMTSPR>,
889 PPC970_DGroup_First, PPC970_Unit_FXU;
892 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
893 "mtlr $rS", SprMTSPR>,
894 PPC970_DGroup_First, PPC970_Unit_FXU;
895 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
896 "mflr $rT", SprMFSPR>,
897 PPC970_DGroup_First, PPC970_Unit_FXU;
899 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
900 // a GPR on the PPC970. As such, copies in and out have the same performance
901 // characteristics as an OR instruction.
902 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
903 "mtspr 256, $rS", IntGeneral>,
904 PPC970_DGroup_Single, PPC970_Unit_FXU;
905 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
906 "mfspr $rT, 256", IntGeneral>,
907 PPC970_DGroup_First, PPC970_Unit_FXU;
909 def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
910 "mtcrf $FXM, $rS", BrMCRX>,
911 PPC970_MicroCode, PPC970_Unit_CRU;
912 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), "mfcr $rT", SprMFCR>,
913 PPC970_MicroCode, PPC970_Unit_CRU;
914 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
915 "mfcr $rT, $FXM", SprMFCR>,
916 PPC970_DGroup_First, PPC970_Unit_CRU;
918 // Instructions to manipulate FPSCR. Only long double handling uses these.
919 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
921 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
923 [(set F8RC:$rT, (PPCmffs))]>,
924 PPC970_DGroup_Single, PPC970_Unit_FPU;
925 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
926 "mtfsb0 $FM", IntMTFSB0,
927 [(PPCmtfsb0 (i32 imm:$FM))]>,
928 PPC970_DGroup_Single, PPC970_Unit_FPU;
929 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
930 "mtfsb1 $FM", IntMTFSB0,
931 [(PPCmtfsb1 (i32 imm:$FM))]>,
932 PPC970_DGroup_Single, PPC970_Unit_FPU;
933 def FADDrtz: AForm_2<63, 21,
934 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
935 "fadd $FRT, $FRA, $FRB", FPGeneral,
936 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
937 PPC970_DGroup_Single, PPC970_Unit_FPU;
938 // MTFSF does not actually produce an FP result. We pretend it copies
939 // input reg B to the output. If we didn't do this it would look like the
940 // instruction had no outputs (because we aren't modelling the FPSCR) and
941 // it would be deleted.
942 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
943 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
944 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
945 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
946 F8RC:$rT, F8RC:$FRB))]>,
947 PPC970_DGroup_Single, PPC970_Unit_FPU;
949 let PPC970_Unit = 1 in { // FXU Operations.
951 // XO-Form instructions. Arithmetic instructions that can set overflow bit
953 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
954 "add $rT, $rA, $rB", IntGeneral,
955 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
956 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
957 "addc $rT, $rA, $rB", IntGeneral,
958 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
959 PPC970_DGroup_Cracked;
960 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
961 "adde $rT, $rA, $rB", IntGeneral,
962 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
963 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
964 "divw $rT, $rA, $rB", IntDivW,
965 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
966 PPC970_DGroup_First, PPC970_DGroup_Cracked;
967 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
968 "divwu $rT, $rA, $rB", IntDivW,
969 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
970 PPC970_DGroup_First, PPC970_DGroup_Cracked;
971 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
972 "mulhw $rT, $rA, $rB", IntMulHW,
973 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
974 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
975 "mulhwu $rT, $rA, $rB", IntMulHWU,
976 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
977 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
978 "mullw $rT, $rA, $rB", IntMulHW,
979 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
980 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
981 "subf $rT, $rA, $rB", IntGeneral,
982 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
983 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
984 "subfc $rT, $rA, $rB", IntGeneral,
985 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
986 PPC970_DGroup_Cracked;
987 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
988 "subfe $rT, $rA, $rB", IntGeneral,
989 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
990 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
991 "addme $rT, $rA", IntGeneral,
992 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
993 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
994 "addze $rT, $rA", IntGeneral,
995 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
996 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
997 "neg $rT, $rA", IntGeneral,
998 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
999 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1000 "subfme $rT, $rA", IntGeneral,
1001 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
1002 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1003 "subfze $rT, $rA", IntGeneral,
1004 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
1007 // A-Form instructions. Most of the instructions executed in the FPU are of
1010 let PPC970_Unit = 3 in { // FPU Operations.
1011 def FMADD : AForm_1<63, 29,
1012 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1013 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1014 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1016 Requires<[FPContractions]>;
1017 def FMADDS : AForm_1<59, 29,
1018 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1019 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1020 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1022 Requires<[FPContractions]>;
1023 def FMSUB : AForm_1<63, 28,
1024 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1025 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1026 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1028 Requires<[FPContractions]>;
1029 def FMSUBS : AForm_1<59, 28,
1030 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1031 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1032 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1034 Requires<[FPContractions]>;
1035 def FNMADD : AForm_1<63, 31,
1036 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1037 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1038 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1040 Requires<[FPContractions]>;
1041 def FNMADDS : AForm_1<59, 31,
1042 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1043 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1044 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1046 Requires<[FPContractions]>;
1047 def FNMSUB : AForm_1<63, 30,
1048 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1049 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1050 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1052 Requires<[FPContractions]>;
1053 def FNMSUBS : AForm_1<59, 30,
1054 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1055 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1056 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1058 Requires<[FPContractions]>;
1059 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1060 // having 4 of these, force the comparison to always be an 8-byte double (code
1061 // should use an FMRSD if the input comparison value really wants to be a float)
1062 // and 4/8 byte forms for the result and operand type..
1063 def FSELD : AForm_1<63, 23,
1064 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1065 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1066 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1067 def FSELS : AForm_1<63, 23,
1068 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1069 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1070 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1071 def FADD : AForm_2<63, 21,
1072 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1073 "fadd $FRT, $FRA, $FRB", FPGeneral,
1074 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1075 def FADDS : AForm_2<59, 21,
1076 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1077 "fadds $FRT, $FRA, $FRB", FPGeneral,
1078 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1079 def FDIV : AForm_2<63, 18,
1080 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1081 "fdiv $FRT, $FRA, $FRB", FPDivD,
1082 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1083 def FDIVS : AForm_2<59, 18,
1084 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1085 "fdivs $FRT, $FRA, $FRB", FPDivS,
1086 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1087 def FMUL : AForm_3<63, 25,
1088 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1089 "fmul $FRT, $FRA, $FRB", FPFused,
1090 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1091 def FMULS : AForm_3<59, 25,
1092 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1093 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1094 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1095 def FSUB : AForm_2<63, 20,
1096 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1097 "fsub $FRT, $FRA, $FRB", FPGeneral,
1098 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1099 def FSUBS : AForm_2<59, 20,
1100 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1101 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1102 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1105 let PPC970_Unit = 1 in { // FXU Operations.
1106 // M-Form instructions. rotate and mask instructions.
1108 let isCommutable = 1 in {
1109 // RLWIMI can be commuted if the rotate amount is zero.
1110 def RLWIMI : MForm_2<20,
1111 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1112 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1113 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1116 def RLWINM : MForm_2<21,
1117 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1118 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1120 def RLWINMo : MForm_2<21,
1121 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1122 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1123 []>, isDOT, PPC970_DGroup_Cracked;
1124 def RLWNM : MForm_2<23,
1125 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1126 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1131 //===----------------------------------------------------------------------===//
1132 // DWARF Pseudo Instructions
1135 def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
1136 "${:comment} .loc $file, $line, $col",
1137 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
1140 //===----------------------------------------------------------------------===//
1141 // PowerPC Instruction Patterns
1144 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1145 def : Pat<(i32 imm:$imm),
1146 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1148 // Implement the 'not' operation with the NOR instruction.
1149 def NOT : Pat<(not GPRC:$in),
1150 (NOR GPRC:$in, GPRC:$in)>;
1152 // ADD an arbitrary immediate.
1153 def : Pat<(add GPRC:$in, imm:$imm),
1154 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1155 // OR an arbitrary immediate.
1156 def : Pat<(or GPRC:$in, imm:$imm),
1157 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1158 // XOR an arbitrary immediate.
1159 def : Pat<(xor GPRC:$in, imm:$imm),
1160 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1162 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1163 (SUBFIC GPRC:$in, imm:$imm)>;
1166 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1167 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1168 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1169 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1172 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1173 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1174 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1175 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1178 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1179 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1182 def : Pat<(PPCcall_Macho (i32 tglobaladdr:$dst)),
1183 (BL_Macho tglobaladdr:$dst)>;
1184 def : Pat<(PPCcall_Macho (i32 texternalsym:$dst)),
1185 (BL_Macho texternalsym:$dst)>;
1186 def : Pat<(PPCcall_ELF (i32 tglobaladdr:$dst)),
1187 (BL_ELF tglobaladdr:$dst)>;
1188 def : Pat<(PPCcall_ELF (i32 texternalsym:$dst)),
1189 (BL_ELF texternalsym:$dst)>;
1191 // Hi and Lo for Darwin Global Addresses.
1192 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1193 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1194 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1195 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1196 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1197 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1198 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1199 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1200 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1201 (ADDIS GPRC:$in, tconstpool:$g)>;
1202 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1203 (ADDIS GPRC:$in, tjumptable:$g)>;
1205 // Fused negative multiply subtract, alternate pattern
1206 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1207 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1208 Requires<[FPContractions]>;
1209 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1210 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1211 Requires<[FPContractions]>;
1213 // Standard shifts. These are represented separately from the real shifts above
1214 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1216 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1217 (SRAW GPRC:$rS, GPRC:$rB)>;
1218 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1219 (SRW GPRC:$rS, GPRC:$rB)>;
1220 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1221 (SLW GPRC:$rS, GPRC:$rB)>;
1223 def : Pat<(zextloadi1 iaddr:$src),
1225 def : Pat<(zextloadi1 xaddr:$src),
1227 def : Pat<(extloadi1 iaddr:$src),
1229 def : Pat<(extloadi1 xaddr:$src),
1231 def : Pat<(extloadi8 iaddr:$src),
1233 def : Pat<(extloadi8 xaddr:$src),
1235 def : Pat<(extloadi16 iaddr:$src),
1237 def : Pat<(extloadi16 xaddr:$src),
1239 def : Pat<(extloadf32 iaddr:$src),
1240 (FMRSD (LFS iaddr:$src))>;
1241 def : Pat<(extloadf32 xaddr:$src),
1242 (FMRSD (LFSX xaddr:$src))>;
1244 include "PPCInstrAltivec.td"
1245 include "PPCInstr64Bit.td"