2 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
4 // The LLVM Compiler Infrastructure
6 // This file was developed by the LLVM research group and is distributed under
7 // the University of Illinois Open Source License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the subset of the 32-bit PowerPC instruction set, as used
12 // by the PowerPC instruction selector.
14 //===----------------------------------------------------------------------===//
16 include "PowerPCInstrFormats.td"
18 class isPPC64 { bit PPC64 = 1; }
19 class isVMX { bit VMX = 1; }
21 let isTerminator = 1 in {
23 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, 0, 0, (ops), "blr">;
24 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, 0, 0, (ops), "bctr">;
27 def u5imm : Operand<i8> {
28 let PrintMethod = "printU5ImmOperand";
30 def u6imm : Operand<i8> {
31 let PrintMethod = "printU6ImmOperand";
33 def s16imm : Operand<i16> {
34 let PrintMethod = "printS16ImmOperand";
36 def u16imm : Operand<i16> {
37 let PrintMethod = "printU16ImmOperand";
39 def target : Operand<i32> {
40 let PrintMethod = "printBranchOperand";
42 def piclabel: Operand<i32> {
43 let PrintMethod = "printPICLabel";
45 def symbolHi: Operand<i32> {
46 let PrintMethod = "printSymbolHi";
48 def symbolLo: Operand<i32> {
49 let PrintMethod = "printSymbolLo";
51 def crbit: Operand<i8> {
52 let PrintMethod = "printcrbit";
55 // Pseudo-instructions:
56 def PHI : Pseudo<(ops), "; PHI">;
58 def ADJCALLSTACKDOWN : Pseudo<(ops), "; ADJCALLSTACKDOWN">;
59 def ADJCALLSTACKUP : Pseudo<(ops), "; ADJCALLSTACKUP">;
61 def IMPLICIT_DEF : Pseudo<(ops), "; IMPLICIT_DEF">;
64 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
66 let isBranch = 1, isTerminator = 1 in {
67 def COND_BRANCH : Pseudo<(ops), "; COND_BRANCH">;
68 def B : IForm<18, 0, 0, 0, 0, (ops target:$func), "b $func">;
69 //def BA : IForm<18, 1, 0, 0, 0, (ops target:$func), "ba $func">;
70 def BL : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
71 //def BLA : IForm<18, 1, 1, 0, 0, (ops target:$func), "bla $func">;
73 // FIXME: 4*CR# needs to be added to the BI field!
74 // This will only work for CR0 as it stands now
75 def BLT : BForm_ext<16, 0, 0, 12, 0, 0, 0, (ops CRRC:$crS, target:$block),
77 def BLE : BForm_ext<16, 0, 0, 4, 1, 0, 0, (ops CRRC:$crS, target:$block),
79 def BEQ : BForm_ext<16, 0, 0, 12, 2, 0, 0, (ops CRRC:$crS, target:$block),
81 def BGE : BForm_ext<16, 0, 0, 4, 0, 0, 0, (ops CRRC:$crS, target:$block),
83 def BGT : BForm_ext<16, 0, 0, 12, 1, 0, 0, (ops CRRC:$crS, target:$block),
85 def BNE : BForm_ext<16, 0, 0, 4, 2, 0, 0, (ops CRRC:$crS, target:$block),
89 let isBranch = 1, isTerminator = 1, isCall = 1,
90 // All calls clobber the non-callee saved registers...
91 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
92 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
94 CR0,CR1,CR5,CR6,CR7] in {
95 // Convenient aliases for call instructions
96 def CALLpcrel : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
97 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1, 0, 0, (ops), "bctrl">;
100 // D-Form instructions. Most instructions that perform an operation on a
101 // register and an immediate are of this type.
104 def LBZ : DForm_1<34, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
105 "lbz $rD, $disp($rA)">;
106 def LHA : DForm_1<42, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
107 "lha $rD, $disp($rA)">;
108 def LHZ : DForm_1<40, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
109 "lhz $rD, $disp($rA)">;
110 def LMW : DForm_1<46, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
111 "lmw $rD, $disp($rA)">;
112 def LWZ : DForm_1<32, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
113 "lwz $rD, $disp($rA)">;
114 def LWZU : DForm_1<35, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
115 "lwzu $rD, $disp($rA)">;
117 def ADDI : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
118 "addi $rD, $rA, $imm">;
119 def ADDIC : DForm_2<12, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
120 "addic $rD, $rA, $imm">;
121 def ADDICo : DForm_2<13, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
122 "addic. $rD, $rA, $imm">;
123 def ADDIS : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
124 "addis $rD, $rA, $imm">;
125 def LA : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
126 "la $rD, $sym($rA)">;
127 def LOADHiAddr : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolHi:$sym),
128 "addis $rD, $rA, $sym">;
129 def MULLI : DForm_2< 7, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
130 "mulli $rD, $rA, $imm">;
131 def SUBFIC : DForm_2< 8, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
132 "subfic $rD, $rA, $imm">;
133 def LI : DForm_2_r0<14, 0, 0, (ops GPRC:$rD, s16imm:$imm),
135 def LIS : DForm_2_r0<15, 0, 0, (ops GPRC:$rD, s16imm:$imm),
138 def STMW : DForm_3<47, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
139 "stmw $rS, $disp($rA)">;
140 def STB : DForm_3<38, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
141 "stb $rS, $disp($rA)">;
142 def STH : DForm_3<44, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
143 "sth $rS, $disp($rA)">;
144 def STW : DForm_3<36, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
145 "stw $rS, $disp($rA)">;
146 def STWU : DForm_3<37, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
147 "stwu $rS, $disp($rA)">;
149 let Defs = [CR0] in {
150 def ANDIo : DForm_4<28, 0, 0,
151 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
152 "andi. $dst, $src1, $src2">;
153 def ANDISo : DForm_4<29, 0, 0,
154 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
155 "andis. $dst, $src1, $src2">;
157 def ORI : DForm_4<24, 0, 0,
158 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
159 "ori $dst, $src1, $src2">;
160 def ORIS : DForm_4<25, 0, 0,
161 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
162 "oris $dst, $src1, $src2">;
163 def XORI : DForm_4<26, 0, 0,
164 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
165 "xori $dst, $src1, $src2">;
166 def XORIS : DForm_4<27, 0, 0,
167 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
168 "xoris $dst, $src1, $src2">;
169 def NOP : DForm_4_zero<24, 0, 0, (ops), "nop">;
170 def CMPI : DForm_5<11, 0, 0, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
171 "cmpi $crD, $L, $rA, $imm">;
172 def CMPWI : DForm_5_ext<11, 0, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
173 "cmpwi $crD, $rA, $imm">;
174 def CMPDI : DForm_5_ext<11, 1, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
175 "cmpdi $crD, $rA, $imm">;
176 def CMPLI : DForm_6<10, 0, 0,
177 (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
178 "cmpli $dst, $size, $src1, $src2">;
179 def CMPLWI : DForm_6_ext<10, 0, 0,
180 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
181 "cmplwi $dst, $src1, $src2">;
182 def CMPLDI : DForm_6_ext<10, 1, 0,
183 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
184 "cmpldi $dst, $src1, $src2">;
186 def LFS : DForm_8<48, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
187 "lfs $rD, $disp($rA)">;
188 def LFD : DForm_8<50, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
189 "lfd $rD, $disp($rA)">;
192 def STFS : DForm_9<52, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
193 "stfs $rS, $disp($rA)">;
194 def STFD : DForm_9<54, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
195 "stfd $rS, $disp($rA)">;
198 // DS-Form instructions. Load/Store instructions available in PPC-64
201 def LWA : DSForm_1<58, 2, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
202 "lwa $rT, $DS($rA)">;
203 def LD : DSForm_2<58, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
207 def STD : DSForm_2<62, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
208 "std $rT, $DS($rA)">;
209 def STDU : DSForm_2<62, 1, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
210 "stdu $rT, $DS($rA)">;
213 // X-Form instructions. Most instructions that perform an operation on a
214 // register and another register are of this type.
217 def LBZX : XForm_1<31, 87, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
218 "lbzx $dst, $base, $index">;
219 def LHAX : XForm_1<31, 343, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
220 "lhax $dst, $base, $index">;
221 def LHZX : XForm_1<31, 279, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
222 "lhzx $dst, $base, $index">;
223 def LWAX : XForm_1<31, 341, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
224 "lwax $dst, $base, $index">;
225 def LWZX : XForm_1<31, 23, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
226 "lwzx $dst, $base, $index">;
227 def LDX : XForm_1<31, 21, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
228 "ldx $dst, $base, $index">;
230 def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
231 "and $rA, $rS, $rB">;
233 def ANDo : XForm_6<31, 28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
234 "and. $rA, $rS, $rB">;
235 def ANDC : XForm_6<31, 60, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
236 "andc $rA, $rS, $rB">;
237 def EQV : XForm_6<31, 284, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
238 "eqv $rA, $rS, $rB">;
239 def NAND : XForm_6<31, 476, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
240 "nand $rA, $rS, $rB">;
241 def NOR : XForm_6<31, 124, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
242 "nor $rA, $rS, $rB">;
243 def OR : XForm_6<31, 444, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
246 def ORo : XForm_6<31, 444, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
247 "or. $rA, $rS, $rB">;
248 def ORC : XForm_6<31, 412, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
249 "orc $rA, $rS, $rB">;
250 def SLD : XForm_6<31, 27, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
251 "sld $rA, $rS, $rB">;
252 def SLW : XForm_6<31, 24, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
253 "slw $rA, $rS, $rB">;
254 def SRD : XForm_6<31, 539, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
255 "srd $rA, $rS, $rB">;
256 def SRW : XForm_6<31, 536, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
257 "srw $rA, $rS, $rB">;
258 def SRAD : XForm_6<31, 794, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
259 "srad $rA, $rS, $rB">;
260 def SRAW : XForm_6<31, 792, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
261 "sraw $rA, $rS, $rB">;
262 def XOR : XForm_6<31, 316, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
263 "xor $rA, $rS, $rB">;
265 def STBX : XForm_8<31, 215, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
266 "stbx $rS, $rA, $rB">;
267 def STHX : XForm_8<31, 407, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
268 "sthx $rS, $rA, $rB">;
269 def STWX : XForm_8<31, 151, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
270 "stwx $rS, $rA, $rB">;
271 def STWUX : XForm_8<31, 183, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
272 "stwux $rS, $rA, $rB">;
273 def STDX : XForm_8<31, 149, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
274 "stdx $rS, $rA, $rB">;
275 def STDUX : XForm_8<31, 181, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
276 "stdux $rS, $rA, $rB">;
278 def SRAWI : XForm_10<31, 824, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
279 "srawi $rA, $rS, $SH">;
280 def CNTLZW : XForm_11<31, 26, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
282 def EXTSB : XForm_11<31, 954, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
284 def EXTSH : XForm_11<31, 922, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
286 def EXTSW : XForm_11<31, 986, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS),
288 def CMP : XForm_16<31, 0, 0, 0,
289 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
290 "cmp $crD, $long, $rA, $rB">;
291 def CMPL : XForm_16<31, 32, 0, 0,
292 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
293 "cmpl $crD, $long, $rA, $rB">;
294 def CMPW : XForm_16_ext<31, 0, 0, 0,
295 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
296 "cmpw $crD, $rA, $rB">;
297 def CMPD : XForm_16_ext<31, 0, 1, 0,
298 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
299 "cmpd $crD, $rA, $rB">;
300 def CMPLW : XForm_16_ext<31, 32, 0, 0,
301 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
302 "cmplw $crD, $rA, $rB">;
303 def CMPLD : XForm_16_ext<31, 32, 1, 0,
304 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
305 "cmpld $crD, $rA, $rB">;
306 def FCMPO : XForm_17<63, 32, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
307 "fcmpo $crD, $fA, $fB">;
308 def FCMPU : XForm_17<63, 0, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
309 "fcmpu $crD, $fA, $fB">;
311 def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
312 "lfsx $dst, $base, $index">;
313 def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
314 "lfdx $dst, $base, $index">;
316 def FCFID : XForm_26<63, 846, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
318 def FCTIDZ : XForm_26<63, 815, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
319 "fctidz $frD, $frB">;
320 def FCTIWZ : XForm_26<63, 15, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
321 "fctiwz $frD, $frB">;
322 def FABS : XForm_26<63, 264, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
324 def FMR : XForm_26<63, 72, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
326 def FNABS : XForm_26<63, 136, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
328 def FNEG : XForm_26<63, 40, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
330 def FRSP : XForm_26<63, 12, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
333 def STFSX : XForm_28<31, 663, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
334 "stfsx $frS, $rA, $rB">;
335 def STFDX : XForm_28<31, 727, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
336 "stfdx $frS, $rA, $rB">;
339 // XL-Form instructions. condition register logical ops.
341 def CRAND : XLForm_1<19, 257, 0, 0, (ops CRRC:$D, crbit:$Db,
342 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
343 "crand $Db, $Ab, $Bb">;
344 def CRANDC : XLForm_1<19, 129, 0, 0, (ops CRRC:$D, crbit:$Db,
345 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
346 "crandc $Db, $Ab, $Bb">;
347 def CREQV : XLForm_1<19, 289, 0, 0, (ops CRRC:$D, crbit:$Db,
348 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
349 "creqv $Db, $Ab, $Bb">;
350 def CRNAND : XLForm_1<19, 225, 0, 0, (ops CRRC:$D, crbit:$Db,
351 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
352 "crnand $Db, $Ab, $Bb">;
353 def CRNOR : XLForm_1<19, 33, 0, 0, (ops CRRC:$D, crbit:$Db,
354 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
355 "crnor $Db, $Ab, $Bb">;
356 def CROR : XLForm_1<19, 449, 0, 0, (ops CRRC:$D, crbit:$Db,
357 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
358 "cror $Db, $Ab, $Bb">;
359 def CRORC : XLForm_1<19, 417, 0, 0, (ops CRRC:$D, crbit:$Db,
360 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
361 "crorc $Db, $Ab, $Bb">;
362 def CRXOR : XLForm_1<19, 193, 0, 0, (ops CRRC:$D, crbit:$Db,
363 CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
364 "crxor $Db, $Ab, $Bb">;
365 def MCRF : XLForm_3<19, 0, 0, 0, (ops CRRC:$BF, CRRC:$BFA),
368 // XFX-Form instructions. Instructions that deal with SPRs
370 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
371 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
372 // which means the SPR value needs to be multiplied by a factor of 32.
373 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT">;
374 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT">;
375 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">;
376 def MTCRF : XFXForm_5<31, 0, 144, (ops CRRC:$FXM, GPRC:$rS),
378 def MFCRF : XFXForm_5<31, 1, 19, (ops GPRC:$rT, CRRC:$FXM),
380 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">;
381 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;
383 // XS-Form instructions. Just 'sradi'
385 def SRADI : XSForm_1<31, 413, 0, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
386 "sradi $rA, $rS, $SH">, isPPC64;
388 // XO-Form instructions. Arithmetic instructions that can set overflow bit
390 def ADD : XOForm_1<31, 266, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
391 "add $rT, $rA, $rB">;
392 def ADDC : XOForm_1<31, 10, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
393 "addc $rT, $rA, $rB">;
394 def ADDE : XOForm_1<31, 138, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
395 "adde $rT, $rA, $rB">;
396 def DIVD : XOForm_1<31, 489, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
397 "divd $rT, $rA, $rB">, isPPC64;
398 def DIVDU : XOForm_1<31, 457, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
399 "divdu $rT, $rA, $rB">, isPPC64;
400 def DIVW : XOForm_1<31, 491, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
401 "divw $rT, $rA, $rB">;
402 def DIVWU : XOForm_1<31, 459, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
403 "divwu $rT, $rA, $rB">;
404 def MULHW : XOForm_1<31, 75, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
405 "mulhw $rT, $rA, $rB">;
406 def MULHWU : XOForm_1<31, 11, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
407 "mulhwu $rT, $rA, $rB">;
408 def MULLD : XOForm_1<31, 233, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
409 "mulld $rT, $rA, $rB">, isPPC64;
410 def MULLW : XOForm_1<31, 235, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
411 "mullw $rT, $rA, $rB">;
412 def SUBF : XOForm_1<31, 40, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
413 "subf $rT, $rA, $rB">;
414 def SUBFC : XOForm_1<31, 8, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
415 "subfc $rT, $rA, $rB">;
416 def SUBFE : XOForm_1<31, 136, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
417 "subfe $rT, $rA, $rB">;
418 def SUB : XOForm_1r<31, 40, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
419 "sub $rT, $rA, $rB">;
420 def ADDME : XOForm_3<31, 234, 0, 0, (ops GPRC:$rT, GPRC:$rA),
422 def ADDZE : XOForm_3<31, 202, 0, 0, (ops GPRC:$rT, GPRC:$rA),
424 def NEG : XOForm_3<31, 104, 0, 0, (ops GPRC:$rT, GPRC:$rA),
426 def SUBFZE : XOForm_3<31, 200, 0, 0, (ops GPRC:$rT, GPRC:$rA),
429 // A-Form instructions. Most of the instructions executed in the FPU are of
432 def FMADD : AForm_1<63, 29, 0,
433 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
434 "fmadd $FRT, $FRA, $FRC, $FRB">;
435 def FMADDS : AForm_1<59, 29, 0,
436 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
437 "fmadds $FRT, $FRA, $FRC, $FRB">;
438 def FMSUB : AForm_1<63, 28, 0,
439 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
440 "fmsub $FRT, $FRA, $FRC, $FRB">;
441 def FMSUBS : AForm_1<59, 28, 0,
442 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
443 "fmsubs $FRT, $FRA, $FRC, $FRB">;
444 def FNMADD : AForm_1<63, 31, 0,
445 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
446 "fnmadd $FRT, $FRA, $FRC, $FRB">;
447 def FNMADDS : AForm_1<59, 31, 0,
448 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
449 "fnmadds $FRT, $FRA, $FRC, $FRB">;
450 def FNMSUB : AForm_1<63, 30, 0,
451 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
452 "fnmsub $FRT, $FRA, $FRC, $FRB">;
453 def FNMSUBS : AForm_1<59, 30, 0,
454 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
455 "fnmsubs $FRT, $FRA, $FRC, $FRB">;
456 def FSEL : AForm_1<63, 23, 0,
457 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
458 "fsel $FRT, $FRA, $FRC, $FRB">;
459 def FADD : AForm_2<63, 21, 0,
460 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
461 "fadd $FRT, $FRA, $FRB">;
462 def FADDS : AForm_2<59, 21, 0,
463 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
464 "fadds $FRT, $FRA, $FRB">;
465 def FDIV : AForm_2<63, 18, 0,
466 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
467 "fdiv $FRT, $FRA, $FRB">;
468 def FDIVS : AForm_2<59, 18, 0,
469 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
470 "fdivs $FRT, $FRA, $FRB">;
471 def FMUL : AForm_3<63, 25, 0,
472 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
473 "fmul $FRT, $FRA, $FRB">;
474 def FMULS : AForm_3<59, 25, 0,
475 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
476 "fmuls $FRT, $FRA, $FRB">;
477 def FSUB : AForm_2<63, 20, 0,
478 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
479 "fsub $FRT, $FRA, $FRB">;
480 def FSUBS : AForm_2<59, 20, 0,
481 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
482 "fsubs $FRT, $FRA, $FRB">;
484 // M-Form instructions. rotate and mask instructions.
486 let isTwoAddress = 1 in {
487 def RLWIMI : MForm_2<20, 0,
488 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
489 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
491 def RLWINM : MForm_2<21, 0,
492 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
493 "rlwinm $rA, $rS, $SH, $MB, $ME">;
495 def RLWINMo : MForm_2<21, 1,
496 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
497 "rlwinm. $rA, $rS, $SH, $MB, $ME">;
498 def RLWNM : MForm_2<23, 0,
499 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
500 "rlwnm $rA, $rS, $rB, $MB, $ME">;
502 // MD-Form instructions. 64 bit rotate instructions.
504 def RLDICL : MDForm_1<30, 0, 0,
505 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
506 "rldicl $rA, $rS, $SH, $MB">, isPPC64;
507 def RLDICR : MDForm_1<30, 1, 0,
508 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
509 "rldicr $rA, $rS, $SH, $ME">, isPPC64;
511 def PowerPCInstrInfo : InstrInfo {
514 let TSFlagsFields = [ "VMX", "PPC64" ];
515 let TSFlagsShifts = [ 0, 1 ];
517 let isLittleEndianEncoding = 1;