1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
61 //===----------------------------------------------------------------------===//
62 // PowerPC specific DAG Nodes.
65 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
66 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
68 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
69 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
70 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
71 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
72 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
73 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
74 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
75 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
76 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
77 [SDNPHasChain, SDNPMayStore]>;
78 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
79 [SDNPHasChain, SDNPMayLoad]>;
80 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
81 [SDNPHasChain, SDNPMayLoad]>;
83 // Extract FPSCR (not modeled at the DAG level).
84 def PPCmffs : SDNode<"PPCISD::MFFS",
85 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
87 // Perform FADD in round-to-zero mode.
88 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
91 def PPCfsel : SDNode<"PPCISD::FSEL",
92 // Type constraint for fsel.
93 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
94 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
96 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
97 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
98 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
99 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
100 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
102 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
103 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
105 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
106 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
107 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
108 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
109 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
110 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
111 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
112 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
114 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
116 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
118 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
119 // amounts. These nodes are generated by the multi-precision shift code.
120 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
121 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
122 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
124 // These are target-independent nodes, but have target-specific formats.
125 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
126 [SDNPHasChain, SDNPOutGlue]>;
127 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
128 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
130 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
131 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
134 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
135 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
137 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
139 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
140 [SDNPHasChain, SDNPSideEffect,
141 SDNPInGlue, SDNPOutGlue]>;
142 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
143 [SDNPHasChain, SDNPSideEffect,
144 SDNPInGlue, SDNPOutGlue]>;
145 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
147 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
151 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
152 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
154 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
157 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
158 SDTypeProfile<1, 1, [SDTCisInt<0>,
160 [SDNPHasChain, SDNPSideEffect]>;
161 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
162 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
163 [SDNPHasChain, SDNPSideEffect]>;
165 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
166 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
167 [SDNPHasChain, SDNPSideEffect]>;
169 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
170 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
172 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
173 [SDNPHasChain, SDNPOptInGlue]>;
175 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
176 [SDNPHasChain, SDNPMayLoad]>;
177 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
178 [SDNPHasChain, SDNPMayStore]>;
180 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
181 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
182 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
183 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
186 // Instructions to support atomic operations
187 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
188 [SDNPHasChain, SDNPMayLoad]>;
189 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
190 [SDNPHasChain, SDNPMayStore]>;
192 // Instructions to support medium and large code model
193 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
194 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
195 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
198 // Instructions to support dynamic alloca.
199 def SDTDynOp : SDTypeProfile<1, 2, []>;
200 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
202 //===----------------------------------------------------------------------===//
203 // PowerPC specific transformation functions and pattern fragments.
206 def SHL32 : SDNodeXForm<imm, [{
207 // Transformation function: 31 - imm
208 return getI32Imm(31 - N->getZExtValue());
211 def SRL32 : SDNodeXForm<imm, [{
212 // Transformation function: 32 - imm
213 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
216 def LO16 : SDNodeXForm<imm, [{
217 // Transformation function: get the low 16 bits.
218 return getI32Imm((unsigned short)N->getZExtValue());
221 def HI16 : SDNodeXForm<imm, [{
222 // Transformation function: shift the immediate value down into the low bits.
223 return getI32Imm((unsigned)N->getZExtValue() >> 16);
226 def HA16 : SDNodeXForm<imm, [{
227 // Transformation function: shift the immediate value down into the low bits.
228 signed int Val = N->getZExtValue();
229 return getI32Imm((Val - (signed short)Val) >> 16);
231 def MB : SDNodeXForm<imm, [{
232 // Transformation function: get the start bit of a mask
234 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
235 return getI32Imm(mb);
238 def ME : SDNodeXForm<imm, [{
239 // Transformation function: get the end bit of a mask
241 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
242 return getI32Imm(me);
244 def maskimm32 : PatLeaf<(imm), [{
245 // maskImm predicate - True if immediate is a run of ones.
247 if (N->getValueType(0) == MVT::i32)
248 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
253 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
254 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
255 // sign extended field. Used by instructions like 'addi'.
256 return (int32_t)Imm == (short)Imm;
258 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
259 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
260 // sign extended field. Used by instructions like 'addi'.
261 return (int64_t)Imm == (short)Imm;
263 def immZExt16 : PatLeaf<(imm), [{
264 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
265 // field. Used by instructions like 'ori'.
266 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
269 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
270 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
271 // identical in 32-bit mode, but in 64-bit mode, they return true if the
272 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
274 def imm16ShiftedZExt : PatLeaf<(imm), [{
275 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
276 // immediate are set. Used by instructions like 'xoris'.
277 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
280 def imm16ShiftedSExt : PatLeaf<(imm), [{
281 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
282 // immediate are set. Used by instructions like 'addis'. Identical to
283 // imm16ShiftedZExt in 32-bit mode.
284 if (N->getZExtValue() & 0xFFFF) return false;
285 if (N->getValueType(0) == MVT::i32)
287 // For 64-bit, make sure it is sext right.
288 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
291 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
292 // restricted memrix (4-aligned) constants are alignment sensitive. If these
293 // offsets are hidden behind TOC entries than the values of the lower-order
294 // bits cannot be checked directly. As a result, we need to also incorporate
295 // an alignment check into the relevant patterns.
297 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
298 return cast<LoadSDNode>(N)->getAlignment() >= 4;
300 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
301 (store node:$val, node:$ptr), [{
302 return cast<StoreSDNode>(N)->getAlignment() >= 4;
304 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
305 return cast<LoadSDNode>(N)->getAlignment() >= 4;
307 def aligned4pre_store : PatFrag<
308 (ops node:$val, node:$base, node:$offset),
309 (pre_store node:$val, node:$base, node:$offset), [{
310 return cast<StoreSDNode>(N)->getAlignment() >= 4;
313 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
314 return cast<LoadSDNode>(N)->getAlignment() < 4;
316 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
317 (store node:$val, node:$ptr), [{
318 return cast<StoreSDNode>(N)->getAlignment() < 4;
320 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
321 return cast<LoadSDNode>(N)->getAlignment() < 4;
324 //===----------------------------------------------------------------------===//
325 // PowerPC Flag Definitions.
327 class isPPC64 { bit PPC64 = 1; }
328 class isDOT { bit RC = 1; }
330 class RegConstraint<string C> {
331 string Constraints = C;
333 class NoEncode<string E> {
334 string DisableEncoding = E;
338 //===----------------------------------------------------------------------===//
339 // PowerPC Operand Definitions.
341 // In the default PowerPC assembler syntax, registers are specified simply
342 // by number, so they cannot be distinguished from immediate values (without
343 // looking at the opcode). This means that the default operand matching logic
344 // for the asm parser does not work, and we need to specify custom matchers.
345 // Since those can only be specified with RegisterOperand classes and not
346 // directly on the RegisterClass, all instructions patterns used by the asm
347 // parser need to use a RegisterOperand (instead of a RegisterClass) for
348 // all their register operands.
349 // For this purpose, we define one RegisterOperand for each RegisterClass,
350 // using the same name as the class, just in lower case.
352 def PPCRegGPRCAsmOperand : AsmOperandClass {
353 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
355 def gprc : RegisterOperand<GPRC> {
356 let ParserMatchClass = PPCRegGPRCAsmOperand;
358 def PPCRegG8RCAsmOperand : AsmOperandClass {
359 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
361 def g8rc : RegisterOperand<G8RC> {
362 let ParserMatchClass = PPCRegG8RCAsmOperand;
364 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
365 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
367 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
368 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
370 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
371 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
373 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
374 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
376 def PPCRegF8RCAsmOperand : AsmOperandClass {
377 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
379 def f8rc : RegisterOperand<F8RC> {
380 let ParserMatchClass = PPCRegF8RCAsmOperand;
382 def PPCRegF4RCAsmOperand : AsmOperandClass {
383 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
385 def f4rc : RegisterOperand<F4RC> {
386 let ParserMatchClass = PPCRegF4RCAsmOperand;
388 def PPCRegVRRCAsmOperand : AsmOperandClass {
389 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
391 def vrrc : RegisterOperand<VRRC> {
392 let ParserMatchClass = PPCRegVRRCAsmOperand;
394 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
395 let Name = "RegCRBITRC"; let PredicateMethod = "isRegNumber";
397 def crbitrc : RegisterOperand<CRBITRC> {
398 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
400 def PPCRegCRRCAsmOperand : AsmOperandClass {
401 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
403 def crrc : RegisterOperand<CRRC> {
404 let ParserMatchClass = PPCRegCRRCAsmOperand;
407 def PPCS5ImmAsmOperand : AsmOperandClass {
408 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
409 let RenderMethod = "addImmOperands";
411 def s5imm : Operand<i32> {
412 let PrintMethod = "printS5ImmOperand";
413 let ParserMatchClass = PPCS5ImmAsmOperand;
415 def PPCU5ImmAsmOperand : AsmOperandClass {
416 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
417 let RenderMethod = "addImmOperands";
419 def u5imm : Operand<i32> {
420 let PrintMethod = "printU5ImmOperand";
421 let ParserMatchClass = PPCU5ImmAsmOperand;
423 def PPCU6ImmAsmOperand : AsmOperandClass {
424 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
425 let RenderMethod = "addImmOperands";
427 def u6imm : Operand<i32> {
428 let PrintMethod = "printU6ImmOperand";
429 let ParserMatchClass = PPCU6ImmAsmOperand;
431 def PPCS16ImmAsmOperand : AsmOperandClass {
432 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
433 let RenderMethod = "addImmOperands";
435 def s16imm : Operand<i32> {
436 let PrintMethod = "printS16ImmOperand";
437 let EncoderMethod = "getImm16Encoding";
438 let ParserMatchClass = PPCS16ImmAsmOperand;
440 def PPCU16ImmAsmOperand : AsmOperandClass {
441 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
442 let RenderMethod = "addImmOperands";
444 def u16imm : Operand<i32> {
445 let PrintMethod = "printU16ImmOperand";
446 let EncoderMethod = "getImm16Encoding";
447 let ParserMatchClass = PPCU16ImmAsmOperand;
449 def PPCS17ImmAsmOperand : AsmOperandClass {
450 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
451 let RenderMethod = "addImmOperands";
453 def s17imm : Operand<i32> {
454 // This operand type is used for addis/lis to allow the assembler parser
455 // to accept immediates in the range -65536..65535 for compatibility with
456 // the GNU assembler. The operand is treated as 16-bit otherwise.
457 let PrintMethod = "printS16ImmOperand";
458 let EncoderMethod = "getImm16Encoding";
459 let ParserMatchClass = PPCS17ImmAsmOperand;
461 def PPCDirectBrAsmOperand : AsmOperandClass {
462 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
463 let RenderMethod = "addBranchTargetOperands";
465 def directbrtarget : Operand<OtherVT> {
466 let PrintMethod = "printBranchOperand";
467 let EncoderMethod = "getDirectBrEncoding";
468 let ParserMatchClass = PPCDirectBrAsmOperand;
470 def absdirectbrtarget : Operand<OtherVT> {
471 let PrintMethod = "printAbsBranchOperand";
472 let EncoderMethod = "getAbsDirectBrEncoding";
473 let ParserMatchClass = PPCDirectBrAsmOperand;
475 def PPCCondBrAsmOperand : AsmOperandClass {
476 let Name = "CondBr"; let PredicateMethod = "isCondBr";
477 let RenderMethod = "addBranchTargetOperands";
479 def condbrtarget : Operand<OtherVT> {
480 let PrintMethod = "printBranchOperand";
481 let EncoderMethod = "getCondBrEncoding";
482 let ParserMatchClass = PPCCondBrAsmOperand;
484 def abscondbrtarget : Operand<OtherVT> {
485 let PrintMethod = "printAbsBranchOperand";
486 let EncoderMethod = "getAbsCondBrEncoding";
487 let ParserMatchClass = PPCCondBrAsmOperand;
489 def calltarget : Operand<iPTR> {
490 let PrintMethod = "printBranchOperand";
491 let EncoderMethod = "getDirectBrEncoding";
492 let ParserMatchClass = PPCDirectBrAsmOperand;
494 def abscalltarget : Operand<iPTR> {
495 let PrintMethod = "printAbsBranchOperand";
496 let EncoderMethod = "getAbsDirectBrEncoding";
497 let ParserMatchClass = PPCDirectBrAsmOperand;
499 def PPCCRBitMaskOperand : AsmOperandClass {
500 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
502 def crbitm: Operand<i8> {
503 let PrintMethod = "printcrbitm";
504 let EncoderMethod = "get_crbitm_encoding";
505 let ParserMatchClass = PPCCRBitMaskOperand;
508 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
509 def PPCRegGxRCNoR0Operand : AsmOperandClass {
510 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
512 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
513 let ParserMatchClass = PPCRegGxRCNoR0Operand;
515 // A version of ptr_rc usable with the asm parser.
516 def PPCRegGxRCOperand : AsmOperandClass {
517 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
519 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
520 let ParserMatchClass = PPCRegGxRCOperand;
523 def PPCDispRIOperand : AsmOperandClass {
524 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
525 let RenderMethod = "addImmOperands";
527 def dispRI : Operand<iPTR> {
528 let ParserMatchClass = PPCDispRIOperand;
530 def PPCDispRIXOperand : AsmOperandClass {
531 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
532 let RenderMethod = "addImmOperands";
534 def dispRIX : Operand<iPTR> {
535 let ParserMatchClass = PPCDispRIXOperand;
538 def memri : Operand<iPTR> {
539 let PrintMethod = "printMemRegImm";
540 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
541 let EncoderMethod = "getMemRIEncoding";
543 def memrr : Operand<iPTR> {
544 let PrintMethod = "printMemRegReg";
545 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
547 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
548 let PrintMethod = "printMemRegImm";
549 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
550 let EncoderMethod = "getMemRIXEncoding";
553 // A single-register address. This is used with the SjLj
554 // pseudo-instructions.
555 def memr : Operand<iPTR> {
556 let MIOperandInfo = (ops ptr_rc:$ptrreg);
559 // PowerPC Predicate operand.
560 def pred : Operand<OtherVT> {
561 let PrintMethod = "printPredicateOperand";
562 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
565 // Define PowerPC specific addressing mode.
566 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
567 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
568 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
569 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
571 // The address in a single register. This is used with the SjLj
572 // pseudo-instructions.
573 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
575 /// This is just the offset part of iaddr, used for preinc.
576 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
578 //===----------------------------------------------------------------------===//
579 // PowerPC Instruction Predicate Definitions.
580 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
581 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
582 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
584 //===----------------------------------------------------------------------===//
585 // PowerPC Multiclass Definitions.
587 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
588 string asmbase, string asmstr, InstrItinClass itin,
590 let BaseName = asmbase in {
591 def NAME : XForm_6<opcode, xo, OOL, IOL,
592 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
593 pattern>, RecFormRel;
595 def o : XForm_6<opcode, xo, OOL, IOL,
596 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
597 []>, isDOT, RecFormRel;
601 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
602 string asmbase, string asmstr, InstrItinClass itin,
604 let BaseName = asmbase in {
605 let Defs = [CARRY] in
606 def NAME : XForm_6<opcode, xo, OOL, IOL,
607 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
608 pattern>, RecFormRel;
609 let Defs = [CARRY, CR0] in
610 def o : XForm_6<opcode, xo, OOL, IOL,
611 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
612 []>, isDOT, RecFormRel;
616 multiclass XForm_10r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
617 string asmbase, string asmstr, InstrItinClass itin,
619 let BaseName = asmbase in {
620 def NAME : XForm_10<opcode, xo, OOL, IOL,
621 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
622 pattern>, RecFormRel;
624 def o : XForm_10<opcode, xo, OOL, IOL,
625 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
626 []>, isDOT, RecFormRel;
630 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
631 string asmbase, string asmstr, InstrItinClass itin,
633 let BaseName = asmbase in {
634 let Defs = [CARRY] in
635 def NAME : XForm_10<opcode, xo, OOL, IOL,
636 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
637 pattern>, RecFormRel;
638 let Defs = [CARRY, CR0] in
639 def o : XForm_10<opcode, xo, OOL, IOL,
640 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
641 []>, isDOT, RecFormRel;
645 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
646 string asmbase, string asmstr, InstrItinClass itin,
648 let BaseName = asmbase in {
649 def NAME : XForm_11<opcode, xo, OOL, IOL,
650 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
651 pattern>, RecFormRel;
653 def o : XForm_11<opcode, xo, OOL, IOL,
654 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
655 []>, isDOT, RecFormRel;
659 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
660 string asmbase, string asmstr, InstrItinClass itin,
662 let BaseName = asmbase in {
663 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
664 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
665 pattern>, RecFormRel;
667 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
668 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
669 []>, isDOT, RecFormRel;
673 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
674 string asmbase, string asmstr, InstrItinClass itin,
676 let BaseName = asmbase in {
677 let Defs = [CARRY] in
678 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
679 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
680 pattern>, RecFormRel;
681 let Defs = [CARRY, CR0] in
682 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
683 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
684 []>, isDOT, RecFormRel;
688 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
689 string asmbase, string asmstr, InstrItinClass itin,
691 let BaseName = asmbase in {
692 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
693 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
694 pattern>, RecFormRel;
696 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
697 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
698 []>, isDOT, RecFormRel;
702 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
703 string asmbase, string asmstr, InstrItinClass itin,
705 let BaseName = asmbase in {
706 let Defs = [CARRY] in
707 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
708 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
709 pattern>, RecFormRel;
710 let Defs = [CARRY, CR0] in
711 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
712 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
713 []>, isDOT, RecFormRel;
717 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
718 string asmbase, string asmstr, InstrItinClass itin,
720 let BaseName = asmbase in {
721 def NAME : MForm_2<opcode, OOL, IOL,
722 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
723 pattern>, RecFormRel;
725 def o : MForm_2<opcode, OOL, IOL,
726 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
727 []>, isDOT, RecFormRel;
731 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
732 string asmbase, string asmstr, InstrItinClass itin,
734 let BaseName = asmbase in {
735 def NAME : MDForm_1<opcode, xo, OOL, IOL,
736 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
737 pattern>, RecFormRel;
739 def o : MDForm_1<opcode, xo, OOL, IOL,
740 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
741 []>, isDOT, RecFormRel;
745 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
746 string asmbase, string asmstr, InstrItinClass itin,
748 let BaseName = asmbase in {
749 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
750 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
751 pattern>, RecFormRel;
753 def o : MDSForm_1<opcode, xo, OOL, IOL,
754 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
755 []>, isDOT, RecFormRel;
759 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
760 string asmbase, string asmstr, InstrItinClass itin,
762 let BaseName = asmbase in {
763 let Defs = [CARRY] in
764 def NAME : XSForm_1<opcode, xo, OOL, IOL,
765 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
766 pattern>, RecFormRel;
767 let Defs = [CARRY, CR0] in
768 def o : XSForm_1<opcode, xo, OOL, IOL,
769 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
770 []>, isDOT, RecFormRel;
774 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
775 string asmbase, string asmstr, InstrItinClass itin,
777 let BaseName = asmbase in {
778 def NAME : XForm_26<opcode, xo, OOL, IOL,
779 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
780 pattern>, RecFormRel;
782 def o : XForm_26<opcode, xo, OOL, IOL,
783 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
784 []>, isDOT, RecFormRel;
788 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
789 string asmbase, string asmstr, InstrItinClass itin,
791 let BaseName = asmbase in {
792 def NAME : AForm_1<opcode, xo, OOL, IOL,
793 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
794 pattern>, RecFormRel;
796 def o : AForm_1<opcode, xo, OOL, IOL,
797 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
798 []>, isDOT, RecFormRel;
802 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
803 string asmbase, string asmstr, InstrItinClass itin,
805 let BaseName = asmbase in {
806 def NAME : AForm_2<opcode, xo, OOL, IOL,
807 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
808 pattern>, RecFormRel;
810 def o : AForm_2<opcode, xo, OOL, IOL,
811 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
812 []>, isDOT, RecFormRel;
816 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
817 string asmbase, string asmstr, InstrItinClass itin,
819 let BaseName = asmbase in {
820 def NAME : AForm_3<opcode, xo, OOL, IOL,
821 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
822 pattern>, RecFormRel;
824 def o : AForm_3<opcode, xo, OOL, IOL,
825 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
826 []>, isDOT, RecFormRel;
830 //===----------------------------------------------------------------------===//
831 // PowerPC Instruction Definitions.
833 // Pseudo-instructions:
835 let hasCtrlDep = 1 in {
836 let Defs = [R1], Uses = [R1] in {
837 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
838 [(callseq_start timm:$amt)]>;
839 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
840 [(callseq_end timm:$amt1, timm:$amt2)]>;
843 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
844 "UPDATE_VRSAVE $rD, $rS", []>;
847 let Defs = [R1], Uses = [R1] in
848 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
850 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
852 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
853 // instruction selection into a branch sequence.
854 let usesCustomInserter = 1, // Expanded after instruction selection.
855 PPC970_Single = 1 in {
856 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
857 // because either operand might become the first operand in an isel, and
858 // that operand cannot be r0.
859 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
860 gprc_nor0:$T, gprc_nor0:$F,
861 i32imm:$BROPC), "#SELECT_CC_I4",
863 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
864 g8rc_nox0:$T, g8rc_nox0:$F,
865 i32imm:$BROPC), "#SELECT_CC_I8",
867 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
868 i32imm:$BROPC), "#SELECT_CC_F4",
870 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
871 i32imm:$BROPC), "#SELECT_CC_F8",
873 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
874 i32imm:$BROPC), "#SELECT_CC_VRRC",
878 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
879 // scavenge a register for it.
881 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
884 // RESTORE_CR - Indicate that we're restoring the CR register (previously
885 // spilled), so we'll need to scavenge a register for it.
887 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
890 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
891 let isReturn = 1, Uses = [LR, RM] in
892 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", BrB,
894 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
895 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
897 let isCodeGenOnly = 1 in
898 def BCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
899 "b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>;
904 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
907 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
908 let isBarrier = 1 in {
909 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
912 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
916 // BCC represents an arbitrary conditional branch on a predicate.
917 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
918 // a two-value operand where a dag node expects two operands. :(
919 let isCodeGenOnly = 1 in {
920 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
921 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
922 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
923 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
924 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
926 let isReturn = 1, Uses = [LR, RM] in
927 def BCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
928 "b${cond:cc}lr${cond:pm} ${cond:reg}", BrB, []>;
931 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
932 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
934 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
936 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
938 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
940 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
942 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
946 let Defs = [CTR], Uses = [CTR] in {
947 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
949 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
951 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
953 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
955 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
957 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
959 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
961 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
963 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
965 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
967 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
969 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
974 // The unconditional BCL used by the SjLj setjmp code.
975 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
976 let Defs = [LR], Uses = [RM] in {
977 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
982 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
983 // Convenient aliases for call instructions
985 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
986 "bl $func", BrB, []>; // See Pat patterns below.
987 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
988 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
990 let isCodeGenOnly = 1 in {
991 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
992 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
993 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
994 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
997 let Uses = [CTR, RM] in {
998 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
999 "bctrl", BrB, [(PPCbctrl)]>,
1000 Requires<[In32BitMode]>;
1002 let isCodeGenOnly = 1 in
1003 def BCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1004 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>;
1006 let Uses = [LR, RM] in {
1007 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1010 let isCodeGenOnly = 1 in
1011 def BCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1012 "b${cond:cc}lrl${cond:pm} ${cond:reg}", BrB, []>;
1014 let Defs = [CTR], Uses = [CTR, RM] in {
1015 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1017 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1019 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1021 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1023 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1025 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1027 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1029 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1031 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1033 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1035 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1037 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1040 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1041 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1043 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1044 "bdnzlrl", BrB, []>;
1045 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1046 "bdzlrl+", BrB, []>;
1047 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1048 "bdnzlrl+", BrB, []>;
1049 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1050 "bdzlrl-", BrB, []>;
1051 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1052 "bdnzlrl-", BrB, []>;
1056 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1057 def TCRETURNdi :Pseudo< (outs),
1058 (ins calltarget:$dst, i32imm:$offset),
1059 "#TC_RETURNd $dst $offset",
1063 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1064 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1065 "#TC_RETURNa $func $offset",
1066 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1068 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1069 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1070 "#TC_RETURNr $dst $offset",
1074 let isCodeGenOnly = 1 in {
1076 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1077 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1078 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
1079 Requires<[In32BitMode]>;
1081 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1082 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1083 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1087 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1088 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1089 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1095 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1096 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1097 "#EH_SJLJ_SETJMP32",
1098 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1099 Requires<[In32BitMode]>;
1100 let isTerminator = 1 in
1101 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1102 "#EH_SJLJ_LONGJMP32",
1103 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1104 Requires<[In32BitMode]>;
1107 let isBranch = 1, isTerminator = 1 in {
1108 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1109 "#EH_SjLj_Setup\t$dst", []>;
1113 let PPC970_Unit = 7 in {
1114 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1115 "sc $lev", BrB, [(PPCsc (i32 imm:$lev))]>;
1118 // DCB* instructions.
1119 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
1120 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1121 PPC970_DGroup_Single;
1122 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
1123 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1124 PPC970_DGroup_Single;
1125 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
1126 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1127 PPC970_DGroup_Single;
1128 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
1129 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1130 PPC970_DGroup_Single;
1131 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
1132 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1133 PPC970_DGroup_Single;
1134 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
1135 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1136 PPC970_DGroup_Single;
1137 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
1138 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1139 PPC970_DGroup_Single;
1140 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
1141 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1142 PPC970_DGroup_Single;
1144 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1145 (DCBT xoaddr:$dst)>;
1147 // Atomic operations
1148 let usesCustomInserter = 1 in {
1149 let Defs = [CR0] in {
1150 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1151 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1152 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1153 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1154 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1155 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1156 def ATOMIC_LOAD_AND_I8 : Pseudo<
1157 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1158 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1159 def ATOMIC_LOAD_OR_I8 : Pseudo<
1160 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1161 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1162 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1163 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1164 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1165 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1166 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1167 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1168 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1169 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1170 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1171 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1172 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1173 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1174 def ATOMIC_LOAD_AND_I16 : Pseudo<
1175 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1176 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1177 def ATOMIC_LOAD_OR_I16 : Pseudo<
1178 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1179 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1180 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1181 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1182 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1183 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1184 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1185 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1186 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1187 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1188 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1189 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1190 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1191 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1192 def ATOMIC_LOAD_AND_I32 : Pseudo<
1193 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1194 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1195 def ATOMIC_LOAD_OR_I32 : Pseudo<
1196 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1197 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1198 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1199 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1200 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1201 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1202 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1203 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1205 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1206 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1207 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1208 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1209 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1210 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1211 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1212 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1213 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1215 def ATOMIC_SWAP_I8 : Pseudo<
1216 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1217 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1218 def ATOMIC_SWAP_I16 : Pseudo<
1219 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1220 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1221 def ATOMIC_SWAP_I32 : Pseudo<
1222 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1223 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1227 // Instructions to support atomic operations
1228 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1229 "lwarx $rD, $src", LdStLWARX,
1230 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1233 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1234 "stwcx. $rS, $dst", LdStSTWCX,
1235 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1238 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1239 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
1241 //===----------------------------------------------------------------------===//
1242 // PPC32 Load Instructions.
1245 // Unindexed (r+i) Loads.
1246 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1247 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1248 "lbz $rD, $src", LdStLoad,
1249 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1250 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1251 "lha $rD, $src", LdStLHA,
1252 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1253 PPC970_DGroup_Cracked;
1254 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1255 "lhz $rD, $src", LdStLoad,
1256 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1257 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1258 "lwz $rD, $src", LdStLoad,
1259 [(set i32:$rD, (load iaddr:$src))]>;
1261 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1262 "lfs $rD, $src", LdStLFD,
1263 [(set f32:$rD, (load iaddr:$src))]>;
1264 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1265 "lfd $rD, $src", LdStLFD,
1266 [(set f64:$rD, (load iaddr:$src))]>;
1269 // Unindexed (r+i) Loads with Update (preinc).
1270 let mayLoad = 1, neverHasSideEffects = 1 in {
1271 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1272 "lbzu $rD, $addr", LdStLoadUpd,
1273 []>, RegConstraint<"$addr.reg = $ea_result">,
1274 NoEncode<"$ea_result">;
1276 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1277 "lhau $rD, $addr", LdStLHAU,
1278 []>, RegConstraint<"$addr.reg = $ea_result">,
1279 NoEncode<"$ea_result">;
1281 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1282 "lhzu $rD, $addr", LdStLoadUpd,
1283 []>, RegConstraint<"$addr.reg = $ea_result">,
1284 NoEncode<"$ea_result">;
1286 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1287 "lwzu $rD, $addr", LdStLoadUpd,
1288 []>, RegConstraint<"$addr.reg = $ea_result">,
1289 NoEncode<"$ea_result">;
1291 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1292 "lfsu $rD, $addr", LdStLFDU,
1293 []>, RegConstraint<"$addr.reg = $ea_result">,
1294 NoEncode<"$ea_result">;
1296 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1297 "lfdu $rD, $addr", LdStLFDU,
1298 []>, RegConstraint<"$addr.reg = $ea_result">,
1299 NoEncode<"$ea_result">;
1302 // Indexed (r+r) Loads with Update (preinc).
1303 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1305 "lbzux $rD, $addr", LdStLoadUpd,
1306 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1307 NoEncode<"$ea_result">;
1309 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1311 "lhaux $rD, $addr", LdStLHAU,
1312 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1313 NoEncode<"$ea_result">;
1315 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1317 "lhzux $rD, $addr", LdStLoadUpd,
1318 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1319 NoEncode<"$ea_result">;
1321 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1323 "lwzux $rD, $addr", LdStLoadUpd,
1324 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1325 NoEncode<"$ea_result">;
1327 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1329 "lfsux $rD, $addr", LdStLFDU,
1330 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1331 NoEncode<"$ea_result">;
1333 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1335 "lfdux $rD, $addr", LdStLFDU,
1336 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1337 NoEncode<"$ea_result">;
1341 // Indexed (r+r) Loads.
1343 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1344 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1345 "lbzx $rD, $src", LdStLoad,
1346 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1347 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1348 "lhax $rD, $src", LdStLHA,
1349 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1350 PPC970_DGroup_Cracked;
1351 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1352 "lhzx $rD, $src", LdStLoad,
1353 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1354 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1355 "lwzx $rD, $src", LdStLoad,
1356 [(set i32:$rD, (load xaddr:$src))]>;
1359 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1360 "lhbrx $rD, $src", LdStLoad,
1361 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1362 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1363 "lwbrx $rD, $src", LdStLoad,
1364 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1366 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1367 "lfsx $frD, $src", LdStLFD,
1368 [(set f32:$frD, (load xaddr:$src))]>;
1369 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1370 "lfdx $frD, $src", LdStLFD,
1371 [(set f64:$frD, (load xaddr:$src))]>;
1373 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1374 "lfiwax $frD, $src", LdStLFD,
1375 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1376 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1377 "lfiwzx $frD, $src", LdStLFD,
1378 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1381 //===----------------------------------------------------------------------===//
1382 // PPC32 Store Instructions.
1385 // Unindexed (r+i) Stores.
1386 let PPC970_Unit = 2 in {
1387 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1388 "stb $rS, $src", LdStStore,
1389 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1390 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1391 "sth $rS, $src", LdStStore,
1392 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1393 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1394 "stw $rS, $src", LdStStore,
1395 [(store i32:$rS, iaddr:$src)]>;
1396 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1397 "stfs $rS, $dst", LdStSTFD,
1398 [(store f32:$rS, iaddr:$dst)]>;
1399 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1400 "stfd $rS, $dst", LdStSTFD,
1401 [(store f64:$rS, iaddr:$dst)]>;
1404 // Unindexed (r+i) Stores with Update (preinc).
1405 let PPC970_Unit = 2, mayStore = 1 in {
1406 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1407 "stbu $rS, $dst", LdStStoreUpd, []>,
1408 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1409 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1410 "sthu $rS, $dst", LdStStoreUpd, []>,
1411 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1412 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1413 "stwu $rS, $dst", LdStStoreUpd, []>,
1414 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1415 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1416 "stfsu $rS, $dst", LdStSTFDU, []>,
1417 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1418 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1419 "stfdu $rS, $dst", LdStSTFDU, []>,
1420 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1423 // Patterns to match the pre-inc stores. We can't put the patterns on
1424 // the instruction definitions directly as ISel wants the address base
1425 // and offset to be separate operands, not a single complex operand.
1426 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1427 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1428 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1429 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1430 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1431 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1432 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1433 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1434 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1435 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1437 // Indexed (r+r) Stores.
1438 let PPC970_Unit = 2 in {
1439 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1440 "stbx $rS, $dst", LdStStore,
1441 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1442 PPC970_DGroup_Cracked;
1443 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1444 "sthx $rS, $dst", LdStStore,
1445 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1446 PPC970_DGroup_Cracked;
1447 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1448 "stwx $rS, $dst", LdStStore,
1449 [(store i32:$rS, xaddr:$dst)]>,
1450 PPC970_DGroup_Cracked;
1452 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1453 "sthbrx $rS, $dst", LdStStore,
1454 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1455 PPC970_DGroup_Cracked;
1456 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1457 "stwbrx $rS, $dst", LdStStore,
1458 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1459 PPC970_DGroup_Cracked;
1461 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1462 "stfiwx $frS, $dst", LdStSTFD,
1463 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1465 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1466 "stfsx $frS, $dst", LdStSTFD,
1467 [(store f32:$frS, xaddr:$dst)]>;
1468 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1469 "stfdx $frS, $dst", LdStSTFD,
1470 [(store f64:$frS, xaddr:$dst)]>;
1473 // Indexed (r+r) Stores with Update (preinc).
1474 let PPC970_Unit = 2, mayStore = 1 in {
1475 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1476 "stbux $rS, $dst", LdStStoreUpd, []>,
1477 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1478 PPC970_DGroup_Cracked;
1479 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1480 "sthux $rS, $dst", LdStStoreUpd, []>,
1481 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1482 PPC970_DGroup_Cracked;
1483 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1484 "stwux $rS, $dst", LdStStoreUpd, []>,
1485 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1486 PPC970_DGroup_Cracked;
1487 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1488 "stfsux $rS, $dst", LdStSTFDU, []>,
1489 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1490 PPC970_DGroup_Cracked;
1491 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1492 "stfdux $rS, $dst", LdStSTFDU, []>,
1493 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1494 PPC970_DGroup_Cracked;
1497 // Patterns to match the pre-inc stores. We can't put the patterns on
1498 // the instruction definitions directly as ISel wants the address base
1499 // and offset to be separate operands, not a single complex operand.
1500 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1501 (STBUX $rS, $ptrreg, $ptroff)>;
1502 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1503 (STHUX $rS, $ptrreg, $ptroff)>;
1504 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1505 (STWUX $rS, $ptrreg, $ptroff)>;
1506 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1507 (STFSUX $rS, $ptrreg, $ptroff)>;
1508 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1509 (STFDUX $rS, $ptrreg, $ptroff)>;
1511 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1512 "sync $L", LdStSync, []>;
1513 def : Pat<(int_ppc_sync), (SYNC 0)>;
1515 //===----------------------------------------------------------------------===//
1516 // PPC32 Arithmetic Instructions.
1519 let PPC970_Unit = 1 in { // FXU Operations.
1520 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1521 "addi $rD, $rA, $imm", IntSimple,
1522 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1523 let BaseName = "addic" in {
1524 let Defs = [CARRY] in
1525 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1526 "addic $rD, $rA, $imm", IntGeneral,
1527 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1528 RecFormRel, PPC970_DGroup_Cracked;
1529 let Defs = [CARRY, CR0] in
1530 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1531 "addic. $rD, $rA, $imm", IntGeneral,
1532 []>, isDOT, RecFormRel;
1534 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1535 "addis $rD, $rA, $imm", IntSimple,
1536 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1537 let isCodeGenOnly = 1 in
1538 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1539 "la $rD, $sym($rA)", IntGeneral,
1540 [(set i32:$rD, (add i32:$rA,
1541 (PPClo tglobaladdr:$sym, 0)))]>;
1542 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1543 "mulli $rD, $rA, $imm", IntMulLI,
1544 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1545 let Defs = [CARRY] in
1546 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1547 "subfic $rD, $rA, $imm", IntGeneral,
1548 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1550 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1551 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1552 "li $rD, $imm", IntSimple,
1553 [(set i32:$rD, imm32SExt16:$imm)]>;
1554 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1555 "lis $rD, $imm", IntSimple,
1556 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1560 let PPC970_Unit = 1 in { // FXU Operations.
1561 let Defs = [CR0] in {
1562 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1563 "andi. $dst, $src1, $src2", IntGeneral,
1564 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1566 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1567 "andis. $dst, $src1, $src2", IntGeneral,
1568 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1571 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1572 "ori $dst, $src1, $src2", IntSimple,
1573 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1574 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1575 "oris $dst, $src1, $src2", IntSimple,
1576 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1577 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1578 "xori $dst, $src1, $src2", IntSimple,
1579 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1580 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1581 "xoris $dst, $src1, $src2", IntSimple,
1582 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1583 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
1585 let isCompare = 1, neverHasSideEffects = 1 in {
1586 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1587 "cmpwi $crD, $rA, $imm", IntCompare>;
1588 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1589 "cmplwi $dst, $src1, $src2", IntCompare>;
1593 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1594 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1595 "nand", "$rA, $rS, $rB", IntSimple,
1596 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1597 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1598 "and", "$rA, $rS, $rB", IntSimple,
1599 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1600 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1601 "andc", "$rA, $rS, $rB", IntSimple,
1602 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1603 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1604 "or", "$rA, $rS, $rB", IntSimple,
1605 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1606 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1607 "nor", "$rA, $rS, $rB", IntSimple,
1608 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1609 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1610 "orc", "$rA, $rS, $rB", IntSimple,
1611 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1612 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1613 "eqv", "$rA, $rS, $rB", IntSimple,
1614 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1615 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1616 "xor", "$rA, $rS, $rB", IntSimple,
1617 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1618 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1619 "slw", "$rA, $rS, $rB", IntGeneral,
1620 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1621 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1622 "srw", "$rA, $rS, $rB", IntGeneral,
1623 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1624 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1625 "sraw", "$rA, $rS, $rB", IntShift,
1626 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1629 let PPC970_Unit = 1 in { // FXU Operations.
1630 let neverHasSideEffects = 1 in {
1631 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1632 "srawi", "$rA, $rS, $SH", IntShift,
1633 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1634 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1635 "cntlzw", "$rA, $rS", IntGeneral,
1636 [(set i32:$rA, (ctlz i32:$rS))]>;
1637 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1638 "extsb", "$rA, $rS", IntSimple,
1639 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1640 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1641 "extsh", "$rA, $rS", IntSimple,
1642 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1644 let isCompare = 1, neverHasSideEffects = 1 in {
1645 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1646 "cmpw $crD, $rA, $rB", IntCompare>;
1647 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1648 "cmplw $crD, $rA, $rB", IntCompare>;
1651 let PPC970_Unit = 3 in { // FPU Operations.
1652 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1653 // "fcmpo $crD, $fA, $fB", FPCompare>;
1654 let isCompare = 1, neverHasSideEffects = 1 in {
1655 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1656 "fcmpu $crD, $fA, $fB", FPCompare>;
1657 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1658 "fcmpu $crD, $fA, $fB", FPCompare>;
1661 let Uses = [RM] in {
1662 let neverHasSideEffects = 1 in {
1663 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1664 "fctiwz", "$frD, $frB", FPGeneral,
1665 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1667 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1668 "frsp", "$frD, $frB", FPGeneral,
1669 [(set f32:$frD, (fround f64:$frB))]>;
1671 // The frin -> nearbyint mapping is valid only in fast-math mode.
1672 let Interpretation64Bit = 1 in
1673 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1674 "frin", "$frD, $frB", FPGeneral,
1675 [(set f64:$frD, (fnearbyint f64:$frB))]>;
1676 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1677 "frin", "$frD, $frB", FPGeneral,
1678 [(set f32:$frD, (fnearbyint f32:$frB))]>;
1681 // These pseudos expand to rint but also set FE_INEXACT when the result does
1682 // not equal the argument.
1683 let usesCustomInserter = 1, Defs = [RM] in { // FIXME: Model FPSCR!
1684 def FRINDrint : Pseudo<(outs f8rc:$frD), (ins f8rc:$frB),
1685 "#FRINDrint", [(set f64:$frD, (frint f64:$frB))]>;
1686 def FRINSrint : Pseudo<(outs f4rc:$frD), (ins f4rc:$frB),
1687 "#FRINSrint", [(set f32:$frD, (frint f32:$frB))]>;
1690 let neverHasSideEffects = 1 in {
1691 let Interpretation64Bit = 1 in
1692 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1693 "frip", "$frD, $frB", FPGeneral,
1694 [(set f64:$frD, (fceil f64:$frB))]>;
1695 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1696 "frip", "$frD, $frB", FPGeneral,
1697 [(set f32:$frD, (fceil f32:$frB))]>;
1698 let Interpretation64Bit = 1 in
1699 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1700 "friz", "$frD, $frB", FPGeneral,
1701 [(set f64:$frD, (ftrunc f64:$frB))]>;
1702 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1703 "friz", "$frD, $frB", FPGeneral,
1704 [(set f32:$frD, (ftrunc f32:$frB))]>;
1705 let Interpretation64Bit = 1 in
1706 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1707 "frim", "$frD, $frB", FPGeneral,
1708 [(set f64:$frD, (ffloor f64:$frB))]>;
1709 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1710 "frim", "$frD, $frB", FPGeneral,
1711 [(set f32:$frD, (ffloor f32:$frB))]>;
1713 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1714 "fsqrt", "$frD, $frB", FPSqrt,
1715 [(set f64:$frD, (fsqrt f64:$frB))]>;
1716 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1717 "fsqrts", "$frD, $frB", FPSqrt,
1718 [(set f32:$frD, (fsqrt f32:$frB))]>;
1723 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1724 /// often coalesced away and we don't want the dispatch group builder to think
1725 /// that they will fill slots (which could cause the load of a LSU reject to
1726 /// sneak into a d-group with a store).
1727 let neverHasSideEffects = 1 in
1728 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1729 "fmr", "$frD, $frB", FPGeneral,
1730 []>, // (set f32:$frD, f32:$frB)
1733 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1734 // These are artificially split into two different forms, for 4/8 byte FP.
1735 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1736 "fabs", "$frD, $frB", FPGeneral,
1737 [(set f32:$frD, (fabs f32:$frB))]>;
1738 let Interpretation64Bit = 1 in
1739 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1740 "fabs", "$frD, $frB", FPGeneral,
1741 [(set f64:$frD, (fabs f64:$frB))]>;
1742 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1743 "fnabs", "$frD, $frB", FPGeneral,
1744 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1745 let Interpretation64Bit = 1 in
1746 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1747 "fnabs", "$frD, $frB", FPGeneral,
1748 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1749 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1750 "fneg", "$frD, $frB", FPGeneral,
1751 [(set f32:$frD, (fneg f32:$frB))]>;
1752 let Interpretation64Bit = 1 in
1753 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1754 "fneg", "$frD, $frB", FPGeneral,
1755 [(set f64:$frD, (fneg f64:$frB))]>;
1757 // Reciprocal estimates.
1758 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1759 "fre", "$frD, $frB", FPGeneral,
1760 [(set f64:$frD, (PPCfre f64:$frB))]>;
1761 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1762 "fres", "$frD, $frB", FPGeneral,
1763 [(set f32:$frD, (PPCfre f32:$frB))]>;
1764 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1765 "frsqrte", "$frD, $frB", FPGeneral,
1766 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1767 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
1768 "frsqrtes", "$frD, $frB", FPGeneral,
1769 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1772 // XL-Form instructions. condition register logical ops.
1774 let neverHasSideEffects = 1 in
1775 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
1776 "mcrf $BF, $BFA", BrMCR>,
1777 PPC970_DGroup_First, PPC970_Unit_CRU;
1779 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
1780 (ins crbitrc:$CRA, crbitrc:$CRB),
1781 "creqv $CRD, $CRA, $CRB", BrCR,
1784 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
1785 (ins crbitrc:$CRA, crbitrc:$CRB),
1786 "cror $CRD, $CRA, $CRB", BrCR,
1789 let isCodeGenOnly = 1 in {
1790 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
1791 "creqv $dst, $dst, $dst", BrCR,
1794 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
1795 "crxor $dst, $dst, $dst", BrCR,
1798 let Defs = [CR1EQ], CRD = 6 in {
1799 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1800 "creqv 6, 6, 6", BrCR,
1803 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1804 "crxor 6, 6, 6", BrCR,
1809 // XFX-Form instructions. Instructions that deal with SPRs.
1811 let Uses = [CTR] in {
1812 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
1813 "mfctr $rT", SprMFSPR>,
1814 PPC970_DGroup_First, PPC970_Unit_FXU;
1816 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
1817 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1818 "mtctr $rS", SprMTSPR>,
1819 PPC970_DGroup_First, PPC970_Unit_FXU;
1821 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
1822 let Pattern = [(int_ppc_mtctr i32:$rS)] in
1823 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1824 "mtctr $rS", SprMTSPR>,
1825 PPC970_DGroup_First, PPC970_Unit_FXU;
1828 let Defs = [LR] in {
1829 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
1830 "mtlr $rS", SprMTSPR>,
1831 PPC970_DGroup_First, PPC970_Unit_FXU;
1833 let Uses = [LR] in {
1834 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
1835 "mflr $rT", SprMFSPR>,
1836 PPC970_DGroup_First, PPC970_Unit_FXU;
1839 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1840 // a GPR on the PPC970. As such, copies in and out have the same performance
1841 // characteristics as an OR instruction.
1842 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
1843 "mtspr 256, $rS", IntGeneral>,
1844 PPC970_DGroup_Single, PPC970_Unit_FXU;
1845 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
1846 "mfspr $rT, 256", IntGeneral>,
1847 PPC970_DGroup_First, PPC970_Unit_FXU;
1849 let isCodeGenOnly = 1 in {
1850 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
1851 (outs VRSAVERC:$reg), (ins gprc:$rS),
1852 "mtspr 256, $rS", IntGeneral>,
1853 PPC970_DGroup_Single, PPC970_Unit_FXU;
1854 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
1855 (ins VRSAVERC:$reg),
1856 "mfspr $rT, 256", IntGeneral>,
1857 PPC970_DGroup_First, PPC970_Unit_FXU;
1860 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
1861 // so we'll need to scavenge a register for it.
1863 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
1864 "#SPILL_VRSAVE", []>;
1866 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
1867 // spilled), so we'll need to scavenge a register for it.
1869 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
1870 "#RESTORE_VRSAVE", []>;
1872 let neverHasSideEffects = 1 in {
1873 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins gprc:$rS),
1874 "mtcrf $FXM, $rS", BrMCRX>,
1875 PPC970_MicroCode, PPC970_Unit_CRU;
1877 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1878 // declaring that here gives the local register allocator problems with this:
1880 // MFCR <kill of whatever preg got assigned to vreg>
1881 // while not declaring it breaks DeadMachineInstructionElimination.
1882 // As it turns out, in all cases where we currently use this,
1883 // we're only interested in one subregister of it. Represent this in the
1884 // instruction to keep the register allocator from becoming confused.
1886 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1887 let isCodeGenOnly = 1 in
1888 def MFCRpseud: XFXForm_3<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
1889 "#MFCRpseud", SprMFCR>,
1890 PPC970_MicroCode, PPC970_Unit_CRU;
1892 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
1893 "mfocrf $rT, $FXM", SprMFCR>,
1894 PPC970_DGroup_First, PPC970_Unit_CRU;
1895 } // neverHasSideEffects = 1
1897 let neverHasSideEffects = 1 in
1898 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
1899 "mfcr $rT", SprMFCR>,
1900 PPC970_MicroCode, PPC970_Unit_CRU;
1902 // Pseudo instruction to perform FADD in round-to-zero mode.
1903 let usesCustomInserter = 1, Uses = [RM] in {
1904 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
1905 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
1908 // The above pseudo gets expanded to make use of the following instructions
1909 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
1910 let Uses = [RM], Defs = [RM] in {
1911 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1912 "mtfsb0 $FM", IntMTFSB0, []>,
1913 PPC970_DGroup_Single, PPC970_Unit_FPU;
1914 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1915 "mtfsb1 $FM", IntMTFSB0, []>,
1916 PPC970_DGroup_Single, PPC970_Unit_FPU;
1917 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
1918 "mtfsf $FM, $rT", IntMTFSB0, []>,
1919 PPC970_DGroup_Single, PPC970_Unit_FPU;
1921 let Uses = [RM] in {
1922 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
1923 "mffs $rT", IntMFFS,
1924 [(set f64:$rT, (PPCmffs))]>,
1925 PPC970_DGroup_Single, PPC970_Unit_FPU;
1929 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1930 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1932 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1933 "add", "$rT, $rA, $rB", IntSimple,
1934 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
1935 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1936 "addc", "$rT, $rA, $rB", IntGeneral,
1937 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
1938 PPC970_DGroup_Cracked;
1939 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1940 "divw", "$rT, $rA, $rB", IntDivW,
1941 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
1942 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1943 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1944 "divwu", "$rT, $rA, $rB", IntDivW,
1945 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
1946 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1947 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1948 "mulhw", "$rT, $rA, $rB", IntMulHW,
1949 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
1950 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1951 "mulhwu", "$rT, $rA, $rB", IntMulHWU,
1952 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
1953 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1954 "mullw", "$rT, $rA, $rB", IntMulHW,
1955 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
1956 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1957 "subf", "$rT, $rA, $rB", IntGeneral,
1958 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
1959 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1960 "subfc", "$rT, $rA, $rB", IntGeneral,
1961 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
1962 PPC970_DGroup_Cracked;
1963 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
1964 "neg", "$rT, $rA", IntSimple,
1965 [(set i32:$rT, (ineg i32:$rA))]>;
1966 let Uses = [CARRY] in {
1967 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1968 "adde", "$rT, $rA, $rB", IntGeneral,
1969 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
1970 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
1971 "addme", "$rT, $rA", IntGeneral,
1972 [(set i32:$rT, (adde i32:$rA, -1))]>;
1973 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
1974 "addze", "$rT, $rA", IntGeneral,
1975 [(set i32:$rT, (adde i32:$rA, 0))]>;
1976 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1977 "subfe", "$rT, $rA, $rB", IntGeneral,
1978 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
1979 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
1980 "subfme", "$rT, $rA", IntGeneral,
1981 [(set i32:$rT, (sube -1, i32:$rA))]>;
1982 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
1983 "subfze", "$rT, $rA", IntGeneral,
1984 [(set i32:$rT, (sube 0, i32:$rA))]>;
1988 // A-Form instructions. Most of the instructions executed in the FPU are of
1991 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1992 let Uses = [RM] in {
1993 defm FMADD : AForm_1r<63, 29,
1994 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
1995 "fmadd", "$FRT, $FRA, $FRC, $FRB", FPFused,
1996 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
1997 defm FMADDS : AForm_1r<59, 29,
1998 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
1999 "fmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2000 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2001 defm FMSUB : AForm_1r<63, 28,
2002 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2003 "fmsub", "$FRT, $FRA, $FRC, $FRB", FPFused,
2005 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2006 defm FMSUBS : AForm_1r<59, 28,
2007 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2008 "fmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2010 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2011 defm FNMADD : AForm_1r<63, 31,
2012 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2013 "fnmadd", "$FRT, $FRA, $FRC, $FRB", FPFused,
2015 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2016 defm FNMADDS : AForm_1r<59, 31,
2017 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2018 "fnmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2020 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2021 defm FNMSUB : AForm_1r<63, 30,
2022 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2023 "fnmsub", "$FRT, $FRA, $FRC, $FRB", FPFused,
2024 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2025 (fneg f64:$FRB))))]>;
2026 defm FNMSUBS : AForm_1r<59, 30,
2027 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2028 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2029 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2030 (fneg f32:$FRB))))]>;
2032 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2033 // having 4 of these, force the comparison to always be an 8-byte double (code
2034 // should use an FMRSD if the input comparison value really wants to be a float)
2035 // and 4/8 byte forms for the result and operand type..
2036 let Interpretation64Bit = 1 in
2037 defm FSELD : AForm_1r<63, 23,
2038 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2039 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2040 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2041 defm FSELS : AForm_1r<63, 23,
2042 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2043 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2044 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2045 let Uses = [RM] in {
2046 defm FADD : AForm_2r<63, 21,
2047 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2048 "fadd", "$FRT, $FRA, $FRB", FPAddSub,
2049 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2050 defm FADDS : AForm_2r<59, 21,
2051 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2052 "fadds", "$FRT, $FRA, $FRB", FPGeneral,
2053 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2054 defm FDIV : AForm_2r<63, 18,
2055 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2056 "fdiv", "$FRT, $FRA, $FRB", FPDivD,
2057 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2058 defm FDIVS : AForm_2r<59, 18,
2059 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2060 "fdivs", "$FRT, $FRA, $FRB", FPDivS,
2061 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2062 defm FMUL : AForm_3r<63, 25,
2063 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2064 "fmul", "$FRT, $FRA, $FRC", FPFused,
2065 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2066 defm FMULS : AForm_3r<59, 25,
2067 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2068 "fmuls", "$FRT, $FRA, $FRC", FPGeneral,
2069 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2070 defm FSUB : AForm_2r<63, 20,
2071 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2072 "fsub", "$FRT, $FRA, $FRB", FPAddSub,
2073 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2074 defm FSUBS : AForm_2r<59, 20,
2075 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2076 "fsubs", "$FRT, $FRA, $FRB", FPGeneral,
2077 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2081 let neverHasSideEffects = 1 in {
2082 let PPC970_Unit = 1 in { // FXU Operations.
2084 def ISEL : AForm_4<31, 15,
2085 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2086 "isel $rT, $rA, $rB, $cond", IntGeneral,
2090 let PPC970_Unit = 1 in { // FXU Operations.
2091 // M-Form instructions. rotate and mask instructions.
2093 let isCommutable = 1 in {
2094 // RLWIMI can be commuted if the rotate amount is zero.
2095 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2096 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2097 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", IntRotate,
2098 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
2101 let BaseName = "rlwinm" in {
2102 def RLWINM : MForm_2<21,
2103 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2104 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
2107 def RLWINMo : MForm_2<21,
2108 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2109 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
2110 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2112 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2113 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2114 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IntGeneral,
2117 } // neverHasSideEffects = 1
2119 //===----------------------------------------------------------------------===//
2120 // PowerPC Instruction Patterns
2123 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2124 def : Pat<(i32 imm:$imm),
2125 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2127 // Implement the 'not' operation with the NOR instruction.
2128 def NOT : Pat<(not i32:$in),
2131 // ADD an arbitrary immediate.
2132 def : Pat<(add i32:$in, imm:$imm),
2133 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2134 // OR an arbitrary immediate.
2135 def : Pat<(or i32:$in, imm:$imm),
2136 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2137 // XOR an arbitrary immediate.
2138 def : Pat<(xor i32:$in, imm:$imm),
2139 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2141 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2142 (SUBFIC $in, imm:$imm)>;
2145 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2146 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2147 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2148 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2151 def : Pat<(rotl i32:$in, i32:$sh),
2152 (RLWNM $in, $sh, 0, 31)>;
2153 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2154 (RLWINM $in, imm:$imm, 0, 31)>;
2157 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2158 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2161 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2162 (BL tglobaladdr:$dst)>;
2163 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2164 (BL texternalsym:$dst)>;
2167 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2168 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2170 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2171 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2173 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2174 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2178 // Hi and Lo for Darwin Global Addresses.
2179 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2180 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2181 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2182 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2183 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2184 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2185 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2186 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2187 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2188 (ADDIS $in, tglobaltlsaddr:$g)>;
2189 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2190 (ADDI $in, tglobaltlsaddr:$g)>;
2191 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2192 (ADDIS $in, tglobaladdr:$g)>;
2193 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2194 (ADDIS $in, tconstpool:$g)>;
2195 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2196 (ADDIS $in, tjumptable:$g)>;
2197 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2198 (ADDIS $in, tblockaddress:$g)>;
2200 // Standard shifts. These are represented separately from the real shifts above
2201 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2203 def : Pat<(sra i32:$rS, i32:$rB),
2205 def : Pat<(srl i32:$rS, i32:$rB),
2207 def : Pat<(shl i32:$rS, i32:$rB),
2210 def : Pat<(zextloadi1 iaddr:$src),
2212 def : Pat<(zextloadi1 xaddr:$src),
2214 def : Pat<(extloadi1 iaddr:$src),
2216 def : Pat<(extloadi1 xaddr:$src),
2218 def : Pat<(extloadi8 iaddr:$src),
2220 def : Pat<(extloadi8 xaddr:$src),
2222 def : Pat<(extloadi16 iaddr:$src),
2224 def : Pat<(extloadi16 xaddr:$src),
2226 def : Pat<(f64 (extloadf32 iaddr:$src)),
2227 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2228 def : Pat<(f64 (extloadf32 xaddr:$src)),
2229 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2231 def : Pat<(f64 (fextend f32:$src)),
2232 (COPY_TO_REGCLASS $src, F8RC)>;
2234 def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>;
2236 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2237 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2238 (FNMSUB $A, $C, $B)>;
2239 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2240 (FNMSUB $A, $C, $B)>;
2241 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2242 (FNMSUBS $A, $C, $B)>;
2243 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2244 (FNMSUBS $A, $C, $B)>;
2246 include "PPCInstrAltivec.td"
2247 include "PPCInstr64Bit.td"
2250 //===----------------------------------------------------------------------===//
2251 // PowerPC Instructions used for assembler/disassembler only
2254 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
2255 "isync", SprISYNC, []>;
2257 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
2258 "icbi $src", LdStICBI, []>;
2260 //===----------------------------------------------------------------------===//
2261 // PowerPC Assembler Instruction Aliases
2264 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
2265 // These are aliases that require C++ handling to convert to the target
2266 // instruction, while InstAliases can be handled directly by tblgen.
2267 class PPCAsmPseudo<string asm, dag iops>
2269 let Namespace = "PPC";
2270 bit PPC64 = 0; // Default value, override with isPPC64
2272 let OutOperandList = (outs);
2273 let InOperandList = iops;
2275 let AsmString = asm;
2276 let isAsmParserOnly = 1;
2280 def : InstAlias<"sc", (SC 0)>;
2282 def : InstAlias<"sync", (SYNC 0)>;
2283 def : InstAlias<"lwsync", (SYNC 1)>;
2284 def : InstAlias<"ptesync", (SYNC 2)>;
2286 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
2288 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2289 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2291 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2292 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2294 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
2296 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
2297 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2298 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
2299 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2300 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
2301 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2302 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
2303 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2305 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2306 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2307 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2308 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2310 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
2311 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2312 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
2313 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2314 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
2315 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2316 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
2317 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2318 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
2319 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2320 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
2321 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2322 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
2323 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2324 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
2325 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2326 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
2327 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2328 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
2329 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2330 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
2331 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2332 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
2333 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2334 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
2335 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2336 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
2337 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2338 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
2339 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2340 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
2341 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2342 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
2343 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
2344 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
2345 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
2347 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
2348 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
2349 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
2350 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
2351 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
2352 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
2354 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
2355 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2356 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
2357 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2358 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
2359 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2360 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
2361 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2362 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
2363 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2364 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
2365 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2366 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
2367 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2368 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
2369 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2370 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
2371 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2372 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
2373 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2374 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
2375 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2376 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
2377 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2378 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
2379 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2380 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
2381 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2382 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
2383 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
2384 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
2385 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
2387 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
2388 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
2389 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
2390 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
2391 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
2392 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
2394 // These generic branch instruction forms are used for the assembler parser only.
2395 // Defs and Uses are conservative, since we don't know the BO value.
2396 let PPC970_Unit = 7 in {
2397 let Defs = [CTR], Uses = [CTR, RM] in {
2398 def gBC : BForm_3<16, 0, 0, (outs),
2399 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
2400 "bc $bo, $bi, $dst">;
2401 def gBCA : BForm_3<16, 1, 0, (outs),
2402 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
2403 "bca $bo, $bi, $dst">;
2405 let Defs = [LR, CTR], Uses = [CTR, RM] in {
2406 def gBCL : BForm_3<16, 0, 1, (outs),
2407 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
2408 "bcl $bo, $bi, $dst">;
2409 def gBCLA : BForm_3<16, 1, 1, (outs),
2410 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
2411 "bcla $bo, $bi, $dst">;
2413 let Defs = [CTR], Uses = [CTR, LR, RM] in
2414 def gBCLR : XLForm_2<19, 16, 0, (outs),
2415 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2416 "bclr $bo, $bi, $bh", BrB, []>;
2417 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
2418 def gBCLRL : XLForm_2<19, 16, 1, (outs),
2419 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2420 "bclrl $bo, $bi, $bh", BrB, []>;
2421 let Defs = [CTR], Uses = [CTR, LR, RM] in
2422 def gBCCTR : XLForm_2<19, 528, 0, (outs),
2423 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2424 "bcctr $bo, $bi, $bh", BrB, []>;
2425 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
2426 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
2427 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2428 "bcctrl $bo, $bi, $bh", BrB, []>;
2430 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
2431 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
2432 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
2433 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
2435 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
2436 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
2437 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
2438 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
2439 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
2440 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
2441 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
2443 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
2444 : BranchSimpleMnemonic1<name, pm, bo> {
2445 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
2446 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
2448 defm : BranchSimpleMnemonic2<"t", "", 12>;
2449 defm : BranchSimpleMnemonic2<"f", "", 4>;
2450 defm : BranchSimpleMnemonic2<"t", "-", 14>;
2451 defm : BranchSimpleMnemonic2<"f", "-", 6>;
2452 defm : BranchSimpleMnemonic2<"t", "+", 15>;
2453 defm : BranchSimpleMnemonic2<"f", "+", 7>;
2454 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
2455 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
2456 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
2457 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
2459 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
2460 def : InstAlias<"b"#name#pm#" $cc, $dst",
2461 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
2462 def : InstAlias<"b"#name#pm#" $dst",
2463 (BCC bibo, CR0, condbrtarget:$dst)>;
2465 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
2466 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
2467 def : InstAlias<"b"#name#"a"#pm#" $dst",
2468 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
2470 def : InstAlias<"b"#name#"lr"#pm#" $cc",
2471 (BCLR bibo, crrc:$cc)>;
2472 def : InstAlias<"b"#name#"lr"#pm,
2475 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
2476 (BCCTR bibo, crrc:$cc)>;
2477 def : InstAlias<"b"#name#"ctr"#pm,
2480 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
2481 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
2482 def : InstAlias<"b"#name#"l"#pm#" $dst",
2483 (BCCL bibo, CR0, condbrtarget:$dst)>;
2485 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
2486 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
2487 def : InstAlias<"b"#name#"la"#pm#" $dst",
2488 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
2490 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
2491 (BCLRL bibo, crrc:$cc)>;
2492 def : InstAlias<"b"#name#"lrl"#pm,
2495 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
2496 (BCCTRL bibo, crrc:$cc)>;
2497 def : InstAlias<"b"#name#"ctrl"#pm,
2498 (BCCTRL bibo, CR0)>;
2500 multiclass BranchExtendedMnemonic<string name, int bibo> {
2501 defm : BranchExtendedMnemonicPM<name, "", bibo>;
2502 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
2503 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
2505 defm : BranchExtendedMnemonic<"lt", 12>;
2506 defm : BranchExtendedMnemonic<"gt", 44>;
2507 defm : BranchExtendedMnemonic<"eq", 76>;
2508 defm : BranchExtendedMnemonic<"un", 108>;
2509 defm : BranchExtendedMnemonic<"so", 108>;
2510 defm : BranchExtendedMnemonic<"ge", 4>;
2511 defm : BranchExtendedMnemonic<"nl", 4>;
2512 defm : BranchExtendedMnemonic<"le", 36>;
2513 defm : BranchExtendedMnemonic<"ng", 36>;
2514 defm : BranchExtendedMnemonic<"ne", 68>;
2515 defm : BranchExtendedMnemonic<"nu", 100>;
2516 defm : BranchExtendedMnemonic<"ns", 100>;
2518 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
2519 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
2520 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
2521 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
2522 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
2523 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
2524 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
2525 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;