1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
60 def tocentry32 : Operand<iPTR> {
61 let MIOperandInfo = (ops i32imm:$imm);
64 def SDT_PPCqvfperm : SDTypeProfile<1, 3, [
65 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3>
67 def SDT_PPCqvgpci : SDTypeProfile<1, 1, [
68 SDTCisVec<0>, SDTCisInt<1>
70 def SDT_PPCqvaligni : SDTypeProfile<1, 3, [
71 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>
73 def SDT_PPCqvesplati : SDTypeProfile<1, 2, [
74 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>
77 def SDT_PPCqbflt : SDTypeProfile<1, 1, [
78 SDTCisVec<0>, SDTCisVec<1>
81 def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [
82 SDTCisVec<0>, SDTCisPtrTy<1>
85 //===----------------------------------------------------------------------===//
86 // PowerPC specific DAG Nodes.
89 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
90 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
92 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
93 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
94 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
95 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
96 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
97 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
98 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
99 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
100 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
101 [SDNPHasChain, SDNPMayStore]>;
102 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
103 [SDNPHasChain, SDNPMayLoad]>;
104 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
105 [SDNPHasChain, SDNPMayLoad]>;
107 // Extract FPSCR (not modeled at the DAG level).
108 def PPCmffs : SDNode<"PPCISD::MFFS",
109 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
111 // Perform FADD in round-to-zero mode.
112 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
115 def PPCfsel : SDNode<"PPCISD::FSEL",
116 // Type constraint for fsel.
117 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
118 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
120 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
121 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
122 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
123 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
124 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
126 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
128 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
129 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
131 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
132 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
133 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
134 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
135 def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR",
136 SDTypeProfile<1, 3, [
137 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
138 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
139 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
140 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
141 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
142 def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",
143 SDTypeProfile<1, 3, [
144 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
145 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
146 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
147 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
149 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
151 def PPCqvfperm : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>;
152 def PPCqvgpci : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>;
153 def PPCqvaligni : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>;
154 def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>;
156 def PPCqbflt : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>;
158 def PPCqvlfsb : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb,
159 [SDNPHasChain, SDNPMayLoad]>;
161 def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>;
163 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
164 // amounts. These nodes are generated by the multi-precision shift code.
165 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
166 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
167 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
169 // These are target-independent nodes, but have target-specific formats.
170 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
171 [SDNPHasChain, SDNPOutGlue]>;
172 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
173 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
175 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
176 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
177 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
179 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
180 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
182 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
183 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
184 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
185 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
187 def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",
188 SDTypeProfile<0, 1, []>,
189 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
192 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
193 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
195 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
196 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
198 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
199 SDTypeProfile<1, 1, [SDTCisInt<0>,
201 [SDNPHasChain, SDNPSideEffect]>;
202 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
203 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
204 [SDNPHasChain, SDNPSideEffect]>;
206 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
207 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
208 [SDNPHasChain, SDNPSideEffect]>;
210 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
211 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
213 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
214 [SDNPHasChain, SDNPOptInGlue]>;
216 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
217 [SDNPHasChain, SDNPMayLoad]>;
218 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
219 [SDNPHasChain, SDNPMayStore]>;
221 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
222 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
223 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
224 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
225 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
227 // Instructions to support atomic operations
228 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
229 [SDNPHasChain, SDNPMayLoad]>;
230 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
231 [SDNPHasChain, SDNPMayStore]>;
233 // Instructions to support medium and large code model
234 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
235 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
236 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
239 // Instructions to support dynamic alloca.
240 def SDTDynOp : SDTypeProfile<1, 2, []>;
241 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
243 //===----------------------------------------------------------------------===//
244 // PowerPC specific transformation functions and pattern fragments.
247 def SHL32 : SDNodeXForm<imm, [{
248 // Transformation function: 31 - imm
249 return getI32Imm(31 - N->getZExtValue());
252 def SRL32 : SDNodeXForm<imm, [{
253 // Transformation function: 32 - imm
254 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
257 def LO16 : SDNodeXForm<imm, [{
258 // Transformation function: get the low 16 bits.
259 return getI32Imm((unsigned short)N->getZExtValue());
262 def HI16 : SDNodeXForm<imm, [{
263 // Transformation function: shift the immediate value down into the low bits.
264 return getI32Imm((unsigned)N->getZExtValue() >> 16);
267 def HA16 : SDNodeXForm<imm, [{
268 // Transformation function: shift the immediate value down into the low bits.
269 signed int Val = N->getZExtValue();
270 return getI32Imm((Val - (signed short)Val) >> 16);
272 def MB : SDNodeXForm<imm, [{
273 // Transformation function: get the start bit of a mask
275 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
276 return getI32Imm(mb);
279 def ME : SDNodeXForm<imm, [{
280 // Transformation function: get the end bit of a mask
282 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
283 return getI32Imm(me);
285 def maskimm32 : PatLeaf<(imm), [{
286 // maskImm predicate - True if immediate is a run of ones.
288 if (N->getValueType(0) == MVT::i32)
289 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
294 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
295 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
296 // sign extended field. Used by instructions like 'addi'.
297 return (int32_t)Imm == (short)Imm;
299 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
300 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
301 // sign extended field. Used by instructions like 'addi'.
302 return (int64_t)Imm == (short)Imm;
304 def immZExt16 : PatLeaf<(imm), [{
305 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
306 // field. Used by instructions like 'ori'.
307 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
310 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
311 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
312 // identical in 32-bit mode, but in 64-bit mode, they return true if the
313 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
315 def imm16ShiftedZExt : PatLeaf<(imm), [{
316 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
317 // immediate are set. Used by instructions like 'xoris'.
318 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
321 def imm16ShiftedSExt : PatLeaf<(imm), [{
322 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
323 // immediate are set. Used by instructions like 'addis'. Identical to
324 // imm16ShiftedZExt in 32-bit mode.
325 if (N->getZExtValue() & 0xFFFF) return false;
326 if (N->getValueType(0) == MVT::i32)
328 // For 64-bit, make sure it is sext right.
329 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
332 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
333 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
334 // zero extended field.
335 return isUInt<32>(Imm);
338 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
339 // restricted memrix (4-aligned) constants are alignment sensitive. If these
340 // offsets are hidden behind TOC entries than the values of the lower-order
341 // bits cannot be checked directly. As a result, we need to also incorporate
342 // an alignment check into the relevant patterns.
344 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
345 return cast<LoadSDNode>(N)->getAlignment() >= 4;
347 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
348 (store node:$val, node:$ptr), [{
349 return cast<StoreSDNode>(N)->getAlignment() >= 4;
351 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
352 return cast<LoadSDNode>(N)->getAlignment() >= 4;
354 def aligned4pre_store : PatFrag<
355 (ops node:$val, node:$base, node:$offset),
356 (pre_store node:$val, node:$base, node:$offset), [{
357 return cast<StoreSDNode>(N)->getAlignment() >= 4;
360 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
361 return cast<LoadSDNode>(N)->getAlignment() < 4;
363 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
364 (store node:$val, node:$ptr), [{
365 return cast<StoreSDNode>(N)->getAlignment() < 4;
367 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
368 return cast<LoadSDNode>(N)->getAlignment() < 4;
371 //===----------------------------------------------------------------------===//
372 // PowerPC Flag Definitions.
374 class isPPC64 { bit PPC64 = 1; }
375 class isDOT { bit RC = 1; }
377 class RegConstraint<string C> {
378 string Constraints = C;
380 class NoEncode<string E> {
381 string DisableEncoding = E;
385 //===----------------------------------------------------------------------===//
386 // PowerPC Operand Definitions.
388 // In the default PowerPC assembler syntax, registers are specified simply
389 // by number, so they cannot be distinguished from immediate values (without
390 // looking at the opcode). This means that the default operand matching logic
391 // for the asm parser does not work, and we need to specify custom matchers.
392 // Since those can only be specified with RegisterOperand classes and not
393 // directly on the RegisterClass, all instructions patterns used by the asm
394 // parser need to use a RegisterOperand (instead of a RegisterClass) for
395 // all their register operands.
396 // For this purpose, we define one RegisterOperand for each RegisterClass,
397 // using the same name as the class, just in lower case.
399 def PPCRegGPRCAsmOperand : AsmOperandClass {
400 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
402 def gprc : RegisterOperand<GPRC> {
403 let ParserMatchClass = PPCRegGPRCAsmOperand;
405 def PPCRegG8RCAsmOperand : AsmOperandClass {
406 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
408 def g8rc : RegisterOperand<G8RC> {
409 let ParserMatchClass = PPCRegG8RCAsmOperand;
411 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
412 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
414 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
415 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
417 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
418 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
420 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
421 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
423 def PPCRegF8RCAsmOperand : AsmOperandClass {
424 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
426 def f8rc : RegisterOperand<F8RC> {
427 let ParserMatchClass = PPCRegF8RCAsmOperand;
429 def PPCRegF4RCAsmOperand : AsmOperandClass {
430 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
432 def f4rc : RegisterOperand<F4RC> {
433 let ParserMatchClass = PPCRegF4RCAsmOperand;
435 def PPCRegVRRCAsmOperand : AsmOperandClass {
436 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
438 def vrrc : RegisterOperand<VRRC> {
439 let ParserMatchClass = PPCRegVRRCAsmOperand;
441 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
442 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
444 def crbitrc : RegisterOperand<CRBITRC> {
445 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
447 def PPCRegCRRCAsmOperand : AsmOperandClass {
448 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
450 def crrc : RegisterOperand<CRRC> {
451 let ParserMatchClass = PPCRegCRRCAsmOperand;
454 def PPCU2ImmAsmOperand : AsmOperandClass {
455 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
456 let RenderMethod = "addImmOperands";
458 def u2imm : Operand<i32> {
459 let PrintMethod = "printU2ImmOperand";
460 let ParserMatchClass = PPCU2ImmAsmOperand;
463 def PPCU4ImmAsmOperand : AsmOperandClass {
464 let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
465 let RenderMethod = "addImmOperands";
467 def u4imm : Operand<i32> {
468 let PrintMethod = "printU4ImmOperand";
469 let ParserMatchClass = PPCU4ImmAsmOperand;
471 def PPCS5ImmAsmOperand : AsmOperandClass {
472 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
473 let RenderMethod = "addImmOperands";
475 def s5imm : Operand<i32> {
476 let PrintMethod = "printS5ImmOperand";
477 let ParserMatchClass = PPCS5ImmAsmOperand;
478 let DecoderMethod = "decodeSImmOperand<5>";
480 def PPCU5ImmAsmOperand : AsmOperandClass {
481 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
482 let RenderMethod = "addImmOperands";
484 def u5imm : Operand<i32> {
485 let PrintMethod = "printU5ImmOperand";
486 let ParserMatchClass = PPCU5ImmAsmOperand;
487 let DecoderMethod = "decodeUImmOperand<5>";
489 def PPCU6ImmAsmOperand : AsmOperandClass {
490 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
491 let RenderMethod = "addImmOperands";
493 def u6imm : Operand<i32> {
494 let PrintMethod = "printU6ImmOperand";
495 let ParserMatchClass = PPCU6ImmAsmOperand;
496 let DecoderMethod = "decodeUImmOperand<6>";
498 def PPCU12ImmAsmOperand : AsmOperandClass {
499 let Name = "U12Imm"; let PredicateMethod = "isU12Imm";
500 let RenderMethod = "addImmOperands";
502 def u12imm : Operand<i32> {
503 let PrintMethod = "printU12ImmOperand";
504 let ParserMatchClass = PPCU12ImmAsmOperand;
505 let DecoderMethod = "decodeUImmOperand<12>";
507 def PPCS16ImmAsmOperand : AsmOperandClass {
508 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
509 let RenderMethod = "addS16ImmOperands";
511 def s16imm : Operand<i32> {
512 let PrintMethod = "printS16ImmOperand";
513 let EncoderMethod = "getImm16Encoding";
514 let ParserMatchClass = PPCS16ImmAsmOperand;
515 let DecoderMethod = "decodeSImmOperand<16>";
517 def PPCU16ImmAsmOperand : AsmOperandClass {
518 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
519 let RenderMethod = "addU16ImmOperands";
521 def u16imm : Operand<i32> {
522 let PrintMethod = "printU16ImmOperand";
523 let EncoderMethod = "getImm16Encoding";
524 let ParserMatchClass = PPCU16ImmAsmOperand;
525 let DecoderMethod = "decodeUImmOperand<16>";
527 def PPCS17ImmAsmOperand : AsmOperandClass {
528 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
529 let RenderMethod = "addS16ImmOperands";
531 def s17imm : Operand<i32> {
532 // This operand type is used for addis/lis to allow the assembler parser
533 // to accept immediates in the range -65536..65535 for compatibility with
534 // the GNU assembler. The operand is treated as 16-bit otherwise.
535 let PrintMethod = "printS16ImmOperand";
536 let EncoderMethod = "getImm16Encoding";
537 let ParserMatchClass = PPCS17ImmAsmOperand;
538 let DecoderMethod = "decodeSImmOperand<16>";
540 def PPCDirectBrAsmOperand : AsmOperandClass {
541 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
542 let RenderMethod = "addBranchTargetOperands";
544 def directbrtarget : Operand<OtherVT> {
545 let PrintMethod = "printBranchOperand";
546 let EncoderMethod = "getDirectBrEncoding";
547 let ParserMatchClass = PPCDirectBrAsmOperand;
549 def absdirectbrtarget : Operand<OtherVT> {
550 let PrintMethod = "printAbsBranchOperand";
551 let EncoderMethod = "getAbsDirectBrEncoding";
552 let ParserMatchClass = PPCDirectBrAsmOperand;
554 def PPCCondBrAsmOperand : AsmOperandClass {
555 let Name = "CondBr"; let PredicateMethod = "isCondBr";
556 let RenderMethod = "addBranchTargetOperands";
558 def condbrtarget : Operand<OtherVT> {
559 let PrintMethod = "printBranchOperand";
560 let EncoderMethod = "getCondBrEncoding";
561 let ParserMatchClass = PPCCondBrAsmOperand;
563 def abscondbrtarget : Operand<OtherVT> {
564 let PrintMethod = "printAbsBranchOperand";
565 let EncoderMethod = "getAbsCondBrEncoding";
566 let ParserMatchClass = PPCCondBrAsmOperand;
568 def calltarget : Operand<iPTR> {
569 let PrintMethod = "printBranchOperand";
570 let EncoderMethod = "getDirectBrEncoding";
571 let ParserMatchClass = PPCDirectBrAsmOperand;
573 def abscalltarget : Operand<iPTR> {
574 let PrintMethod = "printAbsBranchOperand";
575 let EncoderMethod = "getAbsDirectBrEncoding";
576 let ParserMatchClass = PPCDirectBrAsmOperand;
578 def PPCCRBitMaskOperand : AsmOperandClass {
579 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
581 def crbitm: Operand<i8> {
582 let PrintMethod = "printcrbitm";
583 let EncoderMethod = "get_crbitm_encoding";
584 let DecoderMethod = "decodeCRBitMOperand";
585 let ParserMatchClass = PPCCRBitMaskOperand;
588 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
589 def PPCRegGxRCNoR0Operand : AsmOperandClass {
590 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
592 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
593 let ParserMatchClass = PPCRegGxRCNoR0Operand;
595 // A version of ptr_rc usable with the asm parser.
596 def PPCRegGxRCOperand : AsmOperandClass {
597 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
599 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
600 let ParserMatchClass = PPCRegGxRCOperand;
603 def PPCDispRIOperand : AsmOperandClass {
604 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
605 let RenderMethod = "addS16ImmOperands";
607 def dispRI : Operand<iPTR> {
608 let ParserMatchClass = PPCDispRIOperand;
610 def PPCDispRIXOperand : AsmOperandClass {
611 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
612 let RenderMethod = "addImmOperands";
614 def dispRIX : Operand<iPTR> {
615 let ParserMatchClass = PPCDispRIXOperand;
617 def PPCDispSPE8Operand : AsmOperandClass {
618 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
619 let RenderMethod = "addImmOperands";
621 def dispSPE8 : Operand<iPTR> {
622 let ParserMatchClass = PPCDispSPE8Operand;
624 def PPCDispSPE4Operand : AsmOperandClass {
625 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
626 let RenderMethod = "addImmOperands";
628 def dispSPE4 : Operand<iPTR> {
629 let ParserMatchClass = PPCDispSPE4Operand;
631 def PPCDispSPE2Operand : AsmOperandClass {
632 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
633 let RenderMethod = "addImmOperands";
635 def dispSPE2 : Operand<iPTR> {
636 let ParserMatchClass = PPCDispSPE2Operand;
639 def memri : Operand<iPTR> {
640 let PrintMethod = "printMemRegImm";
641 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
642 let EncoderMethod = "getMemRIEncoding";
643 let DecoderMethod = "decodeMemRIOperands";
645 def memrr : Operand<iPTR> {
646 let PrintMethod = "printMemRegReg";
647 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
649 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
650 let PrintMethod = "printMemRegImm";
651 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
652 let EncoderMethod = "getMemRIXEncoding";
653 let DecoderMethod = "decodeMemRIXOperands";
655 def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned.
656 let PrintMethod = "printMemRegImm";
657 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
658 let EncoderMethod = "getSPE8DisEncoding";
660 def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned.
661 let PrintMethod = "printMemRegImm";
662 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
663 let EncoderMethod = "getSPE4DisEncoding";
665 def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned.
666 let PrintMethod = "printMemRegImm";
667 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
668 let EncoderMethod = "getSPE2DisEncoding";
671 // A single-register address. This is used with the SjLj
672 // pseudo-instructions.
673 def memr : Operand<iPTR> {
674 let MIOperandInfo = (ops ptr_rc:$ptrreg);
676 def PPCTLSRegOperand : AsmOperandClass {
677 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
678 let RenderMethod = "addTLSRegOperands";
680 def tlsreg32 : Operand<i32> {
681 let EncoderMethod = "getTLSRegEncoding";
682 let ParserMatchClass = PPCTLSRegOperand;
684 def tlsgd32 : Operand<i32> {}
685 def tlscall32 : Operand<i32> {
686 let PrintMethod = "printTLSCall";
687 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
688 let EncoderMethod = "getTLSCallEncoding";
691 // PowerPC Predicate operand.
692 def pred : Operand<OtherVT> {
693 let PrintMethod = "printPredicateOperand";
694 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
697 // Define PowerPC specific addressing mode.
698 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
699 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
700 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
701 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
703 // The address in a single register. This is used with the SjLj
704 // pseudo-instructions.
705 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
707 /// This is just the offset part of iaddr, used for preinc.
708 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
710 //===----------------------------------------------------------------------===//
711 // PowerPC Instruction Predicate Definitions.
712 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
713 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
714 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
715 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
716 def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
717 def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
718 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
719 def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
720 def IsE500 : Predicate<"PPCSubTarget->isE500()">;
721 def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
722 def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
724 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
725 def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">;
727 //===----------------------------------------------------------------------===//
728 // PowerPC Multiclass Definitions.
730 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
731 string asmbase, string asmstr, InstrItinClass itin,
733 let BaseName = asmbase in {
734 def NAME : XForm_6<opcode, xo, OOL, IOL,
735 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
736 pattern>, RecFormRel;
738 def o : XForm_6<opcode, xo, OOL, IOL,
739 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
740 []>, isDOT, RecFormRel;
744 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
745 string asmbase, string asmstr, InstrItinClass itin,
747 let BaseName = asmbase in {
748 let Defs = [CARRY] in
749 def NAME : XForm_6<opcode, xo, OOL, IOL,
750 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
751 pattern>, RecFormRel;
752 let Defs = [CARRY, CR0] in
753 def o : XForm_6<opcode, xo, OOL, IOL,
754 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
755 []>, isDOT, RecFormRel;
759 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
760 string asmbase, string asmstr, InstrItinClass itin,
762 let BaseName = asmbase in {
763 let Defs = [CARRY] in
764 def NAME : XForm_10<opcode, xo, OOL, IOL,
765 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
766 pattern>, RecFormRel;
767 let Defs = [CARRY, CR0] in
768 def o : XForm_10<opcode, xo, OOL, IOL,
769 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
770 []>, isDOT, RecFormRel;
774 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
775 string asmbase, string asmstr, InstrItinClass itin,
777 let BaseName = asmbase in {
778 def NAME : XForm_11<opcode, xo, OOL, IOL,
779 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
780 pattern>, RecFormRel;
782 def o : XForm_11<opcode, xo, OOL, IOL,
783 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
784 []>, isDOT, RecFormRel;
788 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
789 string asmbase, string asmstr, InstrItinClass itin,
791 let BaseName = asmbase in {
792 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
793 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
794 pattern>, RecFormRel;
796 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
797 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
798 []>, isDOT, RecFormRel;
802 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
803 string asmbase, string asmstr, InstrItinClass itin,
805 let BaseName = asmbase in {
806 let Defs = [CARRY] in
807 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
808 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
809 pattern>, RecFormRel;
810 let Defs = [CARRY, CR0] in
811 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
812 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
813 []>, isDOT, RecFormRel;
817 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
818 string asmbase, string asmstr, InstrItinClass itin,
820 let BaseName = asmbase in {
821 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
822 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
823 pattern>, RecFormRel;
825 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
826 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
827 []>, isDOT, RecFormRel;
831 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
832 string asmbase, string asmstr, InstrItinClass itin,
834 let BaseName = asmbase in {
835 let Defs = [CARRY] in
836 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
837 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
838 pattern>, RecFormRel;
839 let Defs = [CARRY, CR0] in
840 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
841 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
842 []>, isDOT, RecFormRel;
846 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
847 string asmbase, string asmstr, InstrItinClass itin,
849 let BaseName = asmbase in {
850 def NAME : MForm_2<opcode, OOL, IOL,
851 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
852 pattern>, RecFormRel;
854 def o : MForm_2<opcode, OOL, IOL,
855 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
856 []>, isDOT, RecFormRel;
860 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
861 string asmbase, string asmstr, InstrItinClass itin,
863 let BaseName = asmbase in {
864 def NAME : MDForm_1<opcode, xo, OOL, IOL,
865 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
866 pattern>, RecFormRel;
868 def o : MDForm_1<opcode, xo, OOL, IOL,
869 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
870 []>, isDOT, RecFormRel;
874 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
875 string asmbase, string asmstr, InstrItinClass itin,
877 let BaseName = asmbase in {
878 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
879 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
880 pattern>, RecFormRel;
882 def o : MDSForm_1<opcode, xo, OOL, IOL,
883 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
884 []>, isDOT, RecFormRel;
888 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
889 string asmbase, string asmstr, InstrItinClass itin,
891 let BaseName = asmbase in {
892 let Defs = [CARRY] in
893 def NAME : XSForm_1<opcode, xo, OOL, IOL,
894 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
895 pattern>, RecFormRel;
896 let Defs = [CARRY, CR0] in
897 def o : XSForm_1<opcode, xo, OOL, IOL,
898 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
899 []>, isDOT, RecFormRel;
903 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
904 string asmbase, string asmstr, InstrItinClass itin,
906 let BaseName = asmbase in {
907 def NAME : XForm_26<opcode, xo, OOL, IOL,
908 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
909 pattern>, RecFormRel;
911 def o : XForm_26<opcode, xo, OOL, IOL,
912 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
913 []>, isDOT, RecFormRel;
917 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
918 string asmbase, string asmstr, InstrItinClass itin,
920 let BaseName = asmbase in {
921 def NAME : XForm_28<opcode, xo, OOL, IOL,
922 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
923 pattern>, RecFormRel;
925 def o : XForm_28<opcode, xo, OOL, IOL,
926 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
927 []>, isDOT, RecFormRel;
931 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
932 string asmbase, string asmstr, InstrItinClass itin,
934 let BaseName = asmbase in {
935 def NAME : AForm_1<opcode, xo, OOL, IOL,
936 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
937 pattern>, RecFormRel;
939 def o : AForm_1<opcode, xo, OOL, IOL,
940 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
941 []>, isDOT, RecFormRel;
945 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
946 string asmbase, string asmstr, InstrItinClass itin,
948 let BaseName = asmbase in {
949 def NAME : AForm_2<opcode, xo, OOL, IOL,
950 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
951 pattern>, RecFormRel;
953 def o : AForm_2<opcode, xo, OOL, IOL,
954 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
955 []>, isDOT, RecFormRel;
959 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
960 string asmbase, string asmstr, InstrItinClass itin,
962 let BaseName = asmbase in {
963 def NAME : AForm_3<opcode, xo, OOL, IOL,
964 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
965 pattern>, RecFormRel;
967 def o : AForm_3<opcode, xo, OOL, IOL,
968 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
969 []>, isDOT, RecFormRel;
973 //===----------------------------------------------------------------------===//
974 // PowerPC Instruction Definitions.
976 // Pseudo-instructions:
978 let hasCtrlDep = 1 in {
979 let Defs = [R1], Uses = [R1] in {
980 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
981 [(callseq_start timm:$amt)]>;
982 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
983 [(callseq_end timm:$amt1, timm:$amt2)]>;
986 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
987 "UPDATE_VRSAVE $rD, $rS", []>;
990 let Defs = [R1], Uses = [R1] in
991 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
993 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
995 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
996 // instruction selection into a branch sequence.
997 let usesCustomInserter = 1, // Expanded after instruction selection.
998 PPC970_Single = 1 in {
999 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
1000 // because either operand might become the first operand in an isel, and
1001 // that operand cannot be r0.
1002 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
1003 gprc_nor0:$T, gprc_nor0:$F,
1004 i32imm:$BROPC), "#SELECT_CC_I4",
1006 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1007 g8rc_nox0:$T, g8rc_nox0:$F,
1008 i32imm:$BROPC), "#SELECT_CC_I8",
1010 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1011 i32imm:$BROPC), "#SELECT_CC_F4",
1013 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
1014 i32imm:$BROPC), "#SELECT_CC_F8",
1016 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1017 i32imm:$BROPC), "#SELECT_CC_VRRC",
1020 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
1021 // register bit directly.
1022 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
1023 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
1024 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
1025 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
1026 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
1027 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
1028 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
1029 f4rc:$T, f4rc:$F), "#SELECT_F4",
1030 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
1031 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
1032 f8rc:$T, f8rc:$F), "#SELECT_F8",
1033 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
1034 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1035 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
1037 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
1040 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
1041 // scavenge a register for it.
1042 let mayStore = 1 in {
1043 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
1045 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1046 "#SPILL_CRBIT", []>;
1049 // RESTORE_CR - Indicate that we're restoring the CR register (previously
1050 // spilled), so we'll need to scavenge a register for it.
1051 let mayLoad = 1 in {
1052 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1054 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1055 "#RESTORE_CRBIT", []>;
1058 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1059 let isReturn = 1, Uses = [LR, RM] in
1060 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1061 [(retflag)]>, Requires<[In32BitMode]>;
1062 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1063 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1066 let isCodeGenOnly = 1 in {
1067 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1068 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1071 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1072 "bcctr 12, $bi, 0", IIC_BrB, []>;
1073 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1074 "bcctr 4, $bi, 0", IIC_BrB, []>;
1080 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1083 def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1086 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1087 let isBarrier = 1 in {
1088 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1091 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1092 "ba $dst", IIC_BrB, []>;
1095 // BCC represents an arbitrary conditional branch on a predicate.
1096 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1097 // a two-value operand where a dag node expects two operands. :(
1098 let isCodeGenOnly = 1 in {
1099 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1100 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1101 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1102 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1103 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1105 let isReturn = 1, Uses = [LR, RM] in
1106 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1107 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1110 let isCodeGenOnly = 1 in {
1111 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1112 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1113 "bc 12, $bi, $dst">;
1115 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1116 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1119 let isReturn = 1, Uses = [LR, RM] in
1120 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1121 "bclr 12, $bi, 0", IIC_BrB, []>;
1122 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1123 "bclr 4, $bi, 0", IIC_BrB, []>;
1126 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1127 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1128 "bdzlr", IIC_BrB, []>;
1129 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1130 "bdnzlr", IIC_BrB, []>;
1131 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1132 "bdzlr+", IIC_BrB, []>;
1133 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1134 "bdnzlr+", IIC_BrB, []>;
1135 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1136 "bdzlr-", IIC_BrB, []>;
1137 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1138 "bdnzlr-", IIC_BrB, []>;
1141 let Defs = [CTR], Uses = [CTR] in {
1142 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1144 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1146 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1148 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1150 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1152 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1154 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1156 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1158 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1160 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1162 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1164 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1169 // The unconditional BCL used by the SjLj setjmp code.
1170 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1171 let Defs = [LR], Uses = [RM] in {
1172 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1173 "bcl 20, 31, $dst">;
1177 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1178 // Convenient aliases for call instructions
1179 let Uses = [RM] in {
1180 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1181 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1182 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1183 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1185 let isCodeGenOnly = 1 in {
1186 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1187 "bl $func", IIC_BrB, []>;
1188 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1189 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1190 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1191 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1193 def BCL : BForm_4<16, 12, 0, 1, (outs),
1194 (ins crbitrc:$bi, condbrtarget:$dst),
1195 "bcl 12, $bi, $dst">;
1196 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1197 (ins crbitrc:$bi, condbrtarget:$dst),
1198 "bcl 4, $bi, $dst">;
1201 let Uses = [CTR, RM] in {
1202 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1203 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1204 Requires<[In32BitMode]>;
1206 let isCodeGenOnly = 1 in {
1207 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1208 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1211 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1212 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1213 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1214 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1217 let Uses = [LR, RM] in {
1218 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1219 "blrl", IIC_BrB, []>;
1221 let isCodeGenOnly = 1 in {
1222 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1223 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1226 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1227 "bclrl 12, $bi, 0", IIC_BrB, []>;
1228 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1229 "bclrl 4, $bi, 0", IIC_BrB, []>;
1232 let Defs = [CTR], Uses = [CTR, RM] in {
1233 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1235 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1237 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1239 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1241 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1243 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1245 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1247 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1249 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1251 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1253 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1255 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1258 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1259 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1260 "bdzlrl", IIC_BrB, []>;
1261 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1262 "bdnzlrl", IIC_BrB, []>;
1263 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1264 "bdzlrl+", IIC_BrB, []>;
1265 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1266 "bdnzlrl+", IIC_BrB, []>;
1267 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1268 "bdzlrl-", IIC_BrB, []>;
1269 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1270 "bdnzlrl-", IIC_BrB, []>;
1274 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1275 def TCRETURNdi :Pseudo< (outs),
1276 (ins calltarget:$dst, i32imm:$offset),
1277 "#TC_RETURNd $dst $offset",
1281 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1282 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1283 "#TC_RETURNa $func $offset",
1284 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1286 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1287 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1288 "#TC_RETURNr $dst $offset",
1292 let isCodeGenOnly = 1 in {
1294 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1295 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1296 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1297 []>, Requires<[In32BitMode]>;
1299 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1300 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1301 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1305 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1306 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1307 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1313 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1315 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1316 "#EH_SJLJ_SETJMP32",
1317 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1318 Requires<[In32BitMode]>;
1319 let isTerminator = 1 in
1320 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1321 "#EH_SJLJ_LONGJMP32",
1322 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1323 Requires<[In32BitMode]>;
1326 let isBranch = 1, isTerminator = 1 in {
1327 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1328 "#EH_SjLj_Setup\t$dst", []>;
1332 let PPC970_Unit = 7 in {
1333 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1334 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1337 // DCB* instructions.
1338 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1339 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1340 PPC970_DGroup_Single;
1341 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1342 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1343 PPC970_DGroup_Single;
1344 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1345 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1346 PPC970_DGroup_Single;
1347 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1348 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1349 PPC970_DGroup_Single;
1350 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1351 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1352 PPC970_DGroup_Single;
1353 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1354 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1355 PPC970_DGroup_Single;
1356 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1357 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1358 PPC970_DGroup_Single;
1359 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1360 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1361 PPC970_DGroup_Single;
1363 def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1364 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1366 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1367 (DCBT xoaddr:$dst)>; // data prefetch for loads
1368 def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1369 (DCBTST xoaddr:$dst)>; // data prefetch for stores
1370 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1371 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
1373 // Atomic operations
1374 let usesCustomInserter = 1 in {
1375 let Defs = [CR0] in {
1376 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1377 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1378 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1379 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1380 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1381 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1382 def ATOMIC_LOAD_AND_I8 : Pseudo<
1383 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1384 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1385 def ATOMIC_LOAD_OR_I8 : Pseudo<
1386 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1387 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1388 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1389 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1390 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1391 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1392 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1393 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1394 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1395 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1396 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1397 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1398 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1399 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1400 def ATOMIC_LOAD_AND_I16 : Pseudo<
1401 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1402 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1403 def ATOMIC_LOAD_OR_I16 : Pseudo<
1404 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1405 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1406 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1407 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1408 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1409 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1410 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1411 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1412 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1413 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1414 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1415 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1416 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1417 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1418 def ATOMIC_LOAD_AND_I32 : Pseudo<
1419 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1420 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1421 def ATOMIC_LOAD_OR_I32 : Pseudo<
1422 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1423 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1424 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1425 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1426 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1427 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1428 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1429 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1431 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1432 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1433 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1434 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1435 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1436 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1437 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1438 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1439 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1441 def ATOMIC_SWAP_I8 : Pseudo<
1442 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1443 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1444 def ATOMIC_SWAP_I16 : Pseudo<
1445 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1446 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1447 def ATOMIC_SWAP_I32 : Pseudo<
1448 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1449 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1453 // Instructions to support atomic operations
1454 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1455 "lwarx $rD, $src", IIC_LdStLWARX,
1456 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1459 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1460 "stwcx. $rS, $dst", IIC_LdStSTWCX,
1461 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1464 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1465 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1467 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1468 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1469 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1470 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1471 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1472 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1473 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1474 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1476 //===----------------------------------------------------------------------===//
1477 // PPC32 Load Instructions.
1480 // Unindexed (r+i) Loads.
1481 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1482 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1483 "lbz $rD, $src", IIC_LdStLoad,
1484 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1485 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1486 "lha $rD, $src", IIC_LdStLHA,
1487 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1488 PPC970_DGroup_Cracked;
1489 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1490 "lhz $rD, $src", IIC_LdStLoad,
1491 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1492 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1493 "lwz $rD, $src", IIC_LdStLoad,
1494 [(set i32:$rD, (load iaddr:$src))]>;
1496 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1497 "lfs $rD, $src", IIC_LdStLFD,
1498 [(set f32:$rD, (load iaddr:$src))]>;
1499 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1500 "lfd $rD, $src", IIC_LdStLFD,
1501 [(set f64:$rD, (load iaddr:$src))]>;
1504 // Unindexed (r+i) Loads with Update (preinc).
1505 let mayLoad = 1, hasSideEffects = 0 in {
1506 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1507 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1508 []>, RegConstraint<"$addr.reg = $ea_result">,
1509 NoEncode<"$ea_result">;
1511 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1512 "lhau $rD, $addr", IIC_LdStLHAU,
1513 []>, RegConstraint<"$addr.reg = $ea_result">,
1514 NoEncode<"$ea_result">;
1516 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1517 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1518 []>, RegConstraint<"$addr.reg = $ea_result">,
1519 NoEncode<"$ea_result">;
1521 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1522 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1523 []>, RegConstraint<"$addr.reg = $ea_result">,
1524 NoEncode<"$ea_result">;
1526 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1527 "lfsu $rD, $addr", IIC_LdStLFDU,
1528 []>, RegConstraint<"$addr.reg = $ea_result">,
1529 NoEncode<"$ea_result">;
1531 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1532 "lfdu $rD, $addr", IIC_LdStLFDU,
1533 []>, RegConstraint<"$addr.reg = $ea_result">,
1534 NoEncode<"$ea_result">;
1537 // Indexed (r+r) Loads with Update (preinc).
1538 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1540 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1541 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1542 NoEncode<"$ea_result">;
1544 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1546 "lhaux $rD, $addr", IIC_LdStLHAUX,
1547 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1548 NoEncode<"$ea_result">;
1550 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1552 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1553 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1554 NoEncode<"$ea_result">;
1556 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1558 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1559 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1560 NoEncode<"$ea_result">;
1562 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1564 "lfsux $rD, $addr", IIC_LdStLFDUX,
1565 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1566 NoEncode<"$ea_result">;
1568 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1570 "lfdux $rD, $addr", IIC_LdStLFDUX,
1571 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1572 NoEncode<"$ea_result">;
1576 // Indexed (r+r) Loads.
1578 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1579 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1580 "lbzx $rD, $src", IIC_LdStLoad,
1581 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1582 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1583 "lhax $rD, $src", IIC_LdStLHA,
1584 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1585 PPC970_DGroup_Cracked;
1586 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1587 "lhzx $rD, $src", IIC_LdStLoad,
1588 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1589 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1590 "lwzx $rD, $src", IIC_LdStLoad,
1591 [(set i32:$rD, (load xaddr:$src))]>;
1594 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1595 "lhbrx $rD, $src", IIC_LdStLoad,
1596 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1597 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1598 "lwbrx $rD, $src", IIC_LdStLoad,
1599 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1601 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1602 "lfsx $frD, $src", IIC_LdStLFD,
1603 [(set f32:$frD, (load xaddr:$src))]>;
1604 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1605 "lfdx $frD, $src", IIC_LdStLFD,
1606 [(set f64:$frD, (load xaddr:$src))]>;
1608 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1609 "lfiwax $frD, $src", IIC_LdStLFD,
1610 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1611 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1612 "lfiwzx $frD, $src", IIC_LdStLFD,
1613 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1617 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1618 "lmw $rD, $src", IIC_LdStLMW, []>;
1620 //===----------------------------------------------------------------------===//
1621 // PPC32 Store Instructions.
1624 // Unindexed (r+i) Stores.
1625 let PPC970_Unit = 2 in {
1626 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1627 "stb $rS, $src", IIC_LdStStore,
1628 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1629 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1630 "sth $rS, $src", IIC_LdStStore,
1631 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1632 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1633 "stw $rS, $src", IIC_LdStStore,
1634 [(store i32:$rS, iaddr:$src)]>;
1635 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1636 "stfs $rS, $dst", IIC_LdStSTFD,
1637 [(store f32:$rS, iaddr:$dst)]>;
1638 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1639 "stfd $rS, $dst", IIC_LdStSTFD,
1640 [(store f64:$rS, iaddr:$dst)]>;
1643 // Unindexed (r+i) Stores with Update (preinc).
1644 let PPC970_Unit = 2, mayStore = 1 in {
1645 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1646 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1647 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1648 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1649 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1650 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1651 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1652 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1653 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1654 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1655 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1656 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1657 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1658 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1659 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1662 // Patterns to match the pre-inc stores. We can't put the patterns on
1663 // the instruction definitions directly as ISel wants the address base
1664 // and offset to be separate operands, not a single complex operand.
1665 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1666 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1667 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1668 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1669 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1670 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1671 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1672 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1673 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1674 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1676 // Indexed (r+r) Stores.
1677 let PPC970_Unit = 2 in {
1678 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1679 "stbx $rS, $dst", IIC_LdStStore,
1680 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1681 PPC970_DGroup_Cracked;
1682 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1683 "sthx $rS, $dst", IIC_LdStStore,
1684 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1685 PPC970_DGroup_Cracked;
1686 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1687 "stwx $rS, $dst", IIC_LdStStore,
1688 [(store i32:$rS, xaddr:$dst)]>,
1689 PPC970_DGroup_Cracked;
1691 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1692 "sthbrx $rS, $dst", IIC_LdStStore,
1693 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1694 PPC970_DGroup_Cracked;
1695 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1696 "stwbrx $rS, $dst", IIC_LdStStore,
1697 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1698 PPC970_DGroup_Cracked;
1700 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1701 "stfiwx $frS, $dst", IIC_LdStSTFD,
1702 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1704 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1705 "stfsx $frS, $dst", IIC_LdStSTFD,
1706 [(store f32:$frS, xaddr:$dst)]>;
1707 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1708 "stfdx $frS, $dst", IIC_LdStSTFD,
1709 [(store f64:$frS, xaddr:$dst)]>;
1712 // Indexed (r+r) Stores with Update (preinc).
1713 let PPC970_Unit = 2, mayStore = 1 in {
1714 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1715 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1716 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1717 PPC970_DGroup_Cracked;
1718 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1719 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1720 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1721 PPC970_DGroup_Cracked;
1722 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1723 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1724 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1725 PPC970_DGroup_Cracked;
1726 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1727 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1728 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1729 PPC970_DGroup_Cracked;
1730 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1731 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1732 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1733 PPC970_DGroup_Cracked;
1736 // Patterns to match the pre-inc stores. We can't put the patterns on
1737 // the instruction definitions directly as ISel wants the address base
1738 // and offset to be separate operands, not a single complex operand.
1739 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1740 (STBUX $rS, $ptrreg, $ptroff)>;
1741 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1742 (STHUX $rS, $ptrreg, $ptroff)>;
1743 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1744 (STWUX $rS, $ptrreg, $ptroff)>;
1745 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1746 (STFSUX $rS, $ptrreg, $ptroff)>;
1747 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1748 (STFDUX $rS, $ptrreg, $ptroff)>;
1751 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1752 "stmw $rS, $dst", IIC_LdStLMW, []>;
1754 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1755 "sync $L", IIC_LdStSync, []>;
1757 let isCodeGenOnly = 1 in {
1758 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1759 "msync", IIC_LdStSync, []> {
1764 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>;
1765 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
1766 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1767 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1769 //===----------------------------------------------------------------------===//
1770 // PPC32 Arithmetic Instructions.
1773 let PPC970_Unit = 1 in { // FXU Operations.
1774 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1775 "addi $rD, $rA, $imm", IIC_IntSimple,
1776 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1777 let BaseName = "addic" in {
1778 let Defs = [CARRY] in
1779 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1780 "addic $rD, $rA, $imm", IIC_IntGeneral,
1781 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1782 RecFormRel, PPC970_DGroup_Cracked;
1783 let Defs = [CARRY, CR0] in
1784 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1785 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1786 []>, isDOT, RecFormRel;
1788 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1789 "addis $rD, $rA, $imm", IIC_IntSimple,
1790 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1791 let isCodeGenOnly = 1 in
1792 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1793 "la $rD, $sym($rA)", IIC_IntGeneral,
1794 [(set i32:$rD, (add i32:$rA,
1795 (PPClo tglobaladdr:$sym, 0)))]>;
1796 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1797 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1798 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1799 let Defs = [CARRY] in
1800 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1801 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1802 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1804 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1805 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1806 "li $rD, $imm", IIC_IntSimple,
1807 [(set i32:$rD, imm32SExt16:$imm)]>;
1808 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1809 "lis $rD, $imm", IIC_IntSimple,
1810 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1814 let PPC970_Unit = 1 in { // FXU Operations.
1815 let Defs = [CR0] in {
1816 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1817 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1818 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1820 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1821 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1822 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1825 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1826 "ori $dst, $src1, $src2", IIC_IntSimple,
1827 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1828 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1829 "oris $dst, $src1, $src2", IIC_IntSimple,
1830 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1831 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1832 "xori $dst, $src1, $src2", IIC_IntSimple,
1833 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1834 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1835 "xoris $dst, $src1, $src2", IIC_IntSimple,
1836 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1838 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1840 let isCodeGenOnly = 1 in {
1841 // The POWER6 and POWER7 have special group-terminating nops.
1842 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1843 "ori 1, 1, 0", IIC_IntSimple, []>;
1844 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1845 "ori 2, 2, 0", IIC_IntSimple, []>;
1848 let isCompare = 1, hasSideEffects = 0 in {
1849 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1850 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1851 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1852 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1856 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
1857 let isCommutable = 1 in {
1858 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1859 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1860 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1861 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1862 "and", "$rA, $rS, $rB", IIC_IntSimple,
1863 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1865 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1866 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1867 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1868 let isCommutable = 1 in {
1869 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1870 "or", "$rA, $rS, $rB", IIC_IntSimple,
1871 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1872 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1873 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1874 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1876 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1877 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1878 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1879 let isCommutable = 1 in {
1880 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1881 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1882 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1883 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1884 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1885 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1887 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1888 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1889 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1890 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1891 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1892 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1893 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1894 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1895 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1898 let PPC970_Unit = 1 in { // FXU Operations.
1899 let hasSideEffects = 0 in {
1900 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1901 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1902 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1903 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1904 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1905 [(set i32:$rA, (ctlz i32:$rS))]>;
1906 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1907 "extsb", "$rA, $rS", IIC_IntSimple,
1908 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1909 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1910 "extsh", "$rA, $rS", IIC_IntSimple,
1911 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1913 let isCommutable = 1 in
1914 def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1915 "cmpb $rA, $rS, $rB", IIC_IntGeneral,
1916 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>;
1918 let isCompare = 1, hasSideEffects = 0 in {
1919 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1920 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1921 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1922 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1925 let PPC970_Unit = 3 in { // FPU Operations.
1926 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1927 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1928 let isCompare = 1, hasSideEffects = 0 in {
1929 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1930 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1931 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1932 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1933 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1936 let Uses = [RM] in {
1937 let hasSideEffects = 0 in {
1938 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1939 "fctiw", "$frD, $frB", IIC_FPGeneral,
1941 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1942 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1943 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1945 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1946 "frsp", "$frD, $frB", IIC_FPGeneral,
1947 [(set f32:$frD, (fround f64:$frB))]>;
1949 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1950 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1951 "frin", "$frD, $frB", IIC_FPGeneral,
1952 [(set f64:$frD, (frnd f64:$frB))]>;
1953 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1954 "frin", "$frD, $frB", IIC_FPGeneral,
1955 [(set f32:$frD, (frnd f32:$frB))]>;
1958 let hasSideEffects = 0 in {
1959 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1960 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1961 "frip", "$frD, $frB", IIC_FPGeneral,
1962 [(set f64:$frD, (fceil f64:$frB))]>;
1963 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1964 "frip", "$frD, $frB", IIC_FPGeneral,
1965 [(set f32:$frD, (fceil f32:$frB))]>;
1966 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1967 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1968 "friz", "$frD, $frB", IIC_FPGeneral,
1969 [(set f64:$frD, (ftrunc f64:$frB))]>;
1970 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1971 "friz", "$frD, $frB", IIC_FPGeneral,
1972 [(set f32:$frD, (ftrunc f32:$frB))]>;
1973 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1974 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1975 "frim", "$frD, $frB", IIC_FPGeneral,
1976 [(set f64:$frD, (ffloor f64:$frB))]>;
1977 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1978 "frim", "$frD, $frB", IIC_FPGeneral,
1979 [(set f32:$frD, (ffloor f32:$frB))]>;
1981 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1982 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
1983 [(set f64:$frD, (fsqrt f64:$frB))]>;
1984 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1985 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
1986 [(set f32:$frD, (fsqrt f32:$frB))]>;
1991 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1992 /// often coalesced away and we don't want the dispatch group builder to think
1993 /// that they will fill slots (which could cause the load of a LSU reject to
1994 /// sneak into a d-group with a store).
1995 let hasSideEffects = 0 in
1996 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1997 "fmr", "$frD, $frB", IIC_FPGeneral,
1998 []>, // (set f32:$frD, f32:$frB)
2001 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2002 // These are artificially split into two different forms, for 4/8 byte FP.
2003 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
2004 "fabs", "$frD, $frB", IIC_FPGeneral,
2005 [(set f32:$frD, (fabs f32:$frB))]>;
2006 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2007 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
2008 "fabs", "$frD, $frB", IIC_FPGeneral,
2009 [(set f64:$frD, (fabs f64:$frB))]>;
2010 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
2011 "fnabs", "$frD, $frB", IIC_FPGeneral,
2012 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
2013 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2014 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
2015 "fnabs", "$frD, $frB", IIC_FPGeneral,
2016 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
2017 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
2018 "fneg", "$frD, $frB", IIC_FPGeneral,
2019 [(set f32:$frD, (fneg f32:$frB))]>;
2020 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2021 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
2022 "fneg", "$frD, $frB", IIC_FPGeneral,
2023 [(set f64:$frD, (fneg f64:$frB))]>;
2025 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
2026 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2027 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
2028 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2029 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
2030 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2031 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
2033 // Reciprocal estimates.
2034 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
2035 "fre", "$frD, $frB", IIC_FPGeneral,
2036 [(set f64:$frD, (PPCfre f64:$frB))]>;
2037 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
2038 "fres", "$frD, $frB", IIC_FPGeneral,
2039 [(set f32:$frD, (PPCfre f32:$frB))]>;
2040 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
2041 "frsqrte", "$frD, $frB", IIC_FPGeneral,
2042 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
2043 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
2044 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
2045 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
2048 // XL-Form instructions. condition register logical ops.
2050 let hasSideEffects = 0 in
2051 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
2052 "mcrf $BF, $BFA", IIC_BrMCR>,
2053 PPC970_DGroup_First, PPC970_Unit_CRU;
2055 // FIXME: According to the ISA (section 2.5.1 of version 2.06), the
2056 // condition-register logical instructions have preferred forms. Specifically,
2057 // it is preferred that the bit specified by the BT field be in the same
2058 // condition register as that specified by the bit BB. We might want to account
2059 // for this via hinting the register allocator and anti-dep breakers, or we
2060 // could constrain the register class to force this constraint and then loosen
2061 // it during register allocation via convertToThreeAddress or some similar
2064 let isCommutable = 1 in {
2065 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
2066 (ins crbitrc:$CRA, crbitrc:$CRB),
2067 "crand $CRD, $CRA, $CRB", IIC_BrCR,
2068 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2070 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2071 (ins crbitrc:$CRA, crbitrc:$CRB),
2072 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2073 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2075 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
2076 (ins crbitrc:$CRA, crbitrc:$CRB),
2077 "cror $CRD, $CRA, $CRB", IIC_BrCR,
2078 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2080 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
2081 (ins crbitrc:$CRA, crbitrc:$CRB),
2082 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2083 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2085 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
2086 (ins crbitrc:$CRA, crbitrc:$CRB),
2087 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2088 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2090 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
2091 (ins crbitrc:$CRA, crbitrc:$CRB),
2092 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2093 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2096 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2097 (ins crbitrc:$CRA, crbitrc:$CRB),
2098 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2099 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2101 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
2102 (ins crbitrc:$CRA, crbitrc:$CRB),
2103 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2104 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2106 let isCodeGenOnly = 1 in {
2107 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2108 "creqv $dst, $dst, $dst", IIC_BrCR,
2109 [(set i1:$dst, 1)]>;
2111 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2112 "crxor $dst, $dst, $dst", IIC_BrCR,
2113 [(set i1:$dst, 0)]>;
2115 let Defs = [CR1EQ], CRD = 6 in {
2116 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
2117 "creqv 6, 6, 6", IIC_BrCR,
2120 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2121 "crxor 6, 6, 6", IIC_BrCR,
2126 // XFX-Form instructions. Instructions that deal with SPRs.
2129 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2130 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2131 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2132 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2134 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2135 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
2137 // A pseudo-instruction used to implement the read of the 64-bit cycle counter
2138 // on a 32-bit target.
2139 let hasSideEffects = 1, usesCustomInserter = 1 in
2140 def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2143 let Uses = [CTR] in {
2144 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2145 "mfctr $rT", IIC_SprMFSPR>,
2146 PPC970_DGroup_First, PPC970_Unit_FXU;
2148 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2149 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2150 "mtctr $rS", IIC_SprMTSPR>,
2151 PPC970_DGroup_First, PPC970_Unit_FXU;
2153 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2154 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2155 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2156 "mtctr $rS", IIC_SprMTSPR>,
2157 PPC970_DGroup_First, PPC970_Unit_FXU;
2160 let Defs = [LR] in {
2161 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2162 "mtlr $rS", IIC_SprMTSPR>,
2163 PPC970_DGroup_First, PPC970_Unit_FXU;
2165 let Uses = [LR] in {
2166 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2167 "mflr $rT", IIC_SprMFSPR>,
2168 PPC970_DGroup_First, PPC970_Unit_FXU;
2171 let isCodeGenOnly = 1 in {
2172 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2173 // like a GPR on the PPC970. As such, copies in and out have the same
2174 // performance characteristics as an OR instruction.
2175 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2176 "mtspr 256, $rS", IIC_IntGeneral>,
2177 PPC970_DGroup_Single, PPC970_Unit_FXU;
2178 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2179 "mfspr $rT, 256", IIC_IntGeneral>,
2180 PPC970_DGroup_First, PPC970_Unit_FXU;
2182 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2183 (outs VRSAVERC:$reg), (ins gprc:$rS),
2184 "mtspr 256, $rS", IIC_IntGeneral>,
2185 PPC970_DGroup_Single, PPC970_Unit_FXU;
2186 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2187 (ins VRSAVERC:$reg),
2188 "mfspr $rT, 256", IIC_IntGeneral>,
2189 PPC970_DGroup_First, PPC970_Unit_FXU;
2192 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2193 // so we'll need to scavenge a register for it.
2195 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2196 "#SPILL_VRSAVE", []>;
2198 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2199 // spilled), so we'll need to scavenge a register for it.
2201 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2202 "#RESTORE_VRSAVE", []>;
2204 let hasSideEffects = 0 in {
2205 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2206 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2207 PPC970_DGroup_First, PPC970_Unit_CRU;
2209 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2210 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2211 PPC970_MicroCode, PPC970_Unit_CRU;
2213 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2214 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2215 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2216 PPC970_DGroup_First, PPC970_Unit_CRU;
2218 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2219 "mfcr $rT", IIC_SprMFCR>,
2220 PPC970_MicroCode, PPC970_Unit_CRU;
2221 } // hasSideEffects = 0
2223 // Pseudo instruction to perform FADD in round-to-zero mode.
2224 let usesCustomInserter = 1, Uses = [RM] in {
2225 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2226 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2229 // The above pseudo gets expanded to make use of the following instructions
2230 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2231 let Uses = [RM], Defs = [RM] in {
2232 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2233 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2234 PPC970_DGroup_Single, PPC970_Unit_FPU;
2235 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2236 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2237 PPC970_DGroup_Single, PPC970_Unit_FPU;
2238 let isCodeGenOnly = 1 in
2239 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2240 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2241 PPC970_DGroup_Single, PPC970_Unit_FPU;
2243 let Uses = [RM] in {
2244 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2245 "mffs $rT", IIC_IntMFFS,
2246 [(set f64:$rT, (PPCmffs))]>,
2247 PPC970_DGroup_Single, PPC970_Unit_FPU;
2250 def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2251 "mffs. $rT", IIC_IntMFFS, []>, isDOT;
2255 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
2256 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2257 let isCommutable = 1 in
2258 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2259 "add", "$rT, $rA, $rB", IIC_IntSimple,
2260 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2261 let isCodeGenOnly = 1 in
2262 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2263 "add $rT, $rA, $rB", IIC_IntSimple,
2264 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2265 let isCommutable = 1 in
2266 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2267 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2268 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2269 PPC970_DGroup_Cracked;
2271 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2272 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2273 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
2274 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2275 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2276 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2277 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2278 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2279 let isCommutable = 1 in {
2280 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2281 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2282 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2283 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2284 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2285 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2286 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2287 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2288 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2290 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2291 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2292 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2293 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2294 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2295 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2296 PPC970_DGroup_Cracked;
2297 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2298 "neg", "$rT, $rA", IIC_IntSimple,
2299 [(set i32:$rT, (ineg i32:$rA))]>;
2300 let Uses = [CARRY] in {
2301 let isCommutable = 1 in
2302 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2303 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2304 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2305 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2306 "addme", "$rT, $rA", IIC_IntGeneral,
2307 [(set i32:$rT, (adde i32:$rA, -1))]>;
2308 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2309 "addze", "$rT, $rA", IIC_IntGeneral,
2310 [(set i32:$rT, (adde i32:$rA, 0))]>;
2311 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2312 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2313 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2314 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2315 "subfme", "$rT, $rA", IIC_IntGeneral,
2316 [(set i32:$rT, (sube -1, i32:$rA))]>;
2317 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2318 "subfze", "$rT, $rA", IIC_IntGeneral,
2319 [(set i32:$rT, (sube 0, i32:$rA))]>;
2323 // A-Form instructions. Most of the instructions executed in the FPU are of
2326 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2327 let Uses = [RM] in {
2328 let isCommutable = 1 in {
2329 defm FMADD : AForm_1r<63, 29,
2330 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2331 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2332 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2333 defm FMADDS : AForm_1r<59, 29,
2334 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2335 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2336 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2337 defm FMSUB : AForm_1r<63, 28,
2338 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2339 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2341 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2342 defm FMSUBS : AForm_1r<59, 28,
2343 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2344 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2346 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2347 defm FNMADD : AForm_1r<63, 31,
2348 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2349 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2351 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2352 defm FNMADDS : AForm_1r<59, 31,
2353 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2354 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2356 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2357 defm FNMSUB : AForm_1r<63, 30,
2358 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2359 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2360 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2361 (fneg f64:$FRB))))]>;
2362 defm FNMSUBS : AForm_1r<59, 30,
2363 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2364 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2365 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2366 (fneg f32:$FRB))))]>;
2369 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2370 // having 4 of these, force the comparison to always be an 8-byte double (code
2371 // should use an FMRSD if the input comparison value really wants to be a float)
2372 // and 4/8 byte forms for the result and operand type..
2373 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2374 defm FSELD : AForm_1r<63, 23,
2375 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2376 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2377 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2378 defm FSELS : AForm_1r<63, 23,
2379 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2380 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2381 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2382 let Uses = [RM] in {
2383 let isCommutable = 1 in {
2384 defm FADD : AForm_2r<63, 21,
2385 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2386 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2387 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2388 defm FADDS : AForm_2r<59, 21,
2389 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2390 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2391 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2393 defm FDIV : AForm_2r<63, 18,
2394 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2395 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2396 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2397 defm FDIVS : AForm_2r<59, 18,
2398 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2399 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2400 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2401 let isCommutable = 1 in {
2402 defm FMUL : AForm_3r<63, 25,
2403 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2404 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2405 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2406 defm FMULS : AForm_3r<59, 25,
2407 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2408 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2409 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2411 defm FSUB : AForm_2r<63, 20,
2412 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2413 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2414 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2415 defm FSUBS : AForm_2r<59, 20,
2416 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2417 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2418 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2422 let hasSideEffects = 0 in {
2423 let PPC970_Unit = 1 in { // FXU Operations.
2425 def ISEL : AForm_4<31, 15,
2426 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2427 "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
2431 let PPC970_Unit = 1 in { // FXU Operations.
2432 // M-Form instructions. rotate and mask instructions.
2434 let isCommutable = 1 in {
2435 // RLWIMI can be commuted if the rotate amount is zero.
2436 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2437 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2438 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2439 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2440 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2442 let BaseName = "rlwinm" in {
2443 def RLWINM : MForm_2<21,
2444 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2445 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2448 def RLWINMo : MForm_2<21,
2449 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2450 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2451 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2453 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2454 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2455 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2458 } // hasSideEffects = 0
2460 //===----------------------------------------------------------------------===//
2461 // PowerPC Instruction Patterns
2464 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2465 def : Pat<(i32 imm:$imm),
2466 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2468 // Implement the 'not' operation with the NOR instruction.
2469 def i32not : OutPatFrag<(ops node:$in),
2471 def : Pat<(not i32:$in),
2474 // ADD an arbitrary immediate.
2475 def : Pat<(add i32:$in, imm:$imm),
2476 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2477 // OR an arbitrary immediate.
2478 def : Pat<(or i32:$in, imm:$imm),
2479 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2480 // XOR an arbitrary immediate.
2481 def : Pat<(xor i32:$in, imm:$imm),
2482 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2484 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2485 (SUBFIC $in, imm:$imm)>;
2488 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2489 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2490 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2491 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2494 def : Pat<(rotl i32:$in, i32:$sh),
2495 (RLWNM $in, $sh, 0, 31)>;
2496 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2497 (RLWINM $in, imm:$imm, 0, 31)>;
2500 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2501 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2504 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2505 (BL tglobaladdr:$dst)>;
2506 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2507 (BL texternalsym:$dst)>;
2509 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2510 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2512 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2513 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2515 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2516 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2520 // Hi and Lo for Darwin Global Addresses.
2521 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2522 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2523 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2524 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2525 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2526 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2527 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2528 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2529 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2530 (ADDIS $in, tglobaltlsaddr:$g)>;
2531 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2532 (ADDI $in, tglobaltlsaddr:$g)>;
2533 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2534 (ADDIS $in, tglobaladdr:$g)>;
2535 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2536 (ADDIS $in, tconstpool:$g)>;
2537 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2538 (ADDIS $in, tjumptable:$g)>;
2539 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2540 (ADDIS $in, tblockaddress:$g)>;
2542 // Support for thread-local storage.
2543 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2544 [(set i32:$rD, (PPCppc32GOT))]>;
2546 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2547 // This uses two output registers, the first as the real output, the second as a
2548 // temporary register, used internally in code generation.
2549 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2550 []>, NoEncode<"$rT">;
2552 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2555 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2556 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2557 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2559 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2562 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2563 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2564 // explicitly defined when this op is created, so not mentioned here.
2565 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2566 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2567 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2570 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2571 // Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR
2572 // are true defines while the rest of the Defs are clobbers.
2573 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2574 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2575 def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD),
2576 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2577 "#ADDItlsgdLADDR32",
2579 (PPCaddiTlsgdLAddr i32:$reg,
2580 tglobaltlsaddr:$disp,
2581 tglobaltlsaddr:$sym))]>;
2582 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2585 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2586 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2587 // explicitly defined when this op is created, so not mentioned here.
2588 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2589 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2590 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2593 (PPCgetTlsldAddr i32:$reg,
2594 tglobaltlsaddr:$sym))]>;
2595 // Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR
2596 // are true defines while the rest of the Defs are clobbers.
2597 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2598 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2599 def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD),
2600 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2601 "#ADDItlsldLADDR32",
2603 (PPCaddiTlsldLAddr i32:$reg,
2604 tglobaltlsaddr:$disp,
2605 tglobaltlsaddr:$sym))]>;
2606 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2609 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2610 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2613 (PPCaddisDtprelHA i32:$reg,
2614 tglobaltlsaddr:$disp))]>;
2616 // Support for Position-independent code
2617 def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2620 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2621 // Get Global (GOT) Base Register offset, from the word immediately preceding
2622 // the function label.
2623 def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2626 // Standard shifts. These are represented separately from the real shifts above
2627 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2629 def : Pat<(sra i32:$rS, i32:$rB),
2631 def : Pat<(srl i32:$rS, i32:$rB),
2633 def : Pat<(shl i32:$rS, i32:$rB),
2636 def : Pat<(zextloadi1 iaddr:$src),
2638 def : Pat<(zextloadi1 xaddr:$src),
2640 def : Pat<(extloadi1 iaddr:$src),
2642 def : Pat<(extloadi1 xaddr:$src),
2644 def : Pat<(extloadi8 iaddr:$src),
2646 def : Pat<(extloadi8 xaddr:$src),
2648 def : Pat<(extloadi16 iaddr:$src),
2650 def : Pat<(extloadi16 xaddr:$src),
2652 def : Pat<(f64 (extloadf32 iaddr:$src)),
2653 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2654 def : Pat<(f64 (extloadf32 xaddr:$src)),
2655 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2657 def : Pat<(f64 (fextend f32:$src)),
2658 (COPY_TO_REGCLASS $src, F8RC)>;
2660 // Only seq_cst fences require the heavyweight sync (SYNC 0).
2661 // All others can use the lightweight sync (SYNC 1).
2662 // source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
2663 // The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
2664 // versions of Power.
2665 def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2666 def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2667 def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
2668 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2670 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2671 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2672 (FNMSUB $A, $C, $B)>;
2673 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2674 (FNMSUB $A, $C, $B)>;
2675 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2676 (FNMSUBS $A, $C, $B)>;
2677 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2678 (FNMSUBS $A, $C, $B)>;
2680 // FCOPYSIGN's operand types need not agree.
2681 def : Pat<(fcopysign f64:$frB, f32:$frA),
2682 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2683 def : Pat<(fcopysign f32:$frB, f64:$frA),
2684 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2686 include "PPCInstrAltivec.td"
2687 include "PPCInstrSPE.td"
2688 include "PPCInstr64Bit.td"
2689 include "PPCInstrVSX.td"
2690 include "PPCInstrQPX.td"
2692 def crnot : OutPatFrag<(ops node:$in),
2694 def : Pat<(not i1:$in),
2697 // Patterns for arithmetic i1 operations.
2698 def : Pat<(add i1:$a, i1:$b),
2700 def : Pat<(sub i1:$a, i1:$b),
2702 def : Pat<(mul i1:$a, i1:$b),
2705 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2706 // (-1 is used to mean all bits set).
2707 def : Pat<(i1 -1), (CRSET)>;
2709 // i1 extensions, implemented in terms of isel.
2710 def : Pat<(i32 (zext i1:$in)),
2711 (SELECT_I4 $in, (LI 1), (LI 0))>;
2712 def : Pat<(i32 (sext i1:$in)),
2713 (SELECT_I4 $in, (LI -1), (LI 0))>;
2715 def : Pat<(i64 (zext i1:$in)),
2716 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2717 def : Pat<(i64 (sext i1:$in)),
2718 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2720 // FIXME: We should choose either a zext or a sext based on other constants
2722 def : Pat<(i32 (anyext i1:$in)),
2723 (SELECT_I4 $in, (LI 1), (LI 0))>;
2724 def : Pat<(i64 (anyext i1:$in)),
2725 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2727 // match setcc on i1 variables.
2728 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2730 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2732 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2734 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2736 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2738 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2740 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2742 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2744 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2746 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2749 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2750 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2751 // floating-point types.
2753 multiclass CRNotPat<dag pattern, dag result> {
2754 def : Pat<pattern, (crnot result)>;
2755 def : Pat<(not pattern), result>;
2757 // We can also fold the crnot into an extension:
2758 def : Pat<(i32 (zext pattern)),
2759 (SELECT_I4 result, (LI 0), (LI 1))>;
2760 def : Pat<(i32 (sext pattern)),
2761 (SELECT_I4 result, (LI 0), (LI -1))>;
2763 // We can also fold the crnot into an extension:
2764 def : Pat<(i64 (zext pattern)),
2765 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2766 def : Pat<(i64 (sext pattern)),
2767 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2769 // FIXME: We should choose either a zext or a sext based on other constants
2771 def : Pat<(i32 (anyext pattern)),
2772 (SELECT_I4 result, (LI 0), (LI 1))>;
2774 def : Pat<(i64 (anyext pattern)),
2775 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2778 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2779 // we need to write imm:$imm in the output patterns below, not just $imm, or
2780 // else the resulting matcher will not correctly add the immediate operand
2781 // (making it a register operand instead).
2784 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2785 OutPatFrag rfrag, OutPatFrag rfrag8> {
2786 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2788 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2790 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2791 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2792 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2793 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2795 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2797 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2799 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2800 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2801 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2802 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2805 // Note that we do all inversions below with i(32|64)not, instead of using
2806 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2807 // has 2-cycle latency.
2809 defm : ExtSetCCPat<SETEQ,
2810 PatFrag<(ops node:$in, node:$cc),
2811 (setcc $in, 0, $cc)>,
2812 OutPatFrag<(ops node:$in),
2813 (RLWINM (CNTLZW $in), 27, 31, 31)>,
2814 OutPatFrag<(ops node:$in),
2815 (RLDICL (CNTLZD $in), 58, 63)> >;
2817 defm : ExtSetCCPat<SETNE,
2818 PatFrag<(ops node:$in, node:$cc),
2819 (setcc $in, 0, $cc)>,
2820 OutPatFrag<(ops node:$in),
2821 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2822 OutPatFrag<(ops node:$in),
2823 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2825 defm : ExtSetCCPat<SETLT,
2826 PatFrag<(ops node:$in, node:$cc),
2827 (setcc $in, 0, $cc)>,
2828 OutPatFrag<(ops node:$in),
2829 (RLWINM $in, 1, 31, 31)>,
2830 OutPatFrag<(ops node:$in),
2831 (RLDICL $in, 1, 63)> >;
2833 defm : ExtSetCCPat<SETGE,
2834 PatFrag<(ops node:$in, node:$cc),
2835 (setcc $in, 0, $cc)>,
2836 OutPatFrag<(ops node:$in),
2837 (RLWINM (i32not $in), 1, 31, 31)>,
2838 OutPatFrag<(ops node:$in),
2839 (RLDICL (i64not $in), 1, 63)> >;
2841 defm : ExtSetCCPat<SETGT,
2842 PatFrag<(ops node:$in, node:$cc),
2843 (setcc $in, 0, $cc)>,
2844 OutPatFrag<(ops node:$in),
2845 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
2846 OutPatFrag<(ops node:$in),
2847 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
2849 defm : ExtSetCCPat<SETLE,
2850 PatFrag<(ops node:$in, node:$cc),
2851 (setcc $in, 0, $cc)>,
2852 OutPatFrag<(ops node:$in),
2853 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
2854 OutPatFrag<(ops node:$in),
2855 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
2857 defm : ExtSetCCPat<SETLT,
2858 PatFrag<(ops node:$in, node:$cc),
2859 (setcc $in, -1, $cc)>,
2860 OutPatFrag<(ops node:$in),
2861 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
2862 OutPatFrag<(ops node:$in),
2863 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2865 defm : ExtSetCCPat<SETGE,
2866 PatFrag<(ops node:$in, node:$cc),
2867 (setcc $in, -1, $cc)>,
2868 OutPatFrag<(ops node:$in),
2869 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
2870 OutPatFrag<(ops node:$in),
2871 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2873 defm : ExtSetCCPat<SETGT,
2874 PatFrag<(ops node:$in, node:$cc),
2875 (setcc $in, -1, $cc)>,
2876 OutPatFrag<(ops node:$in),
2877 (RLWINM (i32not $in), 1, 31, 31)>,
2878 OutPatFrag<(ops node:$in),
2879 (RLDICL (i64not $in), 1, 63)> >;
2881 defm : ExtSetCCPat<SETLE,
2882 PatFrag<(ops node:$in, node:$cc),
2883 (setcc $in, -1, $cc)>,
2884 OutPatFrag<(ops node:$in),
2885 (RLWINM $in, 1, 31, 31)>,
2886 OutPatFrag<(ops node:$in),
2887 (RLDICL $in, 1, 63)> >;
2890 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
2891 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2892 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
2893 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2894 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
2895 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2896 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
2897 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2898 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
2899 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2900 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
2901 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2903 // For non-equality comparisons, the default code would materialize the
2904 // constant, then compare against it, like this:
2906 // ori r2, r2, 22136
2909 // Since we are just comparing for equality, we can emit this instead:
2910 // xoris r0,r3,0x1234
2911 // cmplwi cr0,r0,0x5678
2914 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
2915 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2916 (LO16 imm:$imm)), sub_eq)>;
2918 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
2919 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2920 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
2921 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2922 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
2923 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2924 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
2925 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2926 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
2927 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2928 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
2929 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2931 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2932 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2933 (LO16 imm:$imm)), sub_eq)>;
2935 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
2936 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2937 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
2938 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2939 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
2940 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2941 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
2942 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2943 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
2944 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2946 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
2947 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2948 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
2949 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2950 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
2951 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2952 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
2953 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2954 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
2955 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2958 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
2959 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2960 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
2961 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2962 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
2963 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2964 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
2965 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2966 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
2967 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2968 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
2969 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2971 // For non-equality comparisons, the default code would materialize the
2972 // constant, then compare against it, like this:
2974 // ori r2, r2, 22136
2977 // Since we are just comparing for equality, we can emit this instead:
2978 // xoris r0,r3,0x1234
2979 // cmpldi cr0,r0,0x5678
2982 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
2983 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2984 (LO16 imm:$imm)), sub_eq)>;
2986 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
2987 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2988 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
2989 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2990 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
2991 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2992 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
2993 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2994 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
2995 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2996 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
2997 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2999 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
3000 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3001 (LO16 imm:$imm)), sub_eq)>;
3003 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3004 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3005 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3006 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3007 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3008 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3009 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
3010 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3011 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
3012 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3014 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3015 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3016 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
3017 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3018 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3019 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3020 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
3021 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3022 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
3023 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3026 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
3027 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3028 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
3029 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3030 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
3031 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3032 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
3033 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3034 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
3035 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3036 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
3037 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3038 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
3039 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3041 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3042 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3043 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
3044 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3045 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
3046 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3047 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
3048 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3049 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3050 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3051 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
3052 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3053 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
3054 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3057 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
3058 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3059 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
3060 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3061 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
3062 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3063 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
3064 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3065 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
3066 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3067 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
3068 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3069 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
3070 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3072 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3073 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3074 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
3075 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3076 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
3077 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3078 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
3079 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3080 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
3081 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3082 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
3083 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3084 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
3085 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3087 // match select on i1 variables:
3088 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
3089 (CROR (CRAND $cond , $tval),
3090 (CRAND (crnot $cond), $fval))>;
3092 // match selectcc on i1 variables:
3093 // select (lhs == rhs), tval, fval is:
3094 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
3095 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
3096 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3097 (CRAND (CRORC $lhs, $rhs), $fval))>;
3098 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
3099 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
3100 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3101 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
3102 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
3103 (CRAND (CRXOR $lhs, $rhs), $fval))>;
3104 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3105 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
3106 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3107 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3108 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3109 (CRAND (CRORC $rhs, $lhs), $fval))>;
3110 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3111 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3112 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3114 // match selectcc on i1 variables with non-i1 output.
3115 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3116 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3117 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3118 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
3119 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3120 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3121 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3122 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
3123 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3124 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3125 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3126 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3128 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3129 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3130 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3131 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
3132 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3133 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3134 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3135 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
3136 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3137 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3138 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3139 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3141 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3142 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3143 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3144 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
3145 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3146 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3147 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3148 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
3149 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3150 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3151 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3152 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3154 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3155 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3156 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3157 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
3158 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3159 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3160 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3161 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
3162 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3163 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3164 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3165 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3167 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3168 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3169 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3170 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3171 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3172 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3173 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3174 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3175 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3176 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3177 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3178 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3180 let usesCustomInserter = 1 in {
3181 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3183 [(set i1:$dst, (trunc (not i32:$in)))]>;
3184 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3186 [(set i1:$dst, (trunc i32:$in))]>;
3188 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3190 [(set i1:$dst, (trunc (not i64:$in)))]>;
3191 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3193 [(set i1:$dst, (trunc i64:$in))]>;
3196 def : Pat<(i1 (not (trunc i32:$in))),
3197 (ANDIo_1_EQ_BIT $in)>;
3198 def : Pat<(i1 (not (trunc i64:$in))),
3199 (ANDIo_1_EQ_BIT8 $in)>;
3201 //===----------------------------------------------------------------------===//
3202 // PowerPC Instructions used for assembler/disassembler only
3205 // FIXME: For B=0 or B > 8, the registers following RT are used.
3206 // WARNING: Do not add patterns for this instruction without fixing this.
3207 def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3208 "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3210 // FIXME: For B=0 or B > 8, the registers following RT are used.
3211 // WARNING: Do not add patterns for this instruction without fixing this.
3212 def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3213 "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3215 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3216 "isync", IIC_SprISYNC, []>;
3218 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3219 "icbi $src", IIC_LdStICBI, []>;
3221 // We used to have EIEIO as value but E[0-9A-Z] is a reserved name
3222 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3223 "eieio", IIC_LdStLoad, []>;
3225 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3226 "wait $L", IIC_LdStLoad, []>;
3228 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3229 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3231 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3232 "mtsr $SR, $RS", IIC_SprMTSR>;
3234 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3235 "mfsr $RS, $SR", IIC_SprMFSR>;
3237 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3238 "mtsrin $RS, $RB", IIC_SprMTSR>;
3240 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3241 "mfsrin $RS, $RB", IIC_SprMFSR>;
3243 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3244 "mtmsr $RS, $L", IIC_SprMTMSR>;
3246 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3247 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3251 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3252 Requires<[IsBookE]> {
3256 let Inst{21-30} = 163;
3259 def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3260 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3261 def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3262 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3264 def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3265 def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3266 def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3267 def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3269 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3270 "mfmsr $RT", IIC_SprMFMSR, []>;
3272 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3273 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3275 def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
3276 "mcrfs $BF, $BFA", IIC_BrMCR>;
3278 def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3279 "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
3281 def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3282 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
3284 def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
3285 def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
3287 def MTFSF : XFLForm_1<63, 711, (outs),
3288 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3289 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
3290 def MTFSFo : XFLForm_1<63, 711, (outs),
3291 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3292 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
3294 def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3295 def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3297 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3298 "slbie $RB", IIC_SprSLBIE, []>;
3300 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3301 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3303 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3304 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3306 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3308 def TLBIA : XForm_0<31, 370, (outs), (ins),
3309 "tlbia", IIC_SprTLBIA, []>;
3311 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3312 "tlbsync", IIC_SprTLBSYNC, []>;
3314 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3315 "tlbiel $RB", IIC_SprTLBIEL, []>;
3317 def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3318 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3319 def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3320 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3322 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3323 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3325 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3326 IIC_LdStLoad>, Requires<[IsBookE]>;
3328 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3329 IIC_LdStLoad>, Requires<[IsBookE]>;
3331 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3332 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3334 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3335 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3337 def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3338 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3340 def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3341 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3343 def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3344 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3345 Requires<[IsPPC4xx]>;
3346 def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3347 (ins gprc:$RST, gprc:$A, gprc:$B),
3348 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3349 Requires<[IsPPC4xx]>, isDOT;
3351 def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3353 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3354 Requires<[IsBookE]>;
3355 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3356 Requires<[IsBookE]>;
3358 def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3360 def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3363 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3364 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3365 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3366 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3368 def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
3370 def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3371 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
3372 def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3373 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
3374 def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3375 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
3376 def LDCIX : XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3377 "ldcix $RST, $A, $B", IIC_LdStLoad, []>;
3379 def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3380 "stbcix $RST, $A, $B", IIC_LdStLoad, []>;
3381 def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3382 "sthcix $RST, $A, $B", IIC_LdStLoad, []>;
3383 def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3384 "stwcix $RST, $A, $B", IIC_LdStLoad, []>;
3385 def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3386 "stdcix $RST, $A, $B", IIC_LdStLoad, []>;
3388 //===----------------------------------------------------------------------===//
3389 // PowerPC Assembler Instruction Aliases
3392 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3393 // These are aliases that require C++ handling to convert to the target
3394 // instruction, while InstAliases can be handled directly by tblgen.
3395 class PPCAsmPseudo<string asm, dag iops>
3397 let Namespace = "PPC";
3398 bit PPC64 = 0; // Default value, override with isPPC64
3400 let OutOperandList = (outs);
3401 let InOperandList = iops;
3403 let AsmString = asm;
3404 let isAsmParserOnly = 1;
3408 def : InstAlias<"sc", (SC 0)>;
3410 def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3411 def : InstAlias<"msync", (SYNC 0)>, Requires<[HasSYNC]>;
3412 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3413 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3415 def : InstAlias<"wait", (WAIT 0)>;
3416 def : InstAlias<"waitrsv", (WAIT 1)>;
3417 def : InstAlias<"waitimpl", (WAIT 2)>;
3419 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3421 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3422 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3423 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3424 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3426 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3427 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3429 def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3430 def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3432 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3433 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3435 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3436 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3438 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3439 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3441 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3442 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3444 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3445 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3447 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3448 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3450 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3451 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3453 def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3454 def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3456 def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3457 def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3459 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3460 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3462 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3463 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3465 def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3466 def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3468 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3469 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3470 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3472 def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3473 def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3475 def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3476 def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3477 def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3478 def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3480 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3482 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3483 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3485 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3486 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3488 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3490 foreach BATR = 0-3 in {
3491 def : InstAlias<"mtdbatu "#BATR#", $Rx",
3492 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3493 Requires<[IsPPC6xx]>;
3494 def : InstAlias<"mfdbatu $Rx, "#BATR,
3495 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3496 Requires<[IsPPC6xx]>;
3497 def : InstAlias<"mtdbatl "#BATR#", $Rx",
3498 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3499 Requires<[IsPPC6xx]>;
3500 def : InstAlias<"mfdbatl $Rx, "#BATR,
3501 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3502 Requires<[IsPPC6xx]>;
3503 def : InstAlias<"mtibatu "#BATR#", $Rx",
3504 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3505 Requires<[IsPPC6xx]>;
3506 def : InstAlias<"mfibatu $Rx, "#BATR,
3507 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3508 Requires<[IsPPC6xx]>;
3509 def : InstAlias<"mtibatl "#BATR#", $Rx",
3510 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3511 Requires<[IsPPC6xx]>;
3512 def : InstAlias<"mfibatl $Rx, "#BATR,
3513 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3514 Requires<[IsPPC6xx]>;
3517 foreach BR = 0-7 in {
3518 def : InstAlias<"mfbr"#BR#" $Rx",
3519 (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3520 Requires<[IsPPC4xx]>;
3521 def : InstAlias<"mtbr"#BR#" $Rx",
3522 (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3523 Requires<[IsPPC4xx]>;
3526 def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3527 def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3529 def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3530 def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
3532 def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3533 def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
3535 def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3536 def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
3538 def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
3539 def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
3541 def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3542 def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
3544 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3546 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3547 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3548 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3549 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3550 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3551 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3552 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3553 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3555 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3556 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3557 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3558 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3560 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3561 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3563 def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
3564 def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
3566 foreach SPRG = 0-3 in {
3567 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
3568 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
3569 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3570 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3572 foreach SPRG = 4-7 in {
3573 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
3574 Requires<[IsBookE]>;
3575 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
3576 Requires<[IsBookE]>;
3577 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3578 Requires<[IsBookE]>;
3579 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3580 Requires<[IsBookE]>;
3583 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3585 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3586 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3588 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3590 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3591 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3593 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3594 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3595 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3596 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3598 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3600 def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
3601 Requires<[IsPPC4xx]>;
3602 def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
3603 Requires<[IsPPC4xx]>;
3604 def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
3605 Requires<[IsPPC4xx]>;
3606 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
3607 Requires<[IsPPC4xx]>;
3609 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3610 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3611 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3612 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3613 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3614 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3615 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3616 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3617 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3618 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3619 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3620 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3621 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3622 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3623 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3624 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3625 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3626 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3627 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3628 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3629 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3630 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3631 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3632 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3633 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3634 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3635 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3636 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3637 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3638 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3639 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3640 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3641 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3642 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3643 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3644 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3646 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3647 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3648 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3649 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3650 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3651 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3653 def : InstAlias<"cntlz $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
3654 def : InstAlias<"cntlz. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>;
3656 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3657 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3658 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3659 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3660 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3661 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3662 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3663 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3664 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3665 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3666 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3667 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3668 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3669 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3670 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3671 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3672 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3673 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3674 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3675 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3676 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3677 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3678 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3679 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3680 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3681 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3682 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3683 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3684 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3685 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3686 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3687 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3689 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3690 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3691 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3692 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3693 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3694 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3696 // These generic branch instruction forms are used for the assembler parser only.
3697 // Defs and Uses are conservative, since we don't know the BO value.
3698 let PPC970_Unit = 7 in {
3699 let Defs = [CTR], Uses = [CTR, RM] in {
3700 def gBC : BForm_3<16, 0, 0, (outs),
3701 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3702 "bc $bo, $bi, $dst">;
3703 def gBCA : BForm_3<16, 1, 0, (outs),
3704 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3705 "bca $bo, $bi, $dst">;
3707 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3708 def gBCL : BForm_3<16, 0, 1, (outs),
3709 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3710 "bcl $bo, $bi, $dst">;
3711 def gBCLA : BForm_3<16, 1, 1, (outs),
3712 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3713 "bcla $bo, $bi, $dst">;
3715 let Defs = [CTR], Uses = [CTR, LR, RM] in
3716 def gBCLR : XLForm_2<19, 16, 0, (outs),
3717 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3718 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3719 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3720 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3721 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3722 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3723 let Defs = [CTR], Uses = [CTR, LR, RM] in
3724 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3725 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3726 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3727 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3728 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3729 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3730 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3732 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3733 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3734 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3735 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3737 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3738 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3739 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3740 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3741 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3742 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3743 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3745 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3746 : BranchSimpleMnemonic1<name, pm, bo> {
3747 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3748 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3750 defm : BranchSimpleMnemonic2<"t", "", 12>;
3751 defm : BranchSimpleMnemonic2<"f", "", 4>;
3752 defm : BranchSimpleMnemonic2<"t", "-", 14>;
3753 defm : BranchSimpleMnemonic2<"f", "-", 6>;
3754 defm : BranchSimpleMnemonic2<"t", "+", 15>;
3755 defm : BranchSimpleMnemonic2<"f", "+", 7>;
3756 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
3757 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
3758 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
3759 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
3761 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
3762 def : InstAlias<"b"#name#pm#" $cc, $dst",
3763 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
3764 def : InstAlias<"b"#name#pm#" $dst",
3765 (BCC bibo, CR0, condbrtarget:$dst)>;
3767 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
3768 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3769 def : InstAlias<"b"#name#"a"#pm#" $dst",
3770 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
3772 def : InstAlias<"b"#name#"lr"#pm#" $cc",
3773 (BCCLR bibo, crrc:$cc)>;
3774 def : InstAlias<"b"#name#"lr"#pm,
3777 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
3778 (BCCCTR bibo, crrc:$cc)>;
3779 def : InstAlias<"b"#name#"ctr"#pm,
3780 (BCCCTR bibo, CR0)>;
3782 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
3783 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
3784 def : InstAlias<"b"#name#"l"#pm#" $dst",
3785 (BCCL bibo, CR0, condbrtarget:$dst)>;
3787 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
3788 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3789 def : InstAlias<"b"#name#"la"#pm#" $dst",
3790 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
3792 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
3793 (BCCLRL bibo, crrc:$cc)>;
3794 def : InstAlias<"b"#name#"lrl"#pm,
3795 (BCCLRL bibo, CR0)>;
3797 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
3798 (BCCCTRL bibo, crrc:$cc)>;
3799 def : InstAlias<"b"#name#"ctrl"#pm,
3800 (BCCCTRL bibo, CR0)>;
3802 multiclass BranchExtendedMnemonic<string name, int bibo> {
3803 defm : BranchExtendedMnemonicPM<name, "", bibo>;
3804 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
3805 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
3807 defm : BranchExtendedMnemonic<"lt", 12>;
3808 defm : BranchExtendedMnemonic<"gt", 44>;
3809 defm : BranchExtendedMnemonic<"eq", 76>;
3810 defm : BranchExtendedMnemonic<"un", 108>;
3811 defm : BranchExtendedMnemonic<"so", 108>;
3812 defm : BranchExtendedMnemonic<"ge", 4>;
3813 defm : BranchExtendedMnemonic<"nl", 4>;
3814 defm : BranchExtendedMnemonic<"le", 36>;
3815 defm : BranchExtendedMnemonic<"ng", 36>;
3816 defm : BranchExtendedMnemonic<"ne", 68>;
3817 defm : BranchExtendedMnemonic<"nu", 100>;
3818 defm : BranchExtendedMnemonic<"ns", 100>;
3820 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
3821 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
3822 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
3823 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
3824 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
3825 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
3826 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
3827 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
3829 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
3830 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
3831 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
3832 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
3833 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
3834 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3835 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
3836 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3838 multiclass TrapExtendedMnemonic<string name, int to> {
3839 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
3840 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
3841 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
3842 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
3844 defm : TrapExtendedMnemonic<"lt", 16>;
3845 defm : TrapExtendedMnemonic<"le", 20>;
3846 defm : TrapExtendedMnemonic<"eq", 4>;
3847 defm : TrapExtendedMnemonic<"ge", 12>;
3848 defm : TrapExtendedMnemonic<"gt", 8>;
3849 defm : TrapExtendedMnemonic<"nl", 12>;
3850 defm : TrapExtendedMnemonic<"ne", 24>;
3851 defm : TrapExtendedMnemonic<"ng", 20>;
3852 defm : TrapExtendedMnemonic<"llt", 2>;
3853 defm : TrapExtendedMnemonic<"lle", 6>;
3854 defm : TrapExtendedMnemonic<"lge", 5>;
3855 defm : TrapExtendedMnemonic<"lgt", 1>;
3856 defm : TrapExtendedMnemonic<"lnl", 5>;
3857 defm : TrapExtendedMnemonic<"lng", 6>;
3858 defm : TrapExtendedMnemonic<"u", 31>;
3861 def : Pat<(atomic_load_8 iaddr:$src), (LBZ memri:$src)>;
3862 def : Pat<(atomic_load_16 iaddr:$src), (LHZ memri:$src)>;
3863 def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>;
3864 def : Pat<(atomic_load_8 xaddr:$src), (LBZX memrr:$src)>;
3865 def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
3866 def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
3869 def : Pat<(atomic_store_8 iaddr:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>;
3870 def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>;
3871 def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>;
3872 def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
3873 def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
3874 def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;