1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
61 //===----------------------------------------------------------------------===//
62 // PowerPC specific DAG Nodes.
65 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
66 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
68 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
69 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
70 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
71 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
72 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
73 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
74 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
75 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
76 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
77 [SDNPHasChain, SDNPMayStore]>;
78 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
79 [SDNPHasChain, SDNPMayLoad]>;
80 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
81 [SDNPHasChain, SDNPMayLoad]>;
83 // Extract FPSCR (not modeled at the DAG level).
84 def PPCmffs : SDNode<"PPCISD::MFFS",
85 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
87 // Perform FADD in round-to-zero mode.
88 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
91 def PPCfsel : SDNode<"PPCISD::FSEL",
92 // Type constraint for fsel.
93 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
94 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
96 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
97 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
98 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
99 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
100 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
102 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
103 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
105 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
106 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
107 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
108 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
109 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
110 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
111 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
112 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
114 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
116 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
118 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
119 // amounts. These nodes are generated by the multi-precision shift code.
120 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
121 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
122 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
124 // These are target-independent nodes, but have target-specific formats.
125 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
126 [SDNPHasChain, SDNPOutGlue]>;
127 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
128 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
130 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
131 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
134 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
135 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
137 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
139 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
140 [SDNPHasChain, SDNPSideEffect,
141 SDNPInGlue, SDNPOutGlue]>;
142 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
143 [SDNPHasChain, SDNPSideEffect,
144 SDNPInGlue, SDNPOutGlue]>;
145 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
147 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
151 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
152 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
154 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
157 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
158 SDTypeProfile<1, 1, [SDTCisInt<0>,
160 [SDNPHasChain, SDNPSideEffect]>;
161 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
162 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
163 [SDNPHasChain, SDNPSideEffect]>;
165 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
166 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
168 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
169 [SDNPHasChain, SDNPOptInGlue]>;
171 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
172 [SDNPHasChain, SDNPMayLoad]>;
173 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
174 [SDNPHasChain, SDNPMayStore]>;
176 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
177 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
178 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
179 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
180 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
182 // Instructions to support atomic operations
183 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
184 [SDNPHasChain, SDNPMayLoad]>;
185 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
186 [SDNPHasChain, SDNPMayStore]>;
188 // Instructions to support medium and large code model
189 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
190 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
191 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
194 // Instructions to support dynamic alloca.
195 def SDTDynOp : SDTypeProfile<1, 2, []>;
196 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
198 //===----------------------------------------------------------------------===//
199 // PowerPC specific transformation functions and pattern fragments.
202 def SHL32 : SDNodeXForm<imm, [{
203 // Transformation function: 31 - imm
204 return getI32Imm(31 - N->getZExtValue());
207 def SRL32 : SDNodeXForm<imm, [{
208 // Transformation function: 32 - imm
209 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
212 def LO16 : SDNodeXForm<imm, [{
213 // Transformation function: get the low 16 bits.
214 return getI32Imm((unsigned short)N->getZExtValue());
217 def HI16 : SDNodeXForm<imm, [{
218 // Transformation function: shift the immediate value down into the low bits.
219 return getI32Imm((unsigned)N->getZExtValue() >> 16);
222 def HA16 : SDNodeXForm<imm, [{
223 // Transformation function: shift the immediate value down into the low bits.
224 signed int Val = N->getZExtValue();
225 return getI32Imm((Val - (signed short)Val) >> 16);
227 def MB : SDNodeXForm<imm, [{
228 // Transformation function: get the start bit of a mask
230 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
231 return getI32Imm(mb);
234 def ME : SDNodeXForm<imm, [{
235 // Transformation function: get the end bit of a mask
237 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
238 return getI32Imm(me);
240 def maskimm32 : PatLeaf<(imm), [{
241 // maskImm predicate - True if immediate is a run of ones.
243 if (N->getValueType(0) == MVT::i32)
244 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
249 def immSExt16 : PatLeaf<(imm), [{
250 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
251 // field. Used by instructions like 'addi'.
252 if (N->getValueType(0) == MVT::i32)
253 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
255 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
257 def immZExt16 : PatLeaf<(imm), [{
258 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
259 // field. Used by instructions like 'ori'.
260 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
263 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
264 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
265 // identical in 32-bit mode, but in 64-bit mode, they return true if the
266 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
268 def imm16ShiftedZExt : PatLeaf<(imm), [{
269 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
270 // immediate are set. Used by instructions like 'xoris'.
271 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
274 def imm16ShiftedSExt : PatLeaf<(imm), [{
275 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
276 // immediate are set. Used by instructions like 'addis'. Identical to
277 // imm16ShiftedZExt in 32-bit mode.
278 if (N->getZExtValue() & 0xFFFF) return false;
279 if (N->getValueType(0) == MVT::i32)
281 // For 64-bit, make sure it is sext right.
282 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
285 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
286 // restricted memrix (offset/4) constants are alignment sensitive. If these
287 // offsets are hidden behind TOC entries than the values of the lower-order
288 // bits cannot be checked directly. As a result, we need to also incorporate
289 // an alignment check into the relevant patterns.
291 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
292 return cast<LoadSDNode>(N)->getAlignment() >= 4;
294 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
295 (store node:$val, node:$ptr), [{
296 return cast<StoreSDNode>(N)->getAlignment() >= 4;
298 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
299 return cast<LoadSDNode>(N)->getAlignment() >= 4;
301 def aligned4pre_store : PatFrag<
302 (ops node:$val, node:$base, node:$offset),
303 (pre_store node:$val, node:$base, node:$offset), [{
304 return cast<StoreSDNode>(N)->getAlignment() >= 4;
307 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
308 return cast<LoadSDNode>(N)->getAlignment() < 4;
310 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
311 (store node:$val, node:$ptr), [{
312 return cast<StoreSDNode>(N)->getAlignment() < 4;
314 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
315 return cast<LoadSDNode>(N)->getAlignment() < 4;
318 //===----------------------------------------------------------------------===//
319 // PowerPC Flag Definitions.
321 class isPPC64 { bit PPC64 = 1; }
323 list<Register> Defs = [CR0];
327 class RegConstraint<string C> {
328 string Constraints = C;
330 class NoEncode<string E> {
331 string DisableEncoding = E;
335 //===----------------------------------------------------------------------===//
336 // PowerPC Operand Definitions.
338 def s5imm : Operand<i32> {
339 let PrintMethod = "printS5ImmOperand";
341 def u5imm : Operand<i32> {
342 let PrintMethod = "printU5ImmOperand";
344 def u6imm : Operand<i32> {
345 let PrintMethod = "printU6ImmOperand";
347 def s16imm : Operand<i32> {
348 let PrintMethod = "printS16ImmOperand";
350 def u16imm : Operand<i32> {
351 let PrintMethod = "printU16ImmOperand";
353 def directbrtarget : Operand<OtherVT> {
354 let PrintMethod = "printBranchOperand";
355 let EncoderMethod = "getDirectBrEncoding";
357 def condbrtarget : Operand<OtherVT> {
358 let PrintMethod = "printBranchOperand";
359 let EncoderMethod = "getCondBrEncoding";
361 def calltarget : Operand<iPTR> {
362 let EncoderMethod = "getDirectBrEncoding";
364 def aaddr : Operand<iPTR> {
365 let PrintMethod = "printAbsAddrOperand";
367 def symbolHi: Operand<i32> {
368 let PrintMethod = "printSymbolHi";
369 let EncoderMethod = "getHA16Encoding";
371 def symbolLo: Operand<i32> {
372 let PrintMethod = "printSymbolLo";
373 let EncoderMethod = "getLO16Encoding";
375 def crbitm: Operand<i8> {
376 let PrintMethod = "printcrbitm";
377 let EncoderMethod = "get_crbitm_encoding";
380 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
381 def ptr_rc_nor0 : PointerLikeRegClass<1>;
383 def dispRI : Operand<iPTR>;
384 def dispRIX : Operand<iPTR>;
386 def memri : Operand<iPTR> {
387 let PrintMethod = "printMemRegImm";
388 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
389 let EncoderMethod = "getMemRIEncoding";
391 def memrr : Operand<iPTR> {
392 let PrintMethod = "printMemRegReg";
393 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc:$offreg);
395 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
396 let PrintMethod = "printMemRegImmShifted";
397 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
398 let EncoderMethod = "getMemRIXEncoding";
401 // A single-register address. This is used with the SjLj
402 // pseudo-instructions.
403 def memr : Operand<iPTR> {
404 let MIOperandInfo = (ops ptr_rc:$ptrreg);
407 // PowerPC Predicate operand.
408 def pred : Operand<OtherVT> {
409 let PrintMethod = "printPredicateOperand";
410 let MIOperandInfo = (ops i32imm:$bibo, CRRC:$reg);
413 // Define PowerPC specific addressing mode.
414 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
415 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
416 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
417 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
419 // The address in a single register. This is used with the SjLj
420 // pseudo-instructions.
421 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
423 /// This is just the offset part of iaddr, used for preinc.
424 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
426 //===----------------------------------------------------------------------===//
427 // PowerPC Instruction Predicate Definitions.
428 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
429 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
430 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
432 //===----------------------------------------------------------------------===//
433 // PowerPC Instruction Definitions.
435 // Pseudo-instructions:
437 let hasCtrlDep = 1 in {
438 let Defs = [R1], Uses = [R1] in {
439 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
440 [(callseq_start timm:$amt)]>;
441 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
442 [(callseq_end timm:$amt1, timm:$amt2)]>;
445 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
446 "UPDATE_VRSAVE $rD, $rS", []>;
449 let Defs = [R1], Uses = [R1] in
450 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "#DYNALLOC",
452 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
454 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
455 // instruction selection into a branch sequence.
456 let usesCustomInserter = 1, // Expanded after instruction selection.
457 PPC970_Single = 1 in {
458 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
459 // because either operand might become the first operand in an isel, and
460 // that operand cannot be r0.
461 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond,
462 GPRC_NOR0:$T, GPRC_NOR0:$F,
463 i32imm:$BROPC), "#SELECT_CC_I4",
465 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond,
466 G8RC_NOX0:$T, G8RC_NOX0:$F,
467 i32imm:$BROPC), "#SELECT_CC_I8",
469 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
470 i32imm:$BROPC), "#SELECT_CC_F4",
472 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
473 i32imm:$BROPC), "#SELECT_CC_F8",
475 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
476 i32imm:$BROPC), "#SELECT_CC_VRRC",
480 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
481 // scavenge a register for it.
483 def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F),
486 // RESTORE_CR - Indicate that we're restoring the CR register (previously
487 // spilled), so we'll need to scavenge a register for it.
489 def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F),
492 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
493 let isReturn = 1, Uses = [LR, RM] in
494 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", BrB,
496 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
497 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
501 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
504 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
505 let isBarrier = 1 in {
506 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
511 // BCC represents an arbitrary conditional branch on a predicate.
512 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
513 // a two-value operand where a dag node expects two operands. :(
514 let isCodeGenOnly = 1 in
515 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
516 "b${cond:cc} ${cond:reg}, $dst"
517 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
519 let Defs = [CTR], Uses = [CTR] in {
520 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
522 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
527 // The unconditional BCL used by the SjLj setjmp code.
528 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
529 let Defs = [LR], Uses = [RM] in {
530 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
535 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
536 // Convenient aliases for call instructions
538 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
539 "bl $func", BrB, []>; // See Pat patterns below.
540 def BLA : IForm<18, 1, 1, (outs), (ins aaddr:$func),
541 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
543 let Uses = [CTR, RM] in {
544 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
545 "bctrl", BrB, [(PPCbctrl)]>,
546 Requires<[In32BitMode]>;
550 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
551 def TCRETURNdi :Pseudo< (outs),
552 (ins calltarget:$dst, i32imm:$offset),
553 "#TC_RETURNd $dst $offset",
557 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
558 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
559 "#TC_RETURNa $func $offset",
560 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
562 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
563 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
564 "#TC_RETURNr $dst $offset",
568 let isCodeGenOnly = 1 in {
570 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
571 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
572 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
573 Requires<[In32BitMode]>;
577 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
578 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
579 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
585 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
586 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
587 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
591 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
592 def EH_SjLj_SetJmp32 : Pseudo<(outs GPRC:$dst), (ins memr:$buf),
594 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
595 Requires<[In32BitMode]>;
596 let isTerminator = 1 in
597 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
598 "#EH_SJLJ_LONGJMP32",
599 [(PPCeh_sjlj_longjmp addr:$buf)]>,
600 Requires<[In32BitMode]>;
603 let isBranch = 1, isTerminator = 1 in {
604 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
605 "#EH_SjLj_Setup\t$dst", []>;
608 // DCB* instructions.
609 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
610 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
611 PPC970_DGroup_Single;
612 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
613 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
614 PPC970_DGroup_Single;
615 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
616 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
617 PPC970_DGroup_Single;
618 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
619 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
620 PPC970_DGroup_Single;
621 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
622 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
623 PPC970_DGroup_Single;
624 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
625 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
626 PPC970_DGroup_Single;
627 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
628 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
629 PPC970_DGroup_Single;
630 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
631 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
632 PPC970_DGroup_Single;
634 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
638 let usesCustomInserter = 1 in {
639 let Defs = [CR0] in {
640 def ATOMIC_LOAD_ADD_I8 : Pseudo<
641 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I8",
642 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
643 def ATOMIC_LOAD_SUB_I8 : Pseudo<
644 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I8",
645 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
646 def ATOMIC_LOAD_AND_I8 : Pseudo<
647 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I8",
648 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
649 def ATOMIC_LOAD_OR_I8 : Pseudo<
650 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I8",
651 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
652 def ATOMIC_LOAD_XOR_I8 : Pseudo<
653 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "ATOMIC_LOAD_XOR_I8",
654 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
655 def ATOMIC_LOAD_NAND_I8 : Pseudo<
656 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I8",
657 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
658 def ATOMIC_LOAD_ADD_I16 : Pseudo<
659 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I16",
660 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
661 def ATOMIC_LOAD_SUB_I16 : Pseudo<
662 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I16",
663 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
664 def ATOMIC_LOAD_AND_I16 : Pseudo<
665 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I16",
666 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
667 def ATOMIC_LOAD_OR_I16 : Pseudo<
668 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I16",
669 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
670 def ATOMIC_LOAD_XOR_I16 : Pseudo<
671 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I16",
672 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
673 def ATOMIC_LOAD_NAND_I16 : Pseudo<
674 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I16",
675 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
676 def ATOMIC_LOAD_ADD_I32 : Pseudo<
677 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I32",
678 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
679 def ATOMIC_LOAD_SUB_I32 : Pseudo<
680 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I32",
681 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
682 def ATOMIC_LOAD_AND_I32 : Pseudo<
683 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I32",
684 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
685 def ATOMIC_LOAD_OR_I32 : Pseudo<
686 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I32",
687 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
688 def ATOMIC_LOAD_XOR_I32 : Pseudo<
689 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I32",
690 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
691 def ATOMIC_LOAD_NAND_I32 : Pseudo<
692 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I32",
693 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
695 def ATOMIC_CMP_SWAP_I8 : Pseudo<
696 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I8",
697 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
698 def ATOMIC_CMP_SWAP_I16 : Pseudo<
699 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
700 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
701 def ATOMIC_CMP_SWAP_I32 : Pseudo<
702 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
703 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
705 def ATOMIC_SWAP_I8 : Pseudo<
706 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_i8",
707 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
708 def ATOMIC_SWAP_I16 : Pseudo<
709 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I16",
710 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
711 def ATOMIC_SWAP_I32 : Pseudo<
712 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I32",
713 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
717 // Instructions to support atomic operations
718 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
719 "lwarx $rD, $src", LdStLWARX,
720 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
723 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
724 "stwcx. $rS, $dst", LdStSTWCX,
725 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
728 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
729 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
731 //===----------------------------------------------------------------------===//
732 // PPC32 Load Instructions.
735 // Unindexed (r+i) Loads.
736 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
737 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
738 "lbz $rD, $src", LdStLoad,
739 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
740 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
741 "lha $rD, $src", LdStLHA,
742 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
743 PPC970_DGroup_Cracked;
744 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
745 "lhz $rD, $src", LdStLoad,
746 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
747 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
748 "lwz $rD, $src", LdStLoad,
749 [(set i32:$rD, (load iaddr:$src))]>;
751 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
752 "lfs $rD, $src", LdStLFD,
753 [(set f32:$rD, (load iaddr:$src))]>;
754 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
755 "lfd $rD, $src", LdStLFD,
756 [(set f64:$rD, (load iaddr:$src))]>;
759 // Unindexed (r+i) Loads with Update (preinc).
761 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
762 "lbzu $rD, $addr", LdStLoadUpd,
763 []>, RegConstraint<"$addr.reg = $ea_result">,
764 NoEncode<"$ea_result">;
766 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
767 "lhau $rD, $addr", LdStLHAU,
768 []>, RegConstraint<"$addr.reg = $ea_result">,
769 NoEncode<"$ea_result">;
771 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
772 "lhzu $rD, $addr", LdStLoadUpd,
773 []>, RegConstraint<"$addr.reg = $ea_result">,
774 NoEncode<"$ea_result">;
776 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
777 "lwzu $rD, $addr", LdStLoadUpd,
778 []>, RegConstraint<"$addr.reg = $ea_result">,
779 NoEncode<"$ea_result">;
781 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
782 "lfsu $rD, $addr", LdStLFDU,
783 []>, RegConstraint<"$addr.reg = $ea_result">,
784 NoEncode<"$ea_result">;
786 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
787 "lfdu $rD, $addr", LdStLFDU,
788 []>, RegConstraint<"$addr.reg = $ea_result">,
789 NoEncode<"$ea_result">;
792 // Indexed (r+r) Loads with Update (preinc).
793 def LBZUX : XForm_1<31, 119, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
795 "lbzux $rD, $addr", LdStLoadUpd,
796 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
797 NoEncode<"$ea_result">;
799 def LHAUX : XForm_1<31, 375, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
801 "lhaux $rD, $addr", LdStLHAU,
802 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
803 NoEncode<"$ea_result">;
805 def LHZUX : XForm_1<31, 311, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
807 "lhzux $rD, $addr", LdStLoadUpd,
808 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
809 NoEncode<"$ea_result">;
811 def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
813 "lwzux $rD, $addr", LdStLoadUpd,
814 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
815 NoEncode<"$ea_result">;
817 def LFSUX : XForm_1<31, 567, (outs F4RC:$rD, ptr_rc_nor0:$ea_result),
819 "lfsux $rD, $addr", LdStLFDU,
820 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
821 NoEncode<"$ea_result">;
823 def LFDUX : XForm_1<31, 631, (outs F8RC:$rD, ptr_rc_nor0:$ea_result),
825 "lfdux $rD, $addr", LdStLFDU,
826 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
827 NoEncode<"$ea_result">;
831 // Indexed (r+r) Loads.
833 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
834 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
835 "lbzx $rD, $src", LdStLoad,
836 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
837 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
838 "lhax $rD, $src", LdStLHA,
839 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
840 PPC970_DGroup_Cracked;
841 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
842 "lhzx $rD, $src", LdStLoad,
843 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
844 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
845 "lwzx $rD, $src", LdStLoad,
846 [(set i32:$rD, (load xaddr:$src))]>;
849 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
850 "lhbrx $rD, $src", LdStLoad,
851 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
852 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
853 "lwbrx $rD, $src", LdStLoad,
854 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
856 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
857 "lfsx $frD, $src", LdStLFD,
858 [(set f32:$frD, (load xaddr:$src))]>;
859 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
860 "lfdx $frD, $src", LdStLFD,
861 [(set f64:$frD, (load xaddr:$src))]>;
863 def LFIWAX : XForm_25<31, 855, (outs F8RC:$frD), (ins memrr:$src),
864 "lfiwax $frD, $src", LdStLFD,
865 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
866 def LFIWZX : XForm_25<31, 887, (outs F8RC:$frD), (ins memrr:$src),
867 "lfiwzx $frD, $src", LdStLFD,
868 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
871 //===----------------------------------------------------------------------===//
872 // PPC32 Store Instructions.
875 // Unindexed (r+i) Stores.
876 let PPC970_Unit = 2 in {
877 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
878 "stb $rS, $src", LdStStore,
879 [(truncstorei8 i32:$rS, iaddr:$src)]>;
880 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
881 "sth $rS, $src", LdStStore,
882 [(truncstorei16 i32:$rS, iaddr:$src)]>;
883 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
884 "stw $rS, $src", LdStStore,
885 [(store i32:$rS, iaddr:$src)]>;
886 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
887 "stfs $rS, $dst", LdStSTFD,
888 [(store f32:$rS, iaddr:$dst)]>;
889 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
890 "stfd $rS, $dst", LdStSTFD,
891 [(store f64:$rS, iaddr:$dst)]>;
894 // Unindexed (r+i) Stores with Update (preinc).
895 let PPC970_Unit = 2, mayStore = 1 in {
896 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
897 "stbu $rS, $dst", LdStStoreUpd, []>,
898 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
899 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
900 "sthu $rS, $dst", LdStStoreUpd, []>,
901 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
902 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
903 "stwu $rS, $dst", LdStStoreUpd, []>,
904 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
905 def STFSU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memri:$dst),
906 "stfsu $rS, $dst", LdStSTFDU, []>,
907 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
908 def STFDU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memri:$dst),
909 "stfdu $rS, $dst", LdStSTFDU, []>,
910 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
913 // Patterns to match the pre-inc stores. We can't put the patterns on
914 // the instruction definitions directly as ISel wants the address base
915 // and offset to be separate operands, not a single complex operand.
916 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
917 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
918 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
919 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
920 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
921 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
922 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
923 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
924 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
925 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
927 // Indexed (r+r) Stores.
928 let PPC970_Unit = 2 in {
929 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
930 "stbx $rS, $dst", LdStStore,
931 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
932 PPC970_DGroup_Cracked;
933 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
934 "sthx $rS, $dst", LdStStore,
935 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
936 PPC970_DGroup_Cracked;
937 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
938 "stwx $rS, $dst", LdStStore,
939 [(store i32:$rS, xaddr:$dst)]>,
940 PPC970_DGroup_Cracked;
942 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
943 "sthbrx $rS, $dst", LdStStore,
944 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
945 PPC970_DGroup_Cracked;
946 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
947 "stwbrx $rS, $dst", LdStStore,
948 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
949 PPC970_DGroup_Cracked;
951 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
952 "stfiwx $frS, $dst", LdStSTFD,
953 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
955 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
956 "stfsx $frS, $dst", LdStSTFD,
957 [(store f32:$frS, xaddr:$dst)]>;
958 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
959 "stfdx $frS, $dst", LdStSTFD,
960 [(store f64:$frS, xaddr:$dst)]>;
963 // Indexed (r+r) Stores with Update (preinc).
964 let PPC970_Unit = 2, mayStore = 1 in {
965 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
966 "stbux $rS, $dst", LdStStoreUpd, []>,
967 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
968 PPC970_DGroup_Cracked;
969 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
970 "sthux $rS, $dst", LdStStoreUpd, []>,
971 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
972 PPC970_DGroup_Cracked;
973 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
974 "stwux $rS, $dst", LdStStoreUpd, []>,
975 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
976 PPC970_DGroup_Cracked;
977 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memrr:$dst),
978 "stfsux $rS, $dst", LdStSTFDU, []>,
979 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
980 PPC970_DGroup_Cracked;
981 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memrr:$dst),
982 "stfdux $rS, $dst", LdStSTFDU, []>,
983 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
984 PPC970_DGroup_Cracked;
987 // Patterns to match the pre-inc stores. We can't put the patterns on
988 // the instruction definitions directly as ISel wants the address base
989 // and offset to be separate operands, not a single complex operand.
990 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
991 (STBUX $rS, $ptrreg, $ptroff)>;
992 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
993 (STHUX $rS, $ptrreg, $ptroff)>;
994 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
995 (STWUX $rS, $ptrreg, $ptroff)>;
996 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
997 (STFSUX $rS, $ptrreg, $ptroff)>;
998 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
999 (STFDUX $rS, $ptrreg, $ptroff)>;
1001 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
1005 //===----------------------------------------------------------------------===//
1006 // PPC32 Arithmetic Instructions.
1009 let PPC970_Unit = 1 in { // FXU Operations.
1010 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$imm),
1011 "addi $rD, $rA, $imm", IntSimple,
1012 [(set i32:$rD, (add i32:$rA, immSExt16:$imm))]>;
1013 let Defs = [CARRY] in {
1014 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1015 "addic $rD, $rA, $imm", IntGeneral,
1016 [(set i32:$rD, (addc i32:$rA, immSExt16:$imm))]>,
1017 PPC970_DGroup_Cracked;
1018 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1019 "addic. $rD, $rA, $imm", IntGeneral,
1022 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolHi:$imm),
1023 "addis $rD, $rA, $imm", IntSimple,
1024 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1025 let isCodeGenOnly = 1 in
1026 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$sym),
1027 "la $rD, $sym($rA)", IntGeneral,
1028 [(set i32:$rD, (add i32:$rA,
1029 (PPClo tglobaladdr:$sym, 0)))]>;
1030 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1031 "mulli $rD, $rA, $imm", IntMulLI,
1032 [(set i32:$rD, (mul i32:$rA, immSExt16:$imm))]>;
1033 let Defs = [CARRY] in {
1034 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1035 "subfic $rD, $rA, $imm", IntGeneral,
1036 [(set i32:$rD, (subc immSExt16:$imm, i32:$rA))]>;
1039 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1040 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
1041 "li $rD, $imm", IntSimple,
1042 [(set i32:$rD, immSExt16:$imm)]>;
1043 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
1044 "lis $rD, $imm", IntSimple,
1045 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1049 let PPC970_Unit = 1 in { // FXU Operations.
1050 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1051 "andi. $dst, $src1, $src2", IntGeneral,
1052 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1054 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1055 "andis. $dst, $src1, $src2", IntGeneral,
1056 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1058 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1059 "ori $dst, $src1, $src2", IntSimple,
1060 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1061 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1062 "oris $dst, $src1, $src2", IntSimple,
1063 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1064 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1065 "xori $dst, $src1, $src2", IntSimple,
1066 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1067 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1068 "xoris $dst, $src1, $src2", IntSimple,
1069 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1070 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
1072 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
1073 "cmpwi $crD, $rA, $imm", IntCompare>;
1074 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1075 "cmplwi $dst, $src1, $src2", IntCompare>;
1079 let PPC970_Unit = 1 in { // FXU Operations.
1080 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1081 "nand $rA, $rS, $rB", IntSimple,
1082 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1083 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1084 "and $rA, $rS, $rB", IntSimple,
1085 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1086 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1087 "andc $rA, $rS, $rB", IntSimple,
1088 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1089 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1090 "or $rA, $rS, $rB", IntSimple,
1091 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1092 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1093 "nor $rA, $rS, $rB", IntSimple,
1094 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1095 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1096 "orc $rA, $rS, $rB", IntSimple,
1097 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1098 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1099 "eqv $rA, $rS, $rB", IntSimple,
1100 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1101 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1102 "xor $rA, $rS, $rB", IntSimple,
1103 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1104 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1105 "slw $rA, $rS, $rB", IntGeneral,
1106 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1107 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1108 "srw $rA, $rS, $rB", IntGeneral,
1109 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1110 let Defs = [CARRY] in {
1111 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1112 "sraw $rA, $rS, $rB", IntShift,
1113 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1117 let PPC970_Unit = 1 in { // FXU Operations.
1118 let Defs = [CARRY] in {
1119 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
1120 "srawi $rA, $rS, $SH", IntShift,
1121 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1123 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
1124 "cntlzw $rA, $rS", IntGeneral,
1125 [(set i32:$rA, (ctlz i32:$rS))]>;
1126 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
1127 "extsb $rA, $rS", IntSimple,
1128 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1129 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
1130 "extsh $rA, $rS", IntSimple,
1131 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1133 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1134 "cmpw $crD, $rA, $rB", IntCompare>;
1135 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1136 "cmplw $crD, $rA, $rB", IntCompare>;
1138 let PPC970_Unit = 3 in { // FPU Operations.
1139 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1140 // "fcmpo $crD, $fA, $fB", FPCompare>;
1141 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
1142 "fcmpu $crD, $fA, $fB", FPCompare>;
1143 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
1144 "fcmpu $crD, $fA, $fB", FPCompare>;
1146 let Uses = [RM] in {
1147 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
1148 "fctiwz $frD, $frB", FPGeneral,
1149 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1151 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
1152 "frsp $frD, $frB", FPGeneral,
1153 [(set f32:$frD, (fround f64:$frB))]>;
1155 // The frin -> nearbyint mapping is valid only in fast-math mode.
1156 def FRIND : XForm_26<63, 392, (outs F8RC:$frD), (ins F8RC:$frB),
1157 "frin $frD, $frB", FPGeneral,
1158 [(set f64:$frD, (fnearbyint f64:$frB))]>;
1159 def FRINS : XForm_26<63, 392, (outs F4RC:$frD), (ins F4RC:$frB),
1160 "frin $frD, $frB", FPGeneral,
1161 [(set f32:$frD, (fnearbyint f32:$frB))]>;
1163 // These pseudos expand to rint but also set FE_INEXACT when the result does
1164 // not equal the argument.
1165 let usesCustomInserter = 1, Defs = [RM] in { // FIXME: Model FPSCR!
1166 def FRINDrint : Pseudo<(outs F8RC:$frD), (ins F8RC:$frB),
1167 "#FRINDrint", [(set f64:$frD, (frint f64:$frB))]>;
1168 def FRINSrint : Pseudo<(outs F4RC:$frD), (ins F4RC:$frB),
1169 "#FRINSrint", [(set f32:$frD, (frint f32:$frB))]>;
1172 def FRIPD : XForm_26<63, 456, (outs F8RC:$frD), (ins F8RC:$frB),
1173 "frip $frD, $frB", FPGeneral,
1174 [(set f64:$frD, (fceil f64:$frB))]>;
1175 def FRIPS : XForm_26<63, 456, (outs F4RC:$frD), (ins F4RC:$frB),
1176 "frip $frD, $frB", FPGeneral,
1177 [(set f32:$frD, (fceil f32:$frB))]>;
1178 def FRIZD : XForm_26<63, 424, (outs F8RC:$frD), (ins F8RC:$frB),
1179 "friz $frD, $frB", FPGeneral,
1180 [(set f64:$frD, (ftrunc f64:$frB))]>;
1181 def FRIZS : XForm_26<63, 424, (outs F4RC:$frD), (ins F4RC:$frB),
1182 "friz $frD, $frB", FPGeneral,
1183 [(set f32:$frD, (ftrunc f32:$frB))]>;
1184 def FRIMD : XForm_26<63, 488, (outs F8RC:$frD), (ins F8RC:$frB),
1185 "frim $frD, $frB", FPGeneral,
1186 [(set f64:$frD, (ffloor f64:$frB))]>;
1187 def FRIMS : XForm_26<63, 488, (outs F4RC:$frD), (ins F4RC:$frB),
1188 "frim $frD, $frB", FPGeneral,
1189 [(set f32:$frD, (ffloor f32:$frB))]>;
1191 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
1192 "fsqrt $frD, $frB", FPSqrt,
1193 [(set f64:$frD, (fsqrt f64:$frB))]>;
1194 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
1195 "fsqrts $frD, $frB", FPSqrt,
1196 [(set f32:$frD, (fsqrt f32:$frB))]>;
1200 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1201 /// often coalesced away and we don't want the dispatch group builder to think
1202 /// that they will fill slots (which could cause the load of a LSU reject to
1203 /// sneak into a d-group with a store).
1204 def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1205 "fmr $frD, $frB", FPGeneral,
1206 []>, // (set f32:$frD, f32:$frB)
1209 let PPC970_Unit = 3 in { // FPU Operations.
1210 // These are artificially split into two different forms, for 4/8 byte FP.
1211 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1212 "fabs $frD, $frB", FPGeneral,
1213 [(set f32:$frD, (fabs f32:$frB))]>;
1214 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1215 "fabs $frD, $frB", FPGeneral,
1216 [(set f64:$frD, (fabs f64:$frB))]>;
1217 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1218 "fnabs $frD, $frB", FPGeneral,
1219 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1220 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1221 "fnabs $frD, $frB", FPGeneral,
1222 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1223 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1224 "fneg $frD, $frB", FPGeneral,
1225 [(set f32:$frD, (fneg f32:$frB))]>;
1226 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1227 "fneg $frD, $frB", FPGeneral,
1228 [(set f64:$frD, (fneg f64:$frB))]>;
1230 // Reciprocal estimates.
1231 def FRE : XForm_26<63, 24, (outs F8RC:$frD), (ins F8RC:$frB),
1232 "fre $frD, $frB", FPGeneral,
1233 [(set f64:$frD, (PPCfre f64:$frB))]>;
1234 def FRES : XForm_26<59, 24, (outs F4RC:$frD), (ins F4RC:$frB),
1235 "fres $frD, $frB", FPGeneral,
1236 [(set f32:$frD, (PPCfre f32:$frB))]>;
1237 def FRSQRTE : XForm_26<63, 26, (outs F8RC:$frD), (ins F8RC:$frB),
1238 "frsqrte $frD, $frB", FPGeneral,
1239 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1240 def FRSQRTES : XForm_26<59, 26, (outs F4RC:$frD), (ins F4RC:$frB),
1241 "frsqrtes $frD, $frB", FPGeneral,
1242 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1245 // XL-Form instructions. condition register logical ops.
1247 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1248 "mcrf $BF, $BFA", BrMCR>,
1249 PPC970_DGroup_First, PPC970_Unit_CRU;
1251 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1252 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1253 "creqv $CRD, $CRA, $CRB", BrCR,
1256 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1257 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1258 "cror $CRD, $CRA, $CRB", BrCR,
1261 let isCodeGenOnly = 1 in {
1262 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1263 "creqv $dst, $dst, $dst", BrCR,
1266 def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins),
1267 "crxor $dst, $dst, $dst", BrCR,
1270 let Defs = [CR1EQ], CRD = 6 in {
1271 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1272 "creqv 6, 6, 6", BrCR,
1275 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1276 "crxor 6, 6, 6", BrCR,
1281 // XFX-Form instructions. Instructions that deal with SPRs.
1283 let Uses = [CTR] in {
1284 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1285 "mfctr $rT", SprMFSPR>,
1286 PPC970_DGroup_First, PPC970_Unit_FXU;
1288 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
1289 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1290 "mtctr $rS", SprMTSPR>,
1291 PPC970_DGroup_First, PPC970_Unit_FXU;
1294 let Defs = [LR] in {
1295 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1296 "mtlr $rS", SprMTSPR>,
1297 PPC970_DGroup_First, PPC970_Unit_FXU;
1299 let Uses = [LR] in {
1300 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1301 "mflr $rT", SprMFSPR>,
1302 PPC970_DGroup_First, PPC970_Unit_FXU;
1305 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1306 // a GPR on the PPC970. As such, copies in and out have the same performance
1307 // characteristics as an OR instruction.
1308 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1309 "mtspr 256, $rS", IntGeneral>,
1310 PPC970_DGroup_Single, PPC970_Unit_FXU;
1311 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1312 "mfspr $rT, 256", IntGeneral>,
1313 PPC970_DGroup_First, PPC970_Unit_FXU;
1315 let isCodeGenOnly = 1 in {
1316 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
1317 (outs VRSAVERC:$reg), (ins GPRC:$rS),
1318 "mtspr 256, $rS", IntGeneral>,
1319 PPC970_DGroup_Single, PPC970_Unit_FXU;
1320 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT),
1321 (ins VRSAVERC:$reg),
1322 "mfspr $rT, 256", IntGeneral>,
1323 PPC970_DGroup_First, PPC970_Unit_FXU;
1326 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
1327 // so we'll need to scavenge a register for it.
1329 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
1330 "#SPILL_VRSAVE", []>;
1332 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
1333 // spilled), so we'll need to scavenge a register for it.
1335 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
1336 "#RESTORE_VRSAVE", []>;
1338 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS),
1339 "mtcrf $FXM, $rS", BrMCRX>,
1340 PPC970_MicroCode, PPC970_Unit_CRU;
1342 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1343 // declaring that here gives the local register allocator problems with this:
1345 // MFCR <kill of whatever preg got assigned to vreg>
1346 // while not declaring it breaks DeadMachineInstructionElimination.
1347 // As it turns out, in all cases where we currently use this,
1348 // we're only interested in one subregister of it. Represent this in the
1349 // instruction to keep the register allocator from becoming confused.
1351 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1352 let isCodeGenOnly = 1 in
1353 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1354 "#MFCRpseud", SprMFCR>,
1355 PPC970_MicroCode, PPC970_Unit_CRU;
1357 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
1358 "mfcr $rT", SprMFCR>,
1359 PPC970_MicroCode, PPC970_Unit_CRU;
1361 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1362 "mfocrf $rT, $FXM", SprMFCR>,
1363 PPC970_DGroup_First, PPC970_Unit_CRU;
1365 // Pseudo instruction to perform FADD in round-to-zero mode.
1366 let usesCustomInserter = 1, Uses = [RM] in {
1367 def FADDrtz: Pseudo<(outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), "",
1368 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
1371 // The above pseudo gets expanded to make use of the following instructions
1372 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
1373 let Uses = [RM], Defs = [RM] in {
1374 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1375 "mtfsb0 $FM", IntMTFSB0, []>,
1376 PPC970_DGroup_Single, PPC970_Unit_FPU;
1377 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1378 "mtfsb1 $FM", IntMTFSB0, []>,
1379 PPC970_DGroup_Single, PPC970_Unit_FPU;
1380 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, F8RC:$rT),
1381 "mtfsf $FM, $rT", IntMTFSB0, []>,
1382 PPC970_DGroup_Single, PPC970_Unit_FPU;
1384 let Uses = [RM] in {
1385 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1386 "mffs $rT", IntMFFS,
1387 [(set f64:$rT, (PPCmffs))]>,
1388 PPC970_DGroup_Single, PPC970_Unit_FPU;
1392 let PPC970_Unit = 1 in { // FXU Operations.
1394 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1396 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1397 "add $rT, $rA, $rB", IntSimple,
1398 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
1399 let Defs = [CARRY] in {
1400 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1401 "addc $rT, $rA, $rB", IntGeneral,
1402 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
1403 PPC970_DGroup_Cracked;
1405 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1406 "divw $rT, $rA, $rB", IntDivW,
1407 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
1408 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1409 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1410 "divwu $rT, $rA, $rB", IntDivW,
1411 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
1412 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1413 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1414 "mulhw $rT, $rA, $rB", IntMulHW,
1415 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
1416 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1417 "mulhwu $rT, $rA, $rB", IntMulHWU,
1418 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
1419 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1420 "mullw $rT, $rA, $rB", IntMulHW,
1421 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
1422 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1423 "subf $rT, $rA, $rB", IntGeneral,
1424 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
1425 let Defs = [CARRY] in {
1426 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1427 "subfc $rT, $rA, $rB", IntGeneral,
1428 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
1429 PPC970_DGroup_Cracked;
1431 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1432 "neg $rT, $rA", IntSimple,
1433 [(set i32:$rT, (ineg i32:$rA))]>;
1434 let Uses = [CARRY], Defs = [CARRY] in {
1435 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1436 "adde $rT, $rA, $rB", IntGeneral,
1437 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
1438 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1439 "addme $rT, $rA", IntGeneral,
1440 [(set i32:$rT, (adde i32:$rA, -1))]>;
1441 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1442 "addze $rT, $rA", IntGeneral,
1443 [(set i32:$rT, (adde i32:$rA, 0))]>;
1444 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1445 "subfe $rT, $rA, $rB", IntGeneral,
1446 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
1447 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1448 "subfme $rT, $rA", IntGeneral,
1449 [(set i32:$rT, (sube -1, i32:$rA))]>;
1450 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1451 "subfze $rT, $rA", IntGeneral,
1452 [(set i32:$rT, (sube 0, i32:$rA))]>;
1456 // A-Form instructions. Most of the instructions executed in the FPU are of
1459 let PPC970_Unit = 3 in { // FPU Operations.
1460 let Uses = [RM] in {
1461 def FMADD : AForm_1<63, 29,
1462 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1463 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1464 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
1465 def FMADDS : AForm_1<59, 29,
1466 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1467 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1468 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
1469 def FMSUB : AForm_1<63, 28,
1470 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1471 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1473 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
1474 def FMSUBS : AForm_1<59, 28,
1475 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1476 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1478 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
1479 def FNMADD : AForm_1<63, 31,
1480 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1481 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1483 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
1484 def FNMADDS : AForm_1<59, 31,
1485 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1486 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1488 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
1489 def FNMSUB : AForm_1<63, 30,
1490 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1491 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1492 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
1493 (fneg f64:$FRB))))]>;
1494 def FNMSUBS : AForm_1<59, 30,
1495 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1496 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1497 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
1498 (fneg f32:$FRB))))]>;
1500 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1501 // having 4 of these, force the comparison to always be an 8-byte double (code
1502 // should use an FMRSD if the input comparison value really wants to be a float)
1503 // and 4/8 byte forms for the result and operand type..
1504 def FSELD : AForm_1<63, 23,
1505 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1506 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1507 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
1508 def FSELS : AForm_1<63, 23,
1509 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1510 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1511 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
1512 let Uses = [RM] in {
1513 def FADD : AForm_2<63, 21,
1514 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1515 "fadd $FRT, $FRA, $FRB", FPAddSub,
1516 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
1517 def FADDS : AForm_2<59, 21,
1518 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1519 "fadds $FRT, $FRA, $FRB", FPGeneral,
1520 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
1521 def FDIV : AForm_2<63, 18,
1522 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1523 "fdiv $FRT, $FRA, $FRB", FPDivD,
1524 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
1525 def FDIVS : AForm_2<59, 18,
1526 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1527 "fdivs $FRT, $FRA, $FRB", FPDivS,
1528 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
1529 def FMUL : AForm_3<63, 25,
1530 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC),
1531 "fmul $FRT, $FRA, $FRC", FPFused,
1532 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
1533 def FMULS : AForm_3<59, 25,
1534 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC),
1535 "fmuls $FRT, $FRA, $FRC", FPGeneral,
1536 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
1537 def FSUB : AForm_2<63, 20,
1538 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1539 "fsub $FRT, $FRA, $FRB", FPAddSub,
1540 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
1541 def FSUBS : AForm_2<59, 20,
1542 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1543 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1544 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
1548 let PPC970_Unit = 1 in { // FXU Operations.
1549 def ISEL : AForm_4<31, 15,
1550 (outs GPRC:$rT), (ins GPRC_NOR0:$rA, GPRC:$rB, CRBITRC:$cond),
1551 "isel $rT, $rA, $rB, $cond", IntGeneral,
1555 let PPC970_Unit = 1 in { // FXU Operations.
1556 // M-Form instructions. rotate and mask instructions.
1558 let isCommutable = 1 in {
1559 // RLWIMI can be commuted if the rotate amount is zero.
1560 def RLWIMI : MForm_2<20,
1561 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1562 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1563 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1566 def RLWINM : MForm_2<21,
1567 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1568 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1570 def RLWINMo : MForm_2<21,
1571 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1572 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1573 []>, isDOT, PPC970_DGroup_Cracked;
1574 def RLWNM : MForm_2<23,
1575 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1576 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1581 //===----------------------------------------------------------------------===//
1582 // PowerPC Instruction Patterns
1585 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1586 def : Pat<(i32 imm:$imm),
1587 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1589 // Implement the 'not' operation with the NOR instruction.
1590 def NOT : Pat<(not i32:$in),
1593 // ADD an arbitrary immediate.
1594 def : Pat<(add i32:$in, imm:$imm),
1595 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1596 // OR an arbitrary immediate.
1597 def : Pat<(or i32:$in, imm:$imm),
1598 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1599 // XOR an arbitrary immediate.
1600 def : Pat<(xor i32:$in, imm:$imm),
1601 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1603 def : Pat<(sub immSExt16:$imm, i32:$in),
1604 (SUBFIC $in, imm:$imm)>;
1607 def : Pat<(shl i32:$in, (i32 imm:$imm)),
1608 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
1609 def : Pat<(srl i32:$in, (i32 imm:$imm)),
1610 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
1613 def : Pat<(rotl i32:$in, i32:$sh),
1614 (RLWNM $in, $sh, 0, 31)>;
1615 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
1616 (RLWINM $in, imm:$imm, 0, 31)>;
1619 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
1620 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1623 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
1624 (BL tglobaladdr:$dst)>;
1625 def : Pat<(PPCcall (i32 texternalsym:$dst)),
1626 (BL texternalsym:$dst)>;
1629 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1630 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1632 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1633 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1635 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1636 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1640 // Hi and Lo for Darwin Global Addresses.
1641 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1642 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1643 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1644 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1645 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1646 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1647 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
1648 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
1649 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
1650 (ADDIS $in, tglobaltlsaddr:$g)>;
1651 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
1652 (ADDI $in, tglobaltlsaddr:$g)>;
1653 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
1654 (ADDIS $in, tglobaladdr:$g)>;
1655 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
1656 (ADDIS $in, tconstpool:$g)>;
1657 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
1658 (ADDIS $in, tjumptable:$g)>;
1659 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
1660 (ADDIS $in, tblockaddress:$g)>;
1662 // Standard shifts. These are represented separately from the real shifts above
1663 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1665 def : Pat<(sra i32:$rS, i32:$rB),
1667 def : Pat<(srl i32:$rS, i32:$rB),
1669 def : Pat<(shl i32:$rS, i32:$rB),
1672 def : Pat<(zextloadi1 iaddr:$src),
1674 def : Pat<(zextloadi1 xaddr:$src),
1676 def : Pat<(extloadi1 iaddr:$src),
1678 def : Pat<(extloadi1 xaddr:$src),
1680 def : Pat<(extloadi8 iaddr:$src),
1682 def : Pat<(extloadi8 xaddr:$src),
1684 def : Pat<(extloadi16 iaddr:$src),
1686 def : Pat<(extloadi16 xaddr:$src),
1688 def : Pat<(f64 (extloadf32 iaddr:$src)),
1689 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1690 def : Pat<(f64 (extloadf32 xaddr:$src)),
1691 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1693 def : Pat<(f64 (fextend f32:$src)),
1694 (COPY_TO_REGCLASS $src, F8RC)>;
1697 def : Pat<(membarrier (i32 imm /*ll*/),
1701 (i32 imm /*device*/)),
1704 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
1706 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
1707 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
1708 (FNMSUB $A, $C, $B)>;
1709 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
1710 (FNMSUB $A, $C, $B)>;
1711 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
1712 (FNMSUBS $A, $C, $B)>;
1713 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
1714 (FNMSUBS $A, $C, $B)>;
1716 include "PPCInstrAltivec.td"
1717 include "PPCInstr64Bit.td"