1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
61 //===----------------------------------------------------------------------===//
62 // PowerPC specific DAG Nodes.
65 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
66 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
68 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
69 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
70 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
71 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
72 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
73 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
74 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
75 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
76 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
77 [SDNPHasChain, SDNPMayStore]>;
78 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
79 [SDNPHasChain, SDNPMayLoad]>;
80 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
81 [SDNPHasChain, SDNPMayLoad]>;
83 // Extract FPSCR (not modeled at the DAG level).
84 def PPCmffs : SDNode<"PPCISD::MFFS",
85 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
87 // Perform FADD in round-to-zero mode.
88 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
91 def PPCfsel : SDNode<"PPCISD::FSEL",
92 // Type constraint for fsel.
93 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
94 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
96 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
97 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
98 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
99 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
100 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
102 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
103 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
105 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
106 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
107 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
108 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
109 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
110 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
111 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
112 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
114 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
116 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
118 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
119 // amounts. These nodes are generated by the multi-precision shift code.
120 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
121 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
122 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
124 // These are target-independent nodes, but have target-specific formats.
125 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
126 [SDNPHasChain, SDNPOutGlue]>;
127 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
128 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
130 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
131 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
134 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
135 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
137 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
139 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
140 [SDNPHasChain, SDNPSideEffect,
141 SDNPInGlue, SDNPOutGlue]>;
142 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
143 [SDNPHasChain, SDNPSideEffect,
144 SDNPInGlue, SDNPOutGlue]>;
145 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
147 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
151 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
152 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
154 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
157 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
158 SDTypeProfile<1, 1, [SDTCisInt<0>,
160 [SDNPHasChain, SDNPSideEffect]>;
161 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
162 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
163 [SDNPHasChain, SDNPSideEffect]>;
165 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
166 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
168 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
169 [SDNPHasChain, SDNPOptInGlue]>;
171 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
172 [SDNPHasChain, SDNPMayLoad]>;
173 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
174 [SDNPHasChain, SDNPMayStore]>;
176 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
177 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
178 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
179 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
180 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
182 // Instructions to support atomic operations
183 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
184 [SDNPHasChain, SDNPMayLoad]>;
185 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
186 [SDNPHasChain, SDNPMayStore]>;
188 // Instructions to support medium and large code model
189 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
190 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
191 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
194 // Instructions to support dynamic alloca.
195 def SDTDynOp : SDTypeProfile<1, 2, []>;
196 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
198 //===----------------------------------------------------------------------===//
199 // PowerPC specific transformation functions and pattern fragments.
202 def SHL32 : SDNodeXForm<imm, [{
203 // Transformation function: 31 - imm
204 return getI32Imm(31 - N->getZExtValue());
207 def SRL32 : SDNodeXForm<imm, [{
208 // Transformation function: 32 - imm
209 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
212 def LO16 : SDNodeXForm<imm, [{
213 // Transformation function: get the low 16 bits.
214 return getI32Imm((unsigned short)N->getZExtValue());
217 def HI16 : SDNodeXForm<imm, [{
218 // Transformation function: shift the immediate value down into the low bits.
219 return getI32Imm((unsigned)N->getZExtValue() >> 16);
222 def HA16 : SDNodeXForm<imm, [{
223 // Transformation function: shift the immediate value down into the low bits.
224 signed int Val = N->getZExtValue();
225 return getI32Imm((Val - (signed short)Val) >> 16);
227 def MB : SDNodeXForm<imm, [{
228 // Transformation function: get the start bit of a mask
230 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
231 return getI32Imm(mb);
234 def ME : SDNodeXForm<imm, [{
235 // Transformation function: get the end bit of a mask
237 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
238 return getI32Imm(me);
240 def maskimm32 : PatLeaf<(imm), [{
241 // maskImm predicate - True if immediate is a run of ones.
243 if (N->getValueType(0) == MVT::i32)
244 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
249 def immSExt16 : PatLeaf<(imm), [{
250 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
251 // field. Used by instructions like 'addi'.
252 if (N->getValueType(0) == MVT::i32)
253 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
255 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
257 def immZExt16 : PatLeaf<(imm), [{
258 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
259 // field. Used by instructions like 'ori'.
260 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
263 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
264 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
265 // identical in 32-bit mode, but in 64-bit mode, they return true if the
266 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
268 def imm16ShiftedZExt : PatLeaf<(imm), [{
269 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
270 // immediate are set. Used by instructions like 'xoris'.
271 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
274 def imm16ShiftedSExt : PatLeaf<(imm), [{
275 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
276 // immediate are set. Used by instructions like 'addis'. Identical to
277 // imm16ShiftedZExt in 32-bit mode.
278 if (N->getZExtValue() & 0xFFFF) return false;
279 if (N->getValueType(0) == MVT::i32)
281 // For 64-bit, make sure it is sext right.
282 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
285 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
286 // restricted memrix (offset/4) constants are alignment sensitive. If these
287 // offsets are hidden behind TOC entries than the values of the lower-order
288 // bits cannot be checked directly. As a result, we need to also incorporate
289 // an alignment check into the relevant patterns.
291 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
292 return cast<LoadSDNode>(N)->getAlignment() >= 4;
294 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
295 (store node:$val, node:$ptr), [{
296 return cast<StoreSDNode>(N)->getAlignment() >= 4;
298 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
299 return cast<LoadSDNode>(N)->getAlignment() >= 4;
301 def aligned4pre_store : PatFrag<
302 (ops node:$val, node:$base, node:$offset),
303 (pre_store node:$val, node:$base, node:$offset), [{
304 return cast<StoreSDNode>(N)->getAlignment() >= 4;
307 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
308 return cast<LoadSDNode>(N)->getAlignment() < 4;
310 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
311 (store node:$val, node:$ptr), [{
312 return cast<StoreSDNode>(N)->getAlignment() < 4;
314 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
315 return cast<LoadSDNode>(N)->getAlignment() < 4;
318 //===----------------------------------------------------------------------===//
319 // PowerPC Flag Definitions.
321 class isPPC64 { bit PPC64 = 1; }
322 class isDOT { bit RC = 1; }
324 class RegConstraint<string C> {
325 string Constraints = C;
327 class NoEncode<string E> {
328 string DisableEncoding = E;
332 //===----------------------------------------------------------------------===//
333 // PowerPC Operand Definitions.
335 def s5imm : Operand<i32> {
336 let PrintMethod = "printS5ImmOperand";
338 def u5imm : Operand<i32> {
339 let PrintMethod = "printU5ImmOperand";
341 def u6imm : Operand<i32> {
342 let PrintMethod = "printU6ImmOperand";
344 def s16imm : Operand<i32> {
345 let PrintMethod = "printS16ImmOperand";
347 def u16imm : Operand<i32> {
348 let PrintMethod = "printU16ImmOperand";
350 def directbrtarget : Operand<OtherVT> {
351 let PrintMethod = "printBranchOperand";
352 let EncoderMethod = "getDirectBrEncoding";
354 def condbrtarget : Operand<OtherVT> {
355 let PrintMethod = "printBranchOperand";
356 let EncoderMethod = "getCondBrEncoding";
358 def calltarget : Operand<iPTR> {
359 let EncoderMethod = "getDirectBrEncoding";
361 def aaddr : Operand<iPTR> {
362 let PrintMethod = "printAbsAddrOperand";
364 def symbolHi: Operand<i32> {
365 let PrintMethod = "printSymbolHi";
366 let EncoderMethod = "getHA16Encoding";
368 def symbolLo: Operand<i32> {
369 let PrintMethod = "printSymbolLo";
370 let EncoderMethod = "getLO16Encoding";
372 def crbitm: Operand<i8> {
373 let PrintMethod = "printcrbitm";
374 let EncoderMethod = "get_crbitm_encoding";
377 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
378 def ptr_rc_nor0 : PointerLikeRegClass<1>;
380 def dispRI : Operand<iPTR>;
381 def dispRIX : Operand<iPTR>;
383 def memri : Operand<iPTR> {
384 let PrintMethod = "printMemRegImm";
385 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
386 let EncoderMethod = "getMemRIEncoding";
388 def memrr : Operand<iPTR> {
389 let PrintMethod = "printMemRegReg";
390 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc:$offreg);
392 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
393 let PrintMethod = "printMemRegImmShifted";
394 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
395 let EncoderMethod = "getMemRIXEncoding";
398 // A single-register address. This is used with the SjLj
399 // pseudo-instructions.
400 def memr : Operand<iPTR> {
401 let MIOperandInfo = (ops ptr_rc:$ptrreg);
404 // PowerPC Predicate operand.
405 def pred : Operand<OtherVT> {
406 let PrintMethod = "printPredicateOperand";
407 let MIOperandInfo = (ops i32imm:$bibo, CRRC:$reg);
410 // Define PowerPC specific addressing mode.
411 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
412 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
413 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
414 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
416 // The address in a single register. This is used with the SjLj
417 // pseudo-instructions.
418 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
420 /// This is just the offset part of iaddr, used for preinc.
421 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
423 //===----------------------------------------------------------------------===//
424 // PowerPC Instruction Predicate Definitions.
425 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
426 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
427 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
429 //===----------------------------------------------------------------------===//
430 // PowerPC Multiclass Definitions.
432 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
433 string asmbase, string asmstr, InstrItinClass itin,
435 let BaseName = asmbase in {
436 def NAME : XForm_6<opcode, xo, OOL, IOL,
437 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
438 pattern>, RecFormRel;
440 def o : XForm_6<opcode, xo, OOL, IOL,
441 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
442 []>, isDOT, RecFormRel;
446 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
447 string asmbase, string asmstr, InstrItinClass itin,
449 let BaseName = asmbase in {
450 let Defs = [CARRY] in
451 def NAME : XForm_6<opcode, xo, OOL, IOL,
452 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
453 pattern>, RecFormRel;
454 let Defs = [CARRY, CR0] in
455 def o : XForm_6<opcode, xo, OOL, IOL,
456 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
457 []>, isDOT, RecFormRel;
461 multiclass XForm_10r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
462 string asmbase, string asmstr, InstrItinClass itin,
464 let BaseName = asmbase in {
465 def NAME : XForm_10<opcode, xo, OOL, IOL,
466 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
467 pattern>, RecFormRel;
469 def o : XForm_10<opcode, xo, OOL, IOL,
470 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
471 []>, isDOT, RecFormRel;
475 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
476 string asmbase, string asmstr, InstrItinClass itin,
478 let BaseName = asmbase in {
479 let Defs = [CARRY] in
480 def NAME : XForm_10<opcode, xo, OOL, IOL,
481 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
482 pattern>, RecFormRel;
483 let Defs = [CARRY, CR0] in
484 def o : XForm_10<opcode, xo, OOL, IOL,
485 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
486 []>, isDOT, RecFormRel;
490 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
491 string asmbase, string asmstr, InstrItinClass itin,
493 let BaseName = asmbase in {
494 def NAME : XForm_11<opcode, xo, OOL, IOL,
495 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
496 pattern>, RecFormRel;
498 def o : XForm_11<opcode, xo, OOL, IOL,
499 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
500 []>, isDOT, RecFormRel;
504 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
505 string asmbase, string asmstr, InstrItinClass itin,
507 let BaseName = asmbase in {
508 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
509 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
510 pattern>, RecFormRel;
512 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
513 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
514 []>, isDOT, RecFormRel;
518 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
519 string asmbase, string asmstr, InstrItinClass itin,
521 let BaseName = asmbase in {
522 let Defs = [CARRY] in
523 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
524 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
525 pattern>, RecFormRel;
526 let Defs = [CARRY, CR0] in
527 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
528 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
529 []>, isDOT, RecFormRel;
533 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
534 string asmbase, string asmstr, InstrItinClass itin,
536 let BaseName = asmbase in {
537 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
538 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
539 pattern>, RecFormRel;
541 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
542 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
543 []>, isDOT, RecFormRel;
547 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
548 string asmbase, string asmstr, InstrItinClass itin,
550 let BaseName = asmbase in {
551 let Defs = [CARRY] in
552 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
553 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
554 pattern>, RecFormRel;
555 let Defs = [CARRY, CR0] in
556 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
557 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
558 []>, isDOT, RecFormRel;
562 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
563 string asmbase, string asmstr, InstrItinClass itin,
565 let BaseName = asmbase in {
566 def NAME : MForm_2<opcode, OOL, IOL,
567 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
568 pattern>, RecFormRel;
570 def o : MForm_2<opcode, OOL, IOL,
571 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
572 []>, isDOT, RecFormRel;
576 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
577 string asmbase, string asmstr, InstrItinClass itin,
579 let BaseName = asmbase in {
580 def NAME : MDForm_1<opcode, xo, OOL, IOL,
581 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
582 pattern>, RecFormRel;
584 def o : MDForm_1<opcode, xo, OOL, IOL,
585 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
586 []>, isDOT, RecFormRel;
590 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
591 string asmbase, string asmstr, InstrItinClass itin,
593 let BaseName = asmbase in {
594 let Defs = [CARRY] in
595 def NAME : XSForm_1<opcode, xo, OOL, IOL,
596 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
597 pattern>, RecFormRel;
598 let Defs = [CARRY, CR0] in
599 def o : XSForm_1<opcode, xo, OOL, IOL,
600 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
601 []>, isDOT, RecFormRel;
605 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
606 string asmbase, string asmstr, InstrItinClass itin,
608 let BaseName = asmbase in {
609 def NAME : XForm_26<opcode, xo, OOL, IOL,
610 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
611 pattern>, RecFormRel;
613 def o : XForm_26<opcode, xo, OOL, IOL,
614 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
615 []>, isDOT, RecFormRel;
619 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
620 string asmbase, string asmstr, InstrItinClass itin,
622 let BaseName = asmbase in {
623 def NAME : AForm_1<opcode, xo, OOL, IOL,
624 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
625 pattern>, RecFormRel;
627 def o : AForm_1<opcode, xo, OOL, IOL,
628 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
629 []>, isDOT, RecFormRel;
633 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
634 string asmbase, string asmstr, InstrItinClass itin,
636 let BaseName = asmbase in {
637 def NAME : AForm_2<opcode, xo, OOL, IOL,
638 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
639 pattern>, RecFormRel;
641 def o : AForm_2<opcode, xo, OOL, IOL,
642 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
643 []>, isDOT, RecFormRel;
647 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
648 string asmbase, string asmstr, InstrItinClass itin,
650 let BaseName = asmbase in {
651 def NAME : AForm_3<opcode, xo, OOL, IOL,
652 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
653 pattern>, RecFormRel;
655 def o : AForm_3<opcode, xo, OOL, IOL,
656 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
657 []>, isDOT, RecFormRel;
661 //===----------------------------------------------------------------------===//
662 // PowerPC Instruction Definitions.
664 // Pseudo-instructions:
666 let hasCtrlDep = 1 in {
667 let Defs = [R1], Uses = [R1] in {
668 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
669 [(callseq_start timm:$amt)]>;
670 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
671 [(callseq_end timm:$amt1, timm:$amt2)]>;
674 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
675 "UPDATE_VRSAVE $rD, $rS", []>;
678 let Defs = [R1], Uses = [R1] in
679 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "#DYNALLOC",
681 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
683 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
684 // instruction selection into a branch sequence.
685 let usesCustomInserter = 1, // Expanded after instruction selection.
686 PPC970_Single = 1 in {
687 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
688 // because either operand might become the first operand in an isel, and
689 // that operand cannot be r0.
690 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond,
691 GPRC_NOR0:$T, GPRC_NOR0:$F,
692 i32imm:$BROPC), "#SELECT_CC_I4",
694 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond,
695 G8RC_NOX0:$T, G8RC_NOX0:$F,
696 i32imm:$BROPC), "#SELECT_CC_I8",
698 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
699 i32imm:$BROPC), "#SELECT_CC_F4",
701 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
702 i32imm:$BROPC), "#SELECT_CC_F8",
704 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
705 i32imm:$BROPC), "#SELECT_CC_VRRC",
709 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
710 // scavenge a register for it.
712 def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F),
715 // RESTORE_CR - Indicate that we're restoring the CR register (previously
716 // spilled), so we'll need to scavenge a register for it.
718 def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F),
721 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
722 let isReturn = 1, Uses = [LR, RM] in
723 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", BrB,
725 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
726 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
728 let isCodeGenOnly = 1 in
729 def BCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
730 "b${cond:cc}ctr ${cond:reg}", BrB, []>;
735 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
738 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
739 let isBarrier = 1 in {
740 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
745 // BCC represents an arbitrary conditional branch on a predicate.
746 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
747 // a two-value operand where a dag node expects two operands. :(
748 let isCodeGenOnly = 1 in {
749 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
750 "b${cond:cc} ${cond:reg}, $dst"
751 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
752 let isReturn = 1, Uses = [LR, RM] in
753 def BCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
754 "b${cond:cc}lr ${cond:reg}", BrB, []>;
756 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
757 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
759 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
764 let Defs = [CTR], Uses = [CTR] in {
765 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
767 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
772 // The unconditional BCL used by the SjLj setjmp code.
773 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
774 let Defs = [LR], Uses = [RM] in {
775 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
780 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
781 // Convenient aliases for call instructions
783 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
784 "bl $func", BrB, []>; // See Pat patterns below.
785 def BLA : IForm<18, 1, 1, (outs), (ins aaddr:$func),
786 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
788 let Uses = [CTR, RM] in {
789 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
790 "bctrl", BrB, [(PPCbctrl)]>,
791 Requires<[In32BitMode]>;
793 let isCodeGenOnly = 1 in
794 def BCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
795 "b${cond:cc}ctrl ${cond:reg}", BrB, []>;
799 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
800 def TCRETURNdi :Pseudo< (outs),
801 (ins calltarget:$dst, i32imm:$offset),
802 "#TC_RETURNd $dst $offset",
806 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
807 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
808 "#TC_RETURNa $func $offset",
809 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
811 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
812 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
813 "#TC_RETURNr $dst $offset",
817 let isCodeGenOnly = 1 in {
819 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
820 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
821 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
822 Requires<[In32BitMode]>;
826 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
827 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
828 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
834 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
835 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
836 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
840 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
841 def EH_SjLj_SetJmp32 : Pseudo<(outs GPRC:$dst), (ins memr:$buf),
843 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
844 Requires<[In32BitMode]>;
845 let isTerminator = 1 in
846 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
847 "#EH_SJLJ_LONGJMP32",
848 [(PPCeh_sjlj_longjmp addr:$buf)]>,
849 Requires<[In32BitMode]>;
852 let isBranch = 1, isTerminator = 1 in {
853 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
854 "#EH_SjLj_Setup\t$dst", []>;
857 // DCB* instructions.
858 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
859 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
860 PPC970_DGroup_Single;
861 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
862 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
863 PPC970_DGroup_Single;
864 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
865 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
866 PPC970_DGroup_Single;
867 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
868 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
869 PPC970_DGroup_Single;
870 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
871 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
872 PPC970_DGroup_Single;
873 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
874 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
875 PPC970_DGroup_Single;
876 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
877 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
878 PPC970_DGroup_Single;
879 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
880 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
881 PPC970_DGroup_Single;
883 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
887 let usesCustomInserter = 1 in {
888 let Defs = [CR0] in {
889 def ATOMIC_LOAD_ADD_I8 : Pseudo<
890 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I8",
891 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
892 def ATOMIC_LOAD_SUB_I8 : Pseudo<
893 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I8",
894 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
895 def ATOMIC_LOAD_AND_I8 : Pseudo<
896 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I8",
897 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
898 def ATOMIC_LOAD_OR_I8 : Pseudo<
899 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I8",
900 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
901 def ATOMIC_LOAD_XOR_I8 : Pseudo<
902 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "ATOMIC_LOAD_XOR_I8",
903 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
904 def ATOMIC_LOAD_NAND_I8 : Pseudo<
905 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I8",
906 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
907 def ATOMIC_LOAD_ADD_I16 : Pseudo<
908 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I16",
909 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
910 def ATOMIC_LOAD_SUB_I16 : Pseudo<
911 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I16",
912 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
913 def ATOMIC_LOAD_AND_I16 : Pseudo<
914 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I16",
915 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
916 def ATOMIC_LOAD_OR_I16 : Pseudo<
917 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I16",
918 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
919 def ATOMIC_LOAD_XOR_I16 : Pseudo<
920 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I16",
921 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
922 def ATOMIC_LOAD_NAND_I16 : Pseudo<
923 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I16",
924 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
925 def ATOMIC_LOAD_ADD_I32 : Pseudo<
926 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I32",
927 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
928 def ATOMIC_LOAD_SUB_I32 : Pseudo<
929 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I32",
930 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
931 def ATOMIC_LOAD_AND_I32 : Pseudo<
932 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I32",
933 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
934 def ATOMIC_LOAD_OR_I32 : Pseudo<
935 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I32",
936 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
937 def ATOMIC_LOAD_XOR_I32 : Pseudo<
938 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I32",
939 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
940 def ATOMIC_LOAD_NAND_I32 : Pseudo<
941 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I32",
942 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
944 def ATOMIC_CMP_SWAP_I8 : Pseudo<
945 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I8",
946 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
947 def ATOMIC_CMP_SWAP_I16 : Pseudo<
948 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
949 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
950 def ATOMIC_CMP_SWAP_I32 : Pseudo<
951 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
952 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
954 def ATOMIC_SWAP_I8 : Pseudo<
955 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_i8",
956 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
957 def ATOMIC_SWAP_I16 : Pseudo<
958 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I16",
959 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
960 def ATOMIC_SWAP_I32 : Pseudo<
961 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I32",
962 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
966 // Instructions to support atomic operations
967 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
968 "lwarx $rD, $src", LdStLWARX,
969 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
972 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
973 "stwcx. $rS, $dst", LdStSTWCX,
974 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
977 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
978 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
980 //===----------------------------------------------------------------------===//
981 // PPC32 Load Instructions.
984 // Unindexed (r+i) Loads.
985 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
986 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
987 "lbz $rD, $src", LdStLoad,
988 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
989 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
990 "lha $rD, $src", LdStLHA,
991 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
992 PPC970_DGroup_Cracked;
993 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
994 "lhz $rD, $src", LdStLoad,
995 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
996 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
997 "lwz $rD, $src", LdStLoad,
998 [(set i32:$rD, (load iaddr:$src))]>;
1000 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
1001 "lfs $rD, $src", LdStLFD,
1002 [(set f32:$rD, (load iaddr:$src))]>;
1003 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
1004 "lfd $rD, $src", LdStLFD,
1005 [(set f64:$rD, (load iaddr:$src))]>;
1008 // Unindexed (r+i) Loads with Update (preinc).
1009 let mayLoad = 1, neverHasSideEffects = 1 in {
1010 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1011 "lbzu $rD, $addr", LdStLoadUpd,
1012 []>, RegConstraint<"$addr.reg = $ea_result">,
1013 NoEncode<"$ea_result">;
1015 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1016 "lhau $rD, $addr", LdStLHAU,
1017 []>, RegConstraint<"$addr.reg = $ea_result">,
1018 NoEncode<"$ea_result">;
1020 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1021 "lhzu $rD, $addr", LdStLoadUpd,
1022 []>, RegConstraint<"$addr.reg = $ea_result">,
1023 NoEncode<"$ea_result">;
1025 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1026 "lwzu $rD, $addr", LdStLoadUpd,
1027 []>, RegConstraint<"$addr.reg = $ea_result">,
1028 NoEncode<"$ea_result">;
1030 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1031 "lfsu $rD, $addr", LdStLFDU,
1032 []>, RegConstraint<"$addr.reg = $ea_result">,
1033 NoEncode<"$ea_result">;
1035 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1036 "lfdu $rD, $addr", LdStLFDU,
1037 []>, RegConstraint<"$addr.reg = $ea_result">,
1038 NoEncode<"$ea_result">;
1041 // Indexed (r+r) Loads with Update (preinc).
1042 def LBZUX : XForm_1<31, 119, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
1044 "lbzux $rD, $addr", LdStLoadUpd,
1045 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1046 NoEncode<"$ea_result">;
1048 def LHAUX : XForm_1<31, 375, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
1050 "lhaux $rD, $addr", LdStLHAU,
1051 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1052 NoEncode<"$ea_result">;
1054 def LHZUX : XForm_1<31, 311, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
1056 "lhzux $rD, $addr", LdStLoadUpd,
1057 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1058 NoEncode<"$ea_result">;
1060 def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
1062 "lwzux $rD, $addr", LdStLoadUpd,
1063 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1064 NoEncode<"$ea_result">;
1066 def LFSUX : XForm_1<31, 567, (outs F4RC:$rD, ptr_rc_nor0:$ea_result),
1068 "lfsux $rD, $addr", LdStLFDU,
1069 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1070 NoEncode<"$ea_result">;
1072 def LFDUX : XForm_1<31, 631, (outs F8RC:$rD, ptr_rc_nor0:$ea_result),
1074 "lfdux $rD, $addr", LdStLFDU,
1075 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1076 NoEncode<"$ea_result">;
1080 // Indexed (r+r) Loads.
1082 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1083 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
1084 "lbzx $rD, $src", LdStLoad,
1085 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1086 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
1087 "lhax $rD, $src", LdStLHA,
1088 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1089 PPC970_DGroup_Cracked;
1090 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
1091 "lhzx $rD, $src", LdStLoad,
1092 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1093 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
1094 "lwzx $rD, $src", LdStLoad,
1095 [(set i32:$rD, (load xaddr:$src))]>;
1098 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
1099 "lhbrx $rD, $src", LdStLoad,
1100 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1101 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
1102 "lwbrx $rD, $src", LdStLoad,
1103 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1105 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
1106 "lfsx $frD, $src", LdStLFD,
1107 [(set f32:$frD, (load xaddr:$src))]>;
1108 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
1109 "lfdx $frD, $src", LdStLFD,
1110 [(set f64:$frD, (load xaddr:$src))]>;
1112 def LFIWAX : XForm_25<31, 855, (outs F8RC:$frD), (ins memrr:$src),
1113 "lfiwax $frD, $src", LdStLFD,
1114 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1115 def LFIWZX : XForm_25<31, 887, (outs F8RC:$frD), (ins memrr:$src),
1116 "lfiwzx $frD, $src", LdStLFD,
1117 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1120 //===----------------------------------------------------------------------===//
1121 // PPC32 Store Instructions.
1124 // Unindexed (r+i) Stores.
1125 let PPC970_Unit = 2 in {
1126 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
1127 "stb $rS, $src", LdStStore,
1128 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1129 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
1130 "sth $rS, $src", LdStStore,
1131 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1132 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
1133 "stw $rS, $src", LdStStore,
1134 [(store i32:$rS, iaddr:$src)]>;
1135 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
1136 "stfs $rS, $dst", LdStSTFD,
1137 [(store f32:$rS, iaddr:$dst)]>;
1138 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
1139 "stfd $rS, $dst", LdStSTFD,
1140 [(store f64:$rS, iaddr:$dst)]>;
1143 // Unindexed (r+i) Stores with Update (preinc).
1144 let PPC970_Unit = 2, mayStore = 1 in {
1145 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
1146 "stbu $rS, $dst", LdStStoreUpd, []>,
1147 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1148 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
1149 "sthu $rS, $dst", LdStStoreUpd, []>,
1150 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1151 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
1152 "stwu $rS, $dst", LdStStoreUpd, []>,
1153 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1154 def STFSU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memri:$dst),
1155 "stfsu $rS, $dst", LdStSTFDU, []>,
1156 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1157 def STFDU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memri:$dst),
1158 "stfdu $rS, $dst", LdStSTFDU, []>,
1159 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1162 // Patterns to match the pre-inc stores. We can't put the patterns on
1163 // the instruction definitions directly as ISel wants the address base
1164 // and offset to be separate operands, not a single complex operand.
1165 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1166 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1167 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1168 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1169 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1170 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1171 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1172 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1173 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1174 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1176 // Indexed (r+r) Stores.
1177 let PPC970_Unit = 2 in {
1178 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
1179 "stbx $rS, $dst", LdStStore,
1180 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1181 PPC970_DGroup_Cracked;
1182 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
1183 "sthx $rS, $dst", LdStStore,
1184 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1185 PPC970_DGroup_Cracked;
1186 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
1187 "stwx $rS, $dst", LdStStore,
1188 [(store i32:$rS, xaddr:$dst)]>,
1189 PPC970_DGroup_Cracked;
1191 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
1192 "sthbrx $rS, $dst", LdStStore,
1193 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1194 PPC970_DGroup_Cracked;
1195 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
1196 "stwbrx $rS, $dst", LdStStore,
1197 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1198 PPC970_DGroup_Cracked;
1200 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
1201 "stfiwx $frS, $dst", LdStSTFD,
1202 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1204 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
1205 "stfsx $frS, $dst", LdStSTFD,
1206 [(store f32:$frS, xaddr:$dst)]>;
1207 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
1208 "stfdx $frS, $dst", LdStSTFD,
1209 [(store f64:$frS, xaddr:$dst)]>;
1212 // Indexed (r+r) Stores with Update (preinc).
1213 let PPC970_Unit = 2, mayStore = 1 in {
1214 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
1215 "stbux $rS, $dst", LdStStoreUpd, []>,
1216 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1217 PPC970_DGroup_Cracked;
1218 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
1219 "sthux $rS, $dst", LdStStoreUpd, []>,
1220 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1221 PPC970_DGroup_Cracked;
1222 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
1223 "stwux $rS, $dst", LdStStoreUpd, []>,
1224 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1225 PPC970_DGroup_Cracked;
1226 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memrr:$dst),
1227 "stfsux $rS, $dst", LdStSTFDU, []>,
1228 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1229 PPC970_DGroup_Cracked;
1230 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memrr:$dst),
1231 "stfdux $rS, $dst", LdStSTFDU, []>,
1232 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1233 PPC970_DGroup_Cracked;
1236 // Patterns to match the pre-inc stores. We can't put the patterns on
1237 // the instruction definitions directly as ISel wants the address base
1238 // and offset to be separate operands, not a single complex operand.
1239 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1240 (STBUX $rS, $ptrreg, $ptroff)>;
1241 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1242 (STHUX $rS, $ptrreg, $ptroff)>;
1243 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1244 (STWUX $rS, $ptrreg, $ptroff)>;
1245 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1246 (STFSUX $rS, $ptrreg, $ptroff)>;
1247 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1248 (STFDUX $rS, $ptrreg, $ptroff)>;
1250 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
1254 //===----------------------------------------------------------------------===//
1255 // PPC32 Arithmetic Instructions.
1258 let PPC970_Unit = 1 in { // FXU Operations.
1259 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$imm),
1260 "addi $rD, $rA, $imm", IntSimple,
1261 [(set i32:$rD, (add i32:$rA, immSExt16:$imm))]>;
1262 let BaseName = "addic" in {
1263 let Defs = [CARRY] in
1264 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1265 "addic $rD, $rA, $imm", IntGeneral,
1266 [(set i32:$rD, (addc i32:$rA, immSExt16:$imm))]>,
1267 RecFormRel, PPC970_DGroup_Cracked;
1268 let Defs = [CARRY, CR0] in
1269 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1270 "addic. $rD, $rA, $imm", IntGeneral,
1271 []>, isDOT, RecFormRel;
1273 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolHi:$imm),
1274 "addis $rD, $rA, $imm", IntSimple,
1275 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1276 let isCodeGenOnly = 1 in
1277 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$sym),
1278 "la $rD, $sym($rA)", IntGeneral,
1279 [(set i32:$rD, (add i32:$rA,
1280 (PPClo tglobaladdr:$sym, 0)))]>;
1281 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1282 "mulli $rD, $rA, $imm", IntMulLI,
1283 [(set i32:$rD, (mul i32:$rA, immSExt16:$imm))]>;
1284 let Defs = [CARRY] in
1285 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1286 "subfic $rD, $rA, $imm", IntGeneral,
1287 [(set i32:$rD, (subc immSExt16:$imm, i32:$rA))]>;
1289 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1290 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
1291 "li $rD, $imm", IntSimple,
1292 [(set i32:$rD, immSExt16:$imm)]>;
1293 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
1294 "lis $rD, $imm", IntSimple,
1295 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1299 let PPC970_Unit = 1 in { // FXU Operations.
1300 let Defs = [CR0] in {
1301 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1302 "andi. $dst, $src1, $src2", IntGeneral,
1303 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1305 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1306 "andis. $dst, $src1, $src2", IntGeneral,
1307 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1310 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1311 "ori $dst, $src1, $src2", IntSimple,
1312 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1313 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1314 "oris $dst, $src1, $src2", IntSimple,
1315 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1316 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1317 "xori $dst, $src1, $src2", IntSimple,
1318 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1319 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1320 "xoris $dst, $src1, $src2", IntSimple,
1321 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1322 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
1324 let isCompare = 1, neverHasSideEffects = 1 in {
1325 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
1326 "cmpwi $crD, $rA, $imm", IntCompare>;
1327 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1328 "cmplwi $dst, $src1, $src2", IntCompare>;
1332 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1333 defm NAND : XForm_6r<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1334 "nand", "$rA, $rS, $rB", IntSimple,
1335 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1336 defm AND : XForm_6r<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1337 "and", "$rA, $rS, $rB", IntSimple,
1338 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1339 defm ANDC : XForm_6r<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1340 "andc", "$rA, $rS, $rB", IntSimple,
1341 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1342 defm OR : XForm_6r<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1343 "or", "$rA, $rS, $rB", IntSimple,
1344 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1345 defm NOR : XForm_6r<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1346 "nor", "$rA, $rS, $rB", IntSimple,
1347 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1348 defm ORC : XForm_6r<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1349 "orc", "$rA, $rS, $rB", IntSimple,
1350 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1351 defm EQV : XForm_6r<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1352 "eqv", "$rA, $rS, $rB", IntSimple,
1353 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1354 defm XOR : XForm_6r<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1355 "xor", "$rA, $rS, $rB", IntSimple,
1356 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1357 defm SLW : XForm_6r<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1358 "slw", "$rA, $rS, $rB", IntGeneral,
1359 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1360 defm SRW : XForm_6r<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1361 "srw", "$rA, $rS, $rB", IntGeneral,
1362 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1363 defm SRAW : XForm_6rc<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1364 "sraw", "$rA, $rS, $rB", IntShift,
1365 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1368 let PPC970_Unit = 1 in { // FXU Operations.
1369 let neverHasSideEffects = 1 in {
1370 defm SRAWI : XForm_10rc<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
1371 "srawi", "$rA, $rS, $SH", IntShift,
1372 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1373 defm CNTLZW : XForm_11r<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
1374 "cntlzw", "$rA, $rS", IntGeneral,
1375 [(set i32:$rA, (ctlz i32:$rS))]>;
1376 defm EXTSB : XForm_11r<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
1377 "extsb", "$rA, $rS", IntSimple,
1378 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1379 defm EXTSH : XForm_11r<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
1380 "extsh", "$rA, $rS", IntSimple,
1381 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1383 let isCompare = 1, neverHasSideEffects = 1 in {
1384 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1385 "cmpw $crD, $rA, $rB", IntCompare>;
1386 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1387 "cmplw $crD, $rA, $rB", IntCompare>;
1390 let PPC970_Unit = 3 in { // FPU Operations.
1391 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1392 // "fcmpo $crD, $fA, $fB", FPCompare>;
1393 let isCompare = 1, neverHasSideEffects = 1 in {
1394 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
1395 "fcmpu $crD, $fA, $fB", FPCompare>;
1396 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
1397 "fcmpu $crD, $fA, $fB", FPCompare>;
1400 let Uses = [RM] in {
1401 let neverHasSideEffects = 1 in {
1402 defm FCTIWZ : XForm_26r<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
1403 "fctiwz", "$frD, $frB", FPGeneral,
1404 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1406 defm FRSP : XForm_26r<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
1407 "frsp", "$frD, $frB", FPGeneral,
1408 [(set f32:$frD, (fround f64:$frB))]>;
1410 // The frin -> nearbyint mapping is valid only in fast-math mode.
1411 let Interpretation64Bit = 1 in
1412 defm FRIND : XForm_26r<63, 392, (outs F8RC:$frD), (ins F8RC:$frB),
1413 "frin", "$frD, $frB", FPGeneral,
1414 [(set f64:$frD, (fnearbyint f64:$frB))]>;
1415 defm FRINS : XForm_26r<63, 392, (outs F4RC:$frD), (ins F4RC:$frB),
1416 "frin", "$frD, $frB", FPGeneral,
1417 [(set f32:$frD, (fnearbyint f32:$frB))]>;
1420 // These pseudos expand to rint but also set FE_INEXACT when the result does
1421 // not equal the argument.
1422 let usesCustomInserter = 1, Defs = [RM] in { // FIXME: Model FPSCR!
1423 def FRINDrint : Pseudo<(outs F8RC:$frD), (ins F8RC:$frB),
1424 "#FRINDrint", [(set f64:$frD, (frint f64:$frB))]>;
1425 def FRINSrint : Pseudo<(outs F4RC:$frD), (ins F4RC:$frB),
1426 "#FRINSrint", [(set f32:$frD, (frint f32:$frB))]>;
1429 let neverHasSideEffects = 1 in {
1430 let Interpretation64Bit = 1 in
1431 defm FRIPD : XForm_26r<63, 456, (outs F8RC:$frD), (ins F8RC:$frB),
1432 "frip", "$frD, $frB", FPGeneral,
1433 [(set f64:$frD, (fceil f64:$frB))]>;
1434 defm FRIPS : XForm_26r<63, 456, (outs F4RC:$frD), (ins F4RC:$frB),
1435 "frip", "$frD, $frB", FPGeneral,
1436 [(set f32:$frD, (fceil f32:$frB))]>;
1437 let Interpretation64Bit = 1 in
1438 defm FRIZD : XForm_26r<63, 424, (outs F8RC:$frD), (ins F8RC:$frB),
1439 "friz", "$frD, $frB", FPGeneral,
1440 [(set f64:$frD, (ftrunc f64:$frB))]>;
1441 defm FRIZS : XForm_26r<63, 424, (outs F4RC:$frD), (ins F4RC:$frB),
1442 "friz", "$frD, $frB", FPGeneral,
1443 [(set f32:$frD, (ftrunc f32:$frB))]>;
1444 let Interpretation64Bit = 1 in
1445 defm FRIMD : XForm_26r<63, 488, (outs F8RC:$frD), (ins F8RC:$frB),
1446 "frim", "$frD, $frB", FPGeneral,
1447 [(set f64:$frD, (ffloor f64:$frB))]>;
1448 defm FRIMS : XForm_26r<63, 488, (outs F4RC:$frD), (ins F4RC:$frB),
1449 "frim", "$frD, $frB", FPGeneral,
1450 [(set f32:$frD, (ffloor f32:$frB))]>;
1452 defm FSQRT : XForm_26r<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
1453 "fsqrt", "$frD, $frB", FPSqrt,
1454 [(set f64:$frD, (fsqrt f64:$frB))]>;
1455 defm FSQRTS : XForm_26r<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
1456 "fsqrts", "$frD, $frB", FPSqrt,
1457 [(set f32:$frD, (fsqrt f32:$frB))]>;
1462 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1463 /// often coalesced away and we don't want the dispatch group builder to think
1464 /// that they will fill slots (which could cause the load of a LSU reject to
1465 /// sneak into a d-group with a store).
1466 let neverHasSideEffects = 1 in
1467 defm FMR : XForm_26r<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1468 "fmr", "$frD, $frB", FPGeneral,
1469 []>, // (set f32:$frD, f32:$frB)
1472 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1473 // These are artificially split into two different forms, for 4/8 byte FP.
1474 defm FABSS : XForm_26r<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1475 "fabs", "$frD, $frB", FPGeneral,
1476 [(set f32:$frD, (fabs f32:$frB))]>;
1477 let Interpretation64Bit = 1 in
1478 defm FABSD : XForm_26r<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1479 "fabs", "$frD, $frB", FPGeneral,
1480 [(set f64:$frD, (fabs f64:$frB))]>;
1481 defm FNABSS : XForm_26r<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1482 "fnabs", "$frD, $frB", FPGeneral,
1483 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1484 let Interpretation64Bit = 1 in
1485 defm FNABSD : XForm_26r<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1486 "fnabs", "$frD, $frB", FPGeneral,
1487 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1488 defm FNEGS : XForm_26r<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1489 "fneg", "$frD, $frB", FPGeneral,
1490 [(set f32:$frD, (fneg f32:$frB))]>;
1491 let Interpretation64Bit = 1 in
1492 defm FNEGD : XForm_26r<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1493 "fneg", "$frD, $frB", FPGeneral,
1494 [(set f64:$frD, (fneg f64:$frB))]>;
1496 // Reciprocal estimates.
1497 defm FRE : XForm_26r<63, 24, (outs F8RC:$frD), (ins F8RC:$frB),
1498 "fre", "$frD, $frB", FPGeneral,
1499 [(set f64:$frD, (PPCfre f64:$frB))]>;
1500 defm FRES : XForm_26r<59, 24, (outs F4RC:$frD), (ins F4RC:$frB),
1501 "fres", "$frD, $frB", FPGeneral,
1502 [(set f32:$frD, (PPCfre f32:$frB))]>;
1503 defm FRSQRTE : XForm_26r<63, 26, (outs F8RC:$frD), (ins F8RC:$frB),
1504 "frsqrte", "$frD, $frB", FPGeneral,
1505 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1506 defm FRSQRTES : XForm_26r<59, 26, (outs F4RC:$frD), (ins F4RC:$frB),
1507 "frsqrtes", "$frD, $frB", FPGeneral,
1508 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1511 // XL-Form instructions. condition register logical ops.
1513 let neverHasSideEffects = 1 in
1514 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1515 "mcrf $BF, $BFA", BrMCR>,
1516 PPC970_DGroup_First, PPC970_Unit_CRU;
1518 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1519 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1520 "creqv $CRD, $CRA, $CRB", BrCR,
1523 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1524 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1525 "cror $CRD, $CRA, $CRB", BrCR,
1528 let isCodeGenOnly = 1 in {
1529 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1530 "creqv $dst, $dst, $dst", BrCR,
1533 def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins),
1534 "crxor $dst, $dst, $dst", BrCR,
1537 let Defs = [CR1EQ], CRD = 6 in {
1538 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1539 "creqv 6, 6, 6", BrCR,
1542 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1543 "crxor 6, 6, 6", BrCR,
1548 // XFX-Form instructions. Instructions that deal with SPRs.
1550 let Uses = [CTR] in {
1551 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1552 "mfctr $rT", SprMFSPR>,
1553 PPC970_DGroup_First, PPC970_Unit_FXU;
1555 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
1556 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1557 "mtctr $rS", SprMTSPR>,
1558 PPC970_DGroup_First, PPC970_Unit_FXU;
1561 let Defs = [LR] in {
1562 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1563 "mtlr $rS", SprMTSPR>,
1564 PPC970_DGroup_First, PPC970_Unit_FXU;
1566 let Uses = [LR] in {
1567 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1568 "mflr $rT", SprMFSPR>,
1569 PPC970_DGroup_First, PPC970_Unit_FXU;
1572 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1573 // a GPR on the PPC970. As such, copies in and out have the same performance
1574 // characteristics as an OR instruction.
1575 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1576 "mtspr 256, $rS", IntGeneral>,
1577 PPC970_DGroup_Single, PPC970_Unit_FXU;
1578 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1579 "mfspr $rT, 256", IntGeneral>,
1580 PPC970_DGroup_First, PPC970_Unit_FXU;
1582 let isCodeGenOnly = 1 in {
1583 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
1584 (outs VRSAVERC:$reg), (ins GPRC:$rS),
1585 "mtspr 256, $rS", IntGeneral>,
1586 PPC970_DGroup_Single, PPC970_Unit_FXU;
1587 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT),
1588 (ins VRSAVERC:$reg),
1589 "mfspr $rT, 256", IntGeneral>,
1590 PPC970_DGroup_First, PPC970_Unit_FXU;
1593 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
1594 // so we'll need to scavenge a register for it.
1596 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
1597 "#SPILL_VRSAVE", []>;
1599 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
1600 // spilled), so we'll need to scavenge a register for it.
1602 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
1603 "#RESTORE_VRSAVE", []>;
1605 let neverHasSideEffects = 1 in {
1606 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS),
1607 "mtcrf $FXM, $rS", BrMCRX>,
1608 PPC970_MicroCode, PPC970_Unit_CRU;
1610 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1611 // declaring that here gives the local register allocator problems with this:
1613 // MFCR <kill of whatever preg got assigned to vreg>
1614 // while not declaring it breaks DeadMachineInstructionElimination.
1615 // As it turns out, in all cases where we currently use this,
1616 // we're only interested in one subregister of it. Represent this in the
1617 // instruction to keep the register allocator from becoming confused.
1619 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1620 let isCodeGenOnly = 1 in
1621 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1622 "#MFCRpseud", SprMFCR>,
1623 PPC970_MicroCode, PPC970_Unit_CRU;
1625 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1626 "mfocrf $rT, $FXM", SprMFCR>,
1627 PPC970_DGroup_First, PPC970_Unit_CRU;
1628 } // neverHasSideEffects = 1
1630 let neverHasSideEffects = 1 in
1631 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
1632 "mfcr $rT", SprMFCR>,
1633 PPC970_MicroCode, PPC970_Unit_CRU;
1635 // Pseudo instruction to perform FADD in round-to-zero mode.
1636 let usesCustomInserter = 1, Uses = [RM] in {
1637 def FADDrtz: Pseudo<(outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), "",
1638 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
1641 // The above pseudo gets expanded to make use of the following instructions
1642 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
1643 let Uses = [RM], Defs = [RM] in {
1644 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1645 "mtfsb0 $FM", IntMTFSB0, []>,
1646 PPC970_DGroup_Single, PPC970_Unit_FPU;
1647 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1648 "mtfsb1 $FM", IntMTFSB0, []>,
1649 PPC970_DGroup_Single, PPC970_Unit_FPU;
1650 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, F8RC:$rT),
1651 "mtfsf $FM, $rT", IntMTFSB0, []>,
1652 PPC970_DGroup_Single, PPC970_Unit_FPU;
1654 let Uses = [RM] in {
1655 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1656 "mffs $rT", IntMFFS,
1657 [(set f64:$rT, (PPCmffs))]>,
1658 PPC970_DGroup_Single, PPC970_Unit_FPU;
1662 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1663 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1665 defm ADD4 : XOForm_1r<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1666 "add", "$rT, $rA, $rB", IntSimple,
1667 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
1668 defm ADDC : XOForm_1rc<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1669 "addc", "$rT, $rA, $rB", IntGeneral,
1670 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
1671 PPC970_DGroup_Cracked;
1672 defm DIVW : XOForm_1r<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1673 "divw", "$rT, $rA, $rB", IntDivW,
1674 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
1675 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1676 defm DIVWU : XOForm_1r<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1677 "divwu", "$rT, $rA, $rB", IntDivW,
1678 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
1679 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1680 defm MULHW : XOForm_1r<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1681 "mulhw", "$rT, $rA, $rB", IntMulHW,
1682 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
1683 defm MULHWU : XOForm_1r<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1684 "mulhwu", "$rT, $rA, $rB", IntMulHWU,
1685 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
1686 defm MULLW : XOForm_1r<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1687 "mullw", "$rT, $rA, $rB", IntMulHW,
1688 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
1689 defm SUBF : XOForm_1r<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1690 "subf", "$rT, $rA, $rB", IntGeneral,
1691 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
1692 defm SUBFC : XOForm_1rc<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1693 "subfc", "$rT, $rA, $rB", IntGeneral,
1694 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
1695 PPC970_DGroup_Cracked;
1696 defm NEG : XOForm_3r<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1697 "neg", "$rT, $rA", IntSimple,
1698 [(set i32:$rT, (ineg i32:$rA))]>;
1699 let Uses = [CARRY] in {
1700 defm ADDE : XOForm_1rc<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1701 "adde", "$rT, $rA, $rB", IntGeneral,
1702 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
1703 defm ADDME : XOForm_3rc<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1704 "addme", "$rT, $rA", IntGeneral,
1705 [(set i32:$rT, (adde i32:$rA, -1))]>;
1706 defm ADDZE : XOForm_3rc<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1707 "addze", "$rT, $rA", IntGeneral,
1708 [(set i32:$rT, (adde i32:$rA, 0))]>;
1709 defm SUBFE : XOForm_1rc<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1710 "subfe", "$rT, $rA, $rB", IntGeneral,
1711 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
1712 defm SUBFME : XOForm_3rc<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1713 "subfme", "$rT, $rA", IntGeneral,
1714 [(set i32:$rT, (sube -1, i32:$rA))]>;
1715 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1716 "subfze", "$rT, $rA", IntGeneral,
1717 [(set i32:$rT, (sube 0, i32:$rA))]>;
1721 // A-Form instructions. Most of the instructions executed in the FPU are of
1724 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1725 let Uses = [RM] in {
1726 defm FMADD : AForm_1r<63, 29,
1727 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1728 "fmadd", "$FRT, $FRA, $FRC, $FRB", FPFused,
1729 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
1730 defm FMADDS : AForm_1r<59, 29,
1731 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1732 "fmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1733 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
1734 defm FMSUB : AForm_1r<63, 28,
1735 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1736 "fmsub", "$FRT, $FRA, $FRC, $FRB", FPFused,
1738 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
1739 defm FMSUBS : AForm_1r<59, 28,
1740 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1741 "fmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1743 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
1744 defm FNMADD : AForm_1r<63, 31,
1745 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1746 "fnmadd", "$FRT, $FRA, $FRC, $FRB", FPFused,
1748 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
1749 defm FNMADDS : AForm_1r<59, 31,
1750 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1751 "fnmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1753 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
1754 defm FNMSUB : AForm_1r<63, 30,
1755 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1756 "fnmsub", "$FRT, $FRA, $FRC, $FRB", FPFused,
1757 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
1758 (fneg f64:$FRB))))]>;
1759 defm FNMSUBS : AForm_1r<59, 30,
1760 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1761 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1762 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
1763 (fneg f32:$FRB))))]>;
1765 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1766 // having 4 of these, force the comparison to always be an 8-byte double (code
1767 // should use an FMRSD if the input comparison value really wants to be a float)
1768 // and 4/8 byte forms for the result and operand type..
1769 let Interpretation64Bit = 1 in
1770 defm FSELD : AForm_1r<63, 23,
1771 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1772 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1773 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
1774 defm FSELS : AForm_1r<63, 23,
1775 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1776 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1777 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
1778 let Uses = [RM] in {
1779 defm FADD : AForm_2r<63, 21,
1780 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1781 "fadd", "$FRT, $FRA, $FRB", FPAddSub,
1782 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
1783 defm FADDS : AForm_2r<59, 21,
1784 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1785 "fadds", "$FRT, $FRA, $FRB", FPGeneral,
1786 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
1787 defm FDIV : AForm_2r<63, 18,
1788 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1789 "fdiv", "$FRT, $FRA, $FRB", FPDivD,
1790 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
1791 defm FDIVS : AForm_2r<59, 18,
1792 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1793 "fdivs", "$FRT, $FRA, $FRB", FPDivS,
1794 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
1795 defm FMUL : AForm_3r<63, 25,
1796 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC),
1797 "fmul", "$FRT, $FRA, $FRC", FPFused,
1798 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
1799 defm FMULS : AForm_3r<59, 25,
1800 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC),
1801 "fmuls", "$FRT, $FRA, $FRC", FPGeneral,
1802 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
1803 defm FSUB : AForm_2r<63, 20,
1804 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1805 "fsub", "$FRT, $FRA, $FRB", FPAddSub,
1806 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
1807 defm FSUBS : AForm_2r<59, 20,
1808 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1809 "fsubs", "$FRT, $FRA, $FRB", FPGeneral,
1810 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
1814 let neverHasSideEffects = 1 in {
1815 let PPC970_Unit = 1 in { // FXU Operations.
1817 def ISEL : AForm_4<31, 15,
1818 (outs GPRC:$rT), (ins GPRC_NOR0:$rA, GPRC:$rB, CRBITRC:$cond),
1819 "isel $rT, $rA, $rB, $cond", IntGeneral,
1823 let PPC970_Unit = 1 in { // FXU Operations.
1824 // M-Form instructions. rotate and mask instructions.
1826 let isCommutable = 1 in {
1827 // RLWIMI can be commuted if the rotate amount is zero.
1828 defm RLWIMI : MForm_2r<20, (outs GPRC:$rA),
1829 (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1830 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", IntRotate,
1831 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1834 let BaseName = "rlwinm" in {
1835 def RLWINM : MForm_2<21,
1836 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1837 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1840 def RLWINMo : MForm_2<21,
1841 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1842 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1843 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
1845 defm RLWNM : MForm_2r<23, (outs GPRC:$rA),
1846 (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1847 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IntGeneral,
1850 } // neverHasSideEffects = 1
1852 //===----------------------------------------------------------------------===//
1853 // PowerPC Instruction Patterns
1856 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1857 def : Pat<(i32 imm:$imm),
1858 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1860 // Implement the 'not' operation with the NOR instruction.
1861 def NOT : Pat<(not i32:$in),
1864 // ADD an arbitrary immediate.
1865 def : Pat<(add i32:$in, imm:$imm),
1866 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1867 // OR an arbitrary immediate.
1868 def : Pat<(or i32:$in, imm:$imm),
1869 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1870 // XOR an arbitrary immediate.
1871 def : Pat<(xor i32:$in, imm:$imm),
1872 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1874 def : Pat<(sub immSExt16:$imm, i32:$in),
1875 (SUBFIC $in, imm:$imm)>;
1878 def : Pat<(shl i32:$in, (i32 imm:$imm)),
1879 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
1880 def : Pat<(srl i32:$in, (i32 imm:$imm)),
1881 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
1884 def : Pat<(rotl i32:$in, i32:$sh),
1885 (RLWNM $in, $sh, 0, 31)>;
1886 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
1887 (RLWINM $in, imm:$imm, 0, 31)>;
1890 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
1891 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1894 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
1895 (BL tglobaladdr:$dst)>;
1896 def : Pat<(PPCcall (i32 texternalsym:$dst)),
1897 (BL texternalsym:$dst)>;
1900 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1901 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1903 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1904 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1906 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1907 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1911 // Hi and Lo for Darwin Global Addresses.
1912 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1913 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1914 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1915 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1916 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1917 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1918 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
1919 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
1920 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
1921 (ADDIS $in, tglobaltlsaddr:$g)>;
1922 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
1923 (ADDI $in, tglobaltlsaddr:$g)>;
1924 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
1925 (ADDIS $in, tglobaladdr:$g)>;
1926 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
1927 (ADDIS $in, tconstpool:$g)>;
1928 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
1929 (ADDIS $in, tjumptable:$g)>;
1930 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
1931 (ADDIS $in, tblockaddress:$g)>;
1933 // Standard shifts. These are represented separately from the real shifts above
1934 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1936 def : Pat<(sra i32:$rS, i32:$rB),
1938 def : Pat<(srl i32:$rS, i32:$rB),
1940 def : Pat<(shl i32:$rS, i32:$rB),
1943 def : Pat<(zextloadi1 iaddr:$src),
1945 def : Pat<(zextloadi1 xaddr:$src),
1947 def : Pat<(extloadi1 iaddr:$src),
1949 def : Pat<(extloadi1 xaddr:$src),
1951 def : Pat<(extloadi8 iaddr:$src),
1953 def : Pat<(extloadi8 xaddr:$src),
1955 def : Pat<(extloadi16 iaddr:$src),
1957 def : Pat<(extloadi16 xaddr:$src),
1959 def : Pat<(f64 (extloadf32 iaddr:$src)),
1960 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1961 def : Pat<(f64 (extloadf32 xaddr:$src)),
1962 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1964 def : Pat<(f64 (fextend f32:$src)),
1965 (COPY_TO_REGCLASS $src, F8RC)>;
1967 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
1969 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
1970 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
1971 (FNMSUB $A, $C, $B)>;
1972 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
1973 (FNMSUB $A, $C, $B)>;
1974 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
1975 (FNMSUBS $A, $C, $B)>;
1976 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
1977 (FNMSUBS $A, $C, $B)>;
1979 include "PPCInstrAltivec.td"
1980 include "PPCInstr64Bit.td"