1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
26 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
27 def SDT_PPCRetFlag : SDTypeProfile<0, 0, []>;
29 //===----------------------------------------------------------------------===//
30 // PowerPC specific DAG Nodes.
33 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
34 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
35 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
36 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
38 def PPCfsel : SDNode<"PPCISD::FSEL",
39 // Type constraint for fsel.
40 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
41 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
43 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
44 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
45 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
46 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
48 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
49 // amounts. These nodes are generated by the multi-precision shift code.
50 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
51 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
52 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
54 // These are target-independent nodes, but have target-specific formats.
55 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>;
56 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>;
58 def retflag : SDNode<"PPCISD::RET_FLAG", SDT_PPCRetFlag,
59 [SDNPHasChain, SDNPOptInFlag]>;
61 //===----------------------------------------------------------------------===//
62 // PowerPC specific transformation functions and pattern fragments.
65 def SHL32 : SDNodeXForm<imm, [{
66 // Transformation function: 31 - imm
67 return getI32Imm(31 - N->getValue());
70 def SHL64 : SDNodeXForm<imm, [{
71 // Transformation function: 63 - imm
72 return getI32Imm(63 - N->getValue());
75 def SRL32 : SDNodeXForm<imm, [{
76 // Transformation function: 32 - imm
77 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
80 def SRL64 : SDNodeXForm<imm, [{
81 // Transformation function: 64 - imm
82 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
85 def LO16 : SDNodeXForm<imm, [{
86 // Transformation function: get the low 16 bits.
87 return getI32Imm((unsigned short)N->getValue());
90 def HI16 : SDNodeXForm<imm, [{
91 // Transformation function: shift the immediate value down into the low bits.
92 return getI32Imm((unsigned)N->getValue() >> 16);
95 def HA16 : SDNodeXForm<imm, [{
96 // Transformation function: shift the immediate value down into the low bits.
97 signed int Val = N->getValue();
98 return getI32Imm((Val - (signed short)Val) >> 16);
102 def immSExt16 : PatLeaf<(imm), [{
103 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
104 // field. Used by instructions like 'addi'.
105 return (int)N->getValue() == (short)N->getValue();
107 def immZExt16 : PatLeaf<(imm), [{
108 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
109 // field. Used by instructions like 'ori'.
110 return (unsigned)N->getValue() == (unsigned short)N->getValue();
113 def imm16Shifted : PatLeaf<(imm), [{
114 // imm16Shifted predicate - True if only bits in the top 16-bits of the
115 // immediate are set. Used by instructions like 'addis'.
116 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
120 // Example of a legalize expander: Only for PPC64.
121 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
122 [(set f64:$tmp , (FCTIDZ f64:$src)),
123 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
124 (store f64:$tmp, i32:$tmpFI),
125 (set i64:$dst, (load i32:$tmpFI))],
129 //===----------------------------------------------------------------------===//
130 // PowerPC Flag Definitions.
132 class isPPC64 { bit PPC64 = 1; }
133 class isVMX { bit VMX = 1; }
135 list<Register> Defs = [CR0];
141 //===----------------------------------------------------------------------===//
142 // PowerPC Operand Definitions.
144 def u5imm : Operand<i32> {
145 let PrintMethod = "printU5ImmOperand";
147 def u6imm : Operand<i32> {
148 let PrintMethod = "printU6ImmOperand";
150 def s16imm : Operand<i32> {
151 let PrintMethod = "printS16ImmOperand";
153 def u16imm : Operand<i32> {
154 let PrintMethod = "printU16ImmOperand";
156 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
157 let PrintMethod = "printS16X4ImmOperand";
159 def target : Operand<OtherVT> {
160 let PrintMethod = "printBranchOperand";
162 def calltarget : Operand<i32> {
163 let PrintMethod = "printCallOperand";
165 def aaddr : Operand<i32> {
166 let PrintMethod = "printAbsAddrOperand";
168 def piclabel: Operand<i32> {
169 let PrintMethod = "printPICLabel";
171 def symbolHi: Operand<i32> {
172 let PrintMethod = "printSymbolHi";
174 def symbolLo: Operand<i32> {
175 let PrintMethod = "printSymbolLo";
177 def crbitm: Operand<i8> {
178 let PrintMethod = "printcrbitm";
181 def memri : Operand<i32> {
182 let PrintMethod = "printMemRegImm";
183 let NumMIOperands = 2;
184 let MIOperandInfo = (ops i32imm, GPRC);
186 def memrr : Operand<i32> {
187 let PrintMethod = "printMemRegReg";
188 let NumMIOperands = 2;
189 let MIOperandInfo = (ops GPRC, GPRC);
192 // Define PowerPC specific addressing mode.
193 def iaddr : ComplexPattern<i32, 2, "SelectAddrImm", []>;
194 def xaddr : ComplexPattern<i32, 2, "SelectAddrIdx", []>;
195 def xoaddr : ComplexPattern<i32, 2, "SelectAddrIdxOnly",[]>;
197 //===----------------------------------------------------------------------===//
198 // PowerPC Instruction Predicate Definitions.
199 def FPContractions : Predicate<"!NoExcessFPPrecision">;
201 //===----------------------------------------------------------------------===//
202 // PowerPC Instruction Definitions.
204 // Pseudo-instructions:
206 let hasCtrlDep = 1 in {
207 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
208 "; ADJCALLSTACKDOWN",
209 [(callseq_start imm:$amt)]>;
210 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
212 [(callseq_end imm:$amt)]>;
214 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
215 [(set GPRC:$rD, (undef))]>;
216 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8",
217 [(set F8RC:$rD, (undef))]>;
218 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4",
219 [(set F4RC:$rD, (undef))]>;
221 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
222 // scheduler into a branch sequence.
223 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
224 PPC970_Single = 1 in {
225 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
226 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
227 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
228 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
229 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
230 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
233 let isTerminator = 1, noResults = 1, PPC970_Unit = 7 in {
235 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>;
236 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
240 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
243 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
244 noResults = 1, PPC970_Unit = 7 in {
245 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
246 target:$true, target:$false),
247 "; COND_BRANCH", []>;
248 def B : IForm<18, 0, 0, (ops target:$dst),
252 // FIXME: 4*CR# needs to be added to the BI field!
253 // This will only work for CR0 as it stands now
254 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
255 "blt $crS, $block", BrB>;
256 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
257 "ble $crS, $block", BrB>;
258 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
259 "beq $crS, $block", BrB>;
260 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
261 "bge $crS, $block", BrB>;
262 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
263 "bgt $crS, $block", BrB>;
264 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
265 "bne $crS, $block", BrB>;
266 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
267 "bun $crS, $block", BrB>;
268 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
269 "bnu $crS, $block", BrB>;
272 let isCall = 1, noResults = 1, PPC970_Unit = 7,
273 // All calls clobber the non-callee saved registers...
274 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
275 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
277 CR0,CR1,CR5,CR6,CR7] in {
278 // Convenient aliases for call instructions
279 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
280 "bl $func", BrB, []>;
281 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
282 "bla $func", BrB, []>;
283 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB,
287 // D-Form instructions. Most instructions that perform an operation on a
288 // register and an immediate are of this type.
290 let isLoad = 1, PPC970_Unit = 2 in {
291 def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
292 "lbz $rD, $src", LdStGeneral,
293 [(set GPRC:$rD, (zextload iaddr:$src, i8))]>;
294 def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
295 "lha $rD, $src", LdStLHA,
296 [(set GPRC:$rD, (sextload iaddr:$src, i16))]>;
297 def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
298 "lhz $rD, $src", LdStGeneral,
299 [(set GPRC:$rD, (zextload iaddr:$src, i16))]>;
300 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
301 "lmw $rD, $disp($rA)", LdStLMW,
303 def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
304 "lwz $rD, $src", LdStGeneral,
305 [(set GPRC:$rD, (load iaddr:$src))]>;
306 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
307 "lwzu $rD, $disp($rA)", LdStGeneral,
310 let PPC970_Unit = 1 in { // FXU Operations.
311 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
312 "addi $rD, $rA, $imm", IntGeneral,
313 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
314 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
315 "addic $rD, $rA, $imm", IntGeneral,
316 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>;
317 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
318 "addic. $rD, $rA, $imm", IntGeneral,
320 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
321 "addis $rD, $rA, $imm", IntGeneral,
322 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
323 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
324 "la $rD, $sym($rA)", IntGeneral,
325 [(set GPRC:$rD, (add GPRC:$rA,
326 (PPClo tglobaladdr:$sym, 0)))]>;
327 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
328 "mulli $rD, $rA, $imm", IntMulLI,
329 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
330 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
331 "subfic $rD, $rA, $imm", IntGeneral,
332 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
333 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
334 "li $rD, $imm", IntGeneral,
335 [(set GPRC:$rD, immSExt16:$imm)]>;
336 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
337 "lis $rD, $imm", IntGeneral,
338 [(set GPRC:$rD, imm16Shifted:$imm)]>;
340 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
341 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
342 "stmw $rS, $disp($rA)", LdStLMW,
344 def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
345 "stb $rS, $src", LdStGeneral,
346 [(truncstore GPRC:$rS, iaddr:$src, i8)]>;
347 def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
348 "sth $rS, $src", LdStGeneral,
349 [(truncstore GPRC:$rS, iaddr:$src, i16)]>;
350 def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
351 "stw $rS, $src", LdStGeneral,
352 [(store GPRC:$rS, iaddr:$src)]>;
353 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
354 "stwu $rS, $disp($rA)", LdStGeneral,
357 let PPC970_Unit = 1 in { // FXU Operations.
358 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
359 "andi. $dst, $src1, $src2", IntGeneral,
360 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
362 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
363 "andis. $dst, $src1, $src2", IntGeneral,
364 [(set GPRC:$dst, (and GPRC:$src1, imm16Shifted:$src2))]>,
366 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
367 "ori $dst, $src1, $src2", IntGeneral,
368 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
369 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
370 "oris $dst, $src1, $src2", IntGeneral,
371 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
372 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
373 "xori $dst, $src1, $src2", IntGeneral,
374 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
375 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
376 "xoris $dst, $src1, $src2", IntGeneral,
377 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
378 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
380 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
381 "cmpi $crD, $L, $rA, $imm", IntCompare>;
382 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
383 "cmpwi $crD, $rA, $imm", IntCompare>;
384 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
385 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
386 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
387 "cmpli $dst, $size, $src1, $src2", IntCompare>;
388 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
389 "cmplwi $dst, $src1, $src2", IntCompare>;
390 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
391 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
393 let isLoad = 1, PPC970_Unit = 2 in {
394 def LFS : DForm_8<48, (ops F4RC:$rD, memri:$src),
395 "lfs $rD, $src", LdStLFDU,
396 [(set F4RC:$rD, (load iaddr:$src))]>;
397 def LFD : DForm_8<50, (ops F8RC:$rD, memri:$src),
398 "lfd $rD, $src", LdStLFD,
399 [(set F8RC:$rD, (load iaddr:$src))]>;
401 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
402 def STFS : DForm_9<52, (ops F4RC:$rS, memri:$dst),
403 "stfs $rS, $dst", LdStUX,
404 [(store F4RC:$rS, iaddr:$dst)]>;
405 def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst),
406 "stfd $rS, $dst", LdStUX,
407 [(store F8RC:$rS, iaddr:$dst)]>;
410 // DS-Form instructions. Load/Store instructions available in PPC-64
412 let isLoad = 1, PPC970_Unit = 2 in {
413 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
414 "lwa $rT, $DS($rA)", LdStLWA,
416 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
417 "ld $rT, $DS($rA)", LdStLD,
420 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
421 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
422 "std $rT, $DS($rA)", LdStSTD,
424 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
425 "stdu $rT, $DS($rA)", LdStSTD,
429 // X-Form instructions. Most instructions that perform an operation on a
430 // register and another register are of this type.
432 let isLoad = 1, PPC970_Unit = 2 in {
433 def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
434 "lbzx $rD, $src", LdStGeneral,
435 [(set GPRC:$rD, (zextload xaddr:$src, i8))]>;
436 def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
437 "lhax $rD, $src", LdStLHA,
438 [(set GPRC:$rD, (sextload xaddr:$src, i16))]>;
439 def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
440 "lhzx $rD, $src", LdStGeneral,
441 [(set GPRC:$rD, (zextload xaddr:$src, i16))]>;
442 def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
443 "lwax $rD, $src", LdStLHA,
444 [(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64;
445 def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
446 "lwzx $rD, $src", LdStGeneral,
447 [(set GPRC:$rD, (load xaddr:$src))]>;
448 def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
449 "ldx $rD, $src", LdStLD,
450 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
451 def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
452 "lvebx $vD, $base, $rA", LdStGeneral,
454 def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
455 "lvehx $vD, $base, $rA", LdStGeneral,
457 def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
458 "lvewx $vD, $base, $rA", LdStGeneral,
460 def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
461 "lvx $vD, $src", LdStGeneral,
462 [(set VRRC:$vD, (v4f32 (load xoaddr:$src)))]>;
464 def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
465 "lvsl $vD, $base, $rA", LdStGeneral,
466 []>, PPC970_Unit_LSU;
467 def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
468 "lvsl $vD, $base, $rA", LdStGeneral,
469 []>, PPC970_Unit_LSU;
470 let PPC970_Unit = 1 in { // FXU Operations.
471 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
472 "nand $rA, $rS, $rB", IntGeneral,
473 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
474 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
475 "and $rA, $rS, $rB", IntGeneral,
476 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
477 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
478 "and. $rA, $rS, $rB", IntGeneral,
480 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
481 "andc $rA, $rS, $rB", IntGeneral,
482 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
483 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
484 "or $rA, $rS, $rB", IntGeneral,
485 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
486 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
487 "or $rA, $rS, $rB", IntGeneral,
488 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
489 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
490 "or $rA, $rS, $rB", IntGeneral,
492 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
493 "or $rA, $rS, $rB", IntGeneral,
495 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
496 "nor $rA, $rS, $rB", IntGeneral,
497 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
498 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
499 "or. $rA, $rS, $rB", IntGeneral,
501 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
502 "orc $rA, $rS, $rB", IntGeneral,
503 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
504 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
505 "eqv $rA, $rS, $rB", IntGeneral,
506 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
507 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
508 "xor $rA, $rS, $rB", IntGeneral,
509 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
510 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
511 "sld $rA, $rS, $rB", IntRotateD,
512 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
513 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
514 "slw $rA, $rS, $rB", IntGeneral,
515 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
516 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
517 "srd $rA, $rS, $rB", IntRotateD,
518 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
519 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
520 "srw $rA, $rS, $rB", IntGeneral,
521 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
522 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
523 "srad $rA, $rS, $rB", IntRotateD,
524 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
525 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
526 "sraw $rA, $rS, $rB", IntShift,
527 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
529 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
530 def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
531 "stbx $rS, $dst", LdStGeneral,
532 [(truncstore GPRC:$rS, xaddr:$dst, i8)]>;
533 def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
534 "sthx $rS, $dst", LdStGeneral,
535 [(truncstore GPRC:$rS, xaddr:$dst, i16)]>;
536 def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
537 "stwx $rS, $dst", LdStGeneral,
538 [(store GPRC:$rS, xaddr:$dst)]>;
539 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
540 "stwux $rS, $rA, $rB", LdStGeneral,
542 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
543 "stdx $rS, $rA, $rB", LdStSTD,
545 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
546 "stdux $rS, $rA, $rB", LdStSTD,
548 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
549 "stvebx $rS, $rA, $rB", LdStGeneral,
551 def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
552 "stvehx $rS, $rA, $rB", LdStGeneral,
554 def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
555 "stvewx $rS, $rA, $rB", LdStGeneral,
557 def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
558 "stvx $rS, $dst", LdStGeneral,
559 [(store (v4f32 VRRC:$rS), xoaddr:$dst)]>;
561 let PPC970_Unit = 1 in { // FXU Operations.
562 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
563 "srawi $rA, $rS, $SH", IntShift,
564 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
565 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
566 "cntlzw $rA, $rS", IntGeneral,
567 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
568 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
569 "extsb $rA, $rS", IntGeneral,
570 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
571 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
572 "extsh $rA, $rS", IntGeneral,
573 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
574 def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
575 "extsw $rA, $rS", IntGeneral,
576 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
577 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
578 "cmp $crD, $long, $rA, $rB", IntCompare>;
579 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
580 "cmpl $crD, $long, $rA, $rB", IntCompare>;
581 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
582 "cmpw $crD, $rA, $rB", IntCompare>;
583 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
584 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
585 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
586 "cmplw $crD, $rA, $rB", IntCompare>;
587 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
588 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
590 let PPC970_Unit = 3 in { // FPU Operations.
591 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
592 // "fcmpo $crD, $fA, $fB", FPCompare>;
593 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
594 "fcmpu $crD, $fA, $fB", FPCompare>;
595 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
596 "fcmpu $crD, $fA, $fB", FPCompare>;
598 let isLoad = 1, PPC970_Unit = 2 in {
599 def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src),
600 "lfsx $frD, $src", LdStLFDU,
601 [(set F4RC:$frD, (load xaddr:$src))]>;
602 def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
603 "lfdx $frD, $src", LdStLFDU,
604 [(set F8RC:$frD, (load xaddr:$src))]>;
606 let PPC970_Unit = 3 in { // FPU Operations.
607 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
608 "fcfid $frD, $frB", FPGeneral,
609 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
610 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
611 "fctidz $frD, $frB", FPGeneral,
612 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
613 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
614 "fctiwz $frD, $frB", FPGeneral,
615 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
616 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
617 "frsp $frD, $frB", FPGeneral,
618 [(set F4RC:$frD, (fround F8RC:$frB))]>;
619 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
620 "fsqrt $frD, $frB", FPSqrt,
621 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
622 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
623 "fsqrts $frD, $frB", FPSqrt,
624 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
627 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
629 /// Note that these are defined as pseudo-ops on the PPC970 because they are
630 /// often coallesced away and we don't want the dispatch group builder to think
631 /// that they will fill slots (which could cause the load of a LSU reject to
632 /// sneak into a d-group with a store).
633 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
634 "fmr $frD, $frB", FPGeneral,
635 []>, // (set F4RC:$frD, F4RC:$frB)
637 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
638 "fmr $frD, $frB", FPGeneral,
639 []>, // (set F8RC:$frD, F8RC:$frB)
641 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
642 "fmr $frD, $frB", FPGeneral,
643 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
646 let PPC970_Unit = 3 in { // FPU Operations.
647 // These are artificially split into two different forms, for 4/8 byte FP.
648 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
649 "fabs $frD, $frB", FPGeneral,
650 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
651 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
652 "fabs $frD, $frB", FPGeneral,
653 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
654 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
655 "fnabs $frD, $frB", FPGeneral,
656 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
657 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
658 "fnabs $frD, $frB", FPGeneral,
659 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
660 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
661 "fneg $frD, $frB", FPGeneral,
662 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
663 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
664 "fneg $frD, $frB", FPGeneral,
665 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
668 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
669 def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst),
670 "stfiwx $frS, $dst", LdStUX,
671 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
672 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst),
673 "stfsx $frS, $dst", LdStUX,
674 [(store F4RC:$frS, xaddr:$dst)]>;
675 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst),
676 "stfdx $frS, $dst", LdStUX,
677 [(store F8RC:$frS, xaddr:$dst)]>;
680 // XL-Form instructions. condition register logical ops.
682 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
683 "mcrf $BF, $BFA", BrMCR>,
684 PPC970_DGroup_First, PPC970_Unit_CRU;
686 // XFX-Form instructions. Instructions that deal with SPRs.
688 def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>,
689 PPC970_DGroup_First, PPC970_Unit_FXU;
690 def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>,
691 PPC970_DGroup_First, PPC970_Unit_FXU;
692 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>,
693 PPC970_MicroCode, PPC970_Unit_CRU;
694 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
695 "mtcrf $FXM, $rS", BrMCRX>,
696 PPC970_MicroCode, PPC970_Unit_CRU;
697 def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
698 "mfcr $rT, $FXM", SprMFCR>,
699 PPC970_DGroup_First, PPC970_Unit_CRU;
700 def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>,
701 PPC970_DGroup_First, PPC970_Unit_FXU;
702 def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>,
703 PPC970_DGroup_First, PPC970_Unit_FXU;
704 def MTSPR : XFXForm_7<31, 467, (ops GPRC:$rS, u16imm:$UIMM), "mtspr $UIMM, $rS",
706 PPC970_DGroup_Single, PPC970_Unit_FXU;
708 // XS-Form instructions. Just 'sradi'
710 let PPC970_Unit = 1 in { // FXU Operations.
711 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
712 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
714 // XO-Form instructions. Arithmetic instructions that can set overflow bit
716 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
717 "add $rT, $rA, $rB", IntGeneral,
718 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
719 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
720 "add $rT, $rA, $rB", IntGeneral,
721 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
722 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
723 "addc $rT, $rA, $rB", IntGeneral,
724 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>;
725 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
726 "adde $rT, $rA, $rB", IntGeneral,
727 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
728 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
729 "divd $rT, $rA, $rB", IntDivD,
730 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
732 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
733 "divdu $rT, $rA, $rB", IntDivD,
734 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
736 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
737 "divw $rT, $rA, $rB", IntDivW,
738 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
740 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
741 "divwu $rT, $rA, $rB", IntDivW,
742 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
744 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
745 "mulhd $rT, $rA, $rB", IntMulHW,
746 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
747 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
748 "mulhdu $rT, $rA, $rB", IntMulHWU,
749 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
750 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
751 "mulhw $rT, $rA, $rB", IntMulHW,
752 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
753 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
754 "mulhwu $rT, $rA, $rB", IntMulHWU,
755 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
756 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
757 "mulld $rT, $rA, $rB", IntMulHD,
758 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
759 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
760 "mullw $rT, $rA, $rB", IntMulHW,
761 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
762 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
763 "subf $rT, $rA, $rB", IntGeneral,
764 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
765 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
766 "subfc $rT, $rA, $rB", IntGeneral,
767 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>;
768 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
769 "subfe $rT, $rA, $rB", IntGeneral,
770 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
771 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
772 "addme $rT, $rA", IntGeneral,
773 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
774 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
775 "addze $rT, $rA", IntGeneral,
776 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
777 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
778 "neg $rT, $rA", IntGeneral,
779 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
780 def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA),
781 "subfme $rT, $rA", IntGeneral,
782 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
783 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
784 "subfze $rT, $rA", IntGeneral,
785 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
788 // A-Form instructions. Most of the instructions executed in the FPU are of
791 let PPC970_Unit = 3 in { // FPU Operations.
792 def FMADD : AForm_1<63, 29,
793 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
794 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
795 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
797 Requires<[FPContractions]>;
798 def FMADDS : AForm_1<59, 29,
799 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
800 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
801 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
803 Requires<[FPContractions]>;
804 def FMSUB : AForm_1<63, 28,
805 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
806 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
807 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
809 Requires<[FPContractions]>;
810 def FMSUBS : AForm_1<59, 28,
811 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
812 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
813 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
815 Requires<[FPContractions]>;
816 def FNMADD : AForm_1<63, 31,
817 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
818 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
819 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
821 Requires<[FPContractions]>;
822 def FNMADDS : AForm_1<59, 31,
823 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
824 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
825 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
827 Requires<[FPContractions]>;
828 def FNMSUB : AForm_1<63, 30,
829 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
830 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
831 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
833 Requires<[FPContractions]>;
834 def FNMSUBS : AForm_1<59, 30,
835 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
836 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
837 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
839 Requires<[FPContractions]>;
840 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
841 // having 4 of these, force the comparison to always be an 8-byte double (code
842 // should use an FMRSD if the input comparison value really wants to be a float)
843 // and 4/8 byte forms for the result and operand type..
844 def FSELD : AForm_1<63, 23,
845 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
846 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
847 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
848 def FSELS : AForm_1<63, 23,
849 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
850 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
851 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
852 def FADD : AForm_2<63, 21,
853 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
854 "fadd $FRT, $FRA, $FRB", FPGeneral,
855 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
856 def FADDS : AForm_2<59, 21,
857 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
858 "fadds $FRT, $FRA, $FRB", FPGeneral,
859 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
860 def FDIV : AForm_2<63, 18,
861 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
862 "fdiv $FRT, $FRA, $FRB", FPDivD,
863 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
864 def FDIVS : AForm_2<59, 18,
865 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
866 "fdivs $FRT, $FRA, $FRB", FPDivS,
867 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
868 def FMUL : AForm_3<63, 25,
869 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
870 "fmul $FRT, $FRA, $FRB", FPFused,
871 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
872 def FMULS : AForm_3<59, 25,
873 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
874 "fmuls $FRT, $FRA, $FRB", FPGeneral,
875 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
876 def FSUB : AForm_2<63, 20,
877 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
878 "fsub $FRT, $FRA, $FRB", FPGeneral,
879 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
880 def FSUBS : AForm_2<59, 20,
881 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
882 "fsubs $FRT, $FRA, $FRB", FPGeneral,
883 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
886 let PPC970_Unit = 1 in { // FXU Operations.
887 // M-Form instructions. rotate and mask instructions.
889 let isTwoAddress = 1, isCommutable = 1 in {
890 // RLWIMI can be commuted if the rotate amount is zero.
891 def RLWIMI : MForm_2<20,
892 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
893 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
895 def RLDIMI : MDForm_1<30, 3,
896 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
897 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
900 def RLWINM : MForm_2<21,
901 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
902 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
904 def RLWINMo : MForm_2<21,
905 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
906 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
908 def RLWNM : MForm_2<23,
909 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
910 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
913 // MD-Form instructions. 64 bit rotate instructions.
915 def RLDICL : MDForm_1<30, 0,
916 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
917 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
919 def RLDICR : MDForm_1<30, 1,
920 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
921 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
925 let PPC970_Unit = 5 in { // VALU Operations.
926 // VA-Form instructions. 3-input AltiVec ops.
927 def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
928 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
929 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
931 Requires<[FPContractions]>;
932 def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
933 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
934 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA,
937 Requires<[FPContractions]>;
939 // VX-Form instructions. AltiVec arithmetic ops.
940 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
941 "vaddfp $vD, $vA, $vB", VecFP,
942 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
943 def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
944 "vadduwm $vD, $vA, $vB", VecGeneral,
945 [(set VRRC:$vD, (add VRRC:$vA, VRRC:$vB))]>;
946 def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
947 "vcfsx $vD, $vB, $UIMM", VecFP,
949 def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
950 "vcfux $vD, $vB, $UIMM", VecFP,
952 def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
953 "vctsxs $vD, $vB, $UIMM", VecFP,
955 def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
956 "vctuxs $vD, $vB, $UIMM", VecFP,
958 def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
959 "vexptefp $vD, $vB", VecFP,
961 def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
962 "vlogefp $vD, $vB", VecFP,
964 def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
965 "vmaxfp $vD, $vA, $vB", VecFP,
967 def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
968 "vminfp $vD, $vA, $vB", VecFP,
970 def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
971 "vrefp $vD, $vB", VecFP,
973 def VRFIM : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB),
974 "vrfim $vD, $vB", VecFP,
976 def VRFIN : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB),
977 "vrfin $vD, $vB", VecFP,
979 def VRFIP : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB),
980 "vrfip $vD, $vB", VecFP,
982 def VRFIZ : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB),
983 "vrfiz $vD, $vB", VecFP,
985 def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
986 "vrsqrtefp $vD, $vB", VecFP,
988 def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
989 "vsubfp $vD, $vA, $vB", VecFP,
990 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
991 def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
992 "vxor $vD, $vA, $vB", VecFP,
995 // VX-Form Pseudo Instructions
997 def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
998 "vxor $vD, $vD, $vD", VecFP,
1002 //===----------------------------------------------------------------------===//
1003 // DWARF Pseudo Instructions
1006 def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
1007 "; .loc $file, $line, $col",
1008 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
1011 def DWARF_LABEL : Pseudo<(ops i32imm:$id),
1013 [(dwarf_label (i32 imm:$id))]>;
1015 //===----------------------------------------------------------------------===//
1016 // PowerPC Instruction Patterns
1019 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1020 def : Pat<(i32 imm:$imm),
1021 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1023 // Implement the 'not' operation with the NOR instruction.
1024 def NOT : Pat<(not GPRC:$in),
1025 (NOR GPRC:$in, GPRC:$in)>;
1027 // ADD an arbitrary immediate.
1028 def : Pat<(add GPRC:$in, imm:$imm),
1029 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1030 // OR an arbitrary immediate.
1031 def : Pat<(or GPRC:$in, imm:$imm),
1032 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1033 // XOR an arbitrary immediate.
1034 def : Pat<(xor GPRC:$in, imm:$imm),
1035 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1037 def : Pat<(subc immSExt16:$imm, GPRC:$in),
1038 (SUBFIC GPRC:$in, imm:$imm)>;
1040 // Return void support.
1041 def : Pat<(ret), (BLR)>;
1044 def : Pat<(i64 (zext GPRC:$in)),
1045 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
1046 def : Pat<(i64 (anyext GPRC:$in)),
1047 (OR4To8 GPRC:$in, GPRC:$in)>;
1048 def : Pat<(i32 (trunc G8RC:$in)),
1049 (OR8To4 G8RC:$in, G8RC:$in)>;
1052 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1053 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1054 def : Pat<(shl G8RC:$in, (i64 imm:$imm)),
1055 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
1057 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1058 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1059 def : Pat<(srl G8RC:$in, (i64 imm:$imm)),
1060 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
1063 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1064 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1065 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1066 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1068 // Hi and Lo for Darwin Global Addresses.
1069 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1070 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1071 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1072 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1073 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1074 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1075 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1076 (ADDIS GPRC:$in, tconstpool:$g)>;
1078 def : Pat<(fmul VRRC:$vA, VRRC:$vB),
1079 (VMADDFP VRRC:$vA, (V_SET0), VRRC:$vB)>;
1081 // Fused negative multiply subtract, alternate pattern
1082 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1083 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1084 Requires<[FPContractions]>;
1085 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1086 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1087 Requires<[FPContractions]>;
1089 // Fused multiply add and multiply sub for packed float. These are represented
1090 // separately from the real instructions above, for operations that must have
1091 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
1092 def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
1093 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
1094 def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
1095 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
1097 // Standard shifts. These are represented separately from the real shifts above
1098 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1100 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1101 (SRAW GPRC:$rS, GPRC:$rB)>;
1102 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1103 (SRW GPRC:$rS, GPRC:$rB)>;
1104 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1105 (SLW GPRC:$rS, GPRC:$rB)>;
1107 def : Pat<(i32 (zextload iaddr:$src, i1)),
1109 def : Pat<(i32 (zextload xaddr:$src, i1)),
1111 def : Pat<(i32 (extload iaddr:$src, i1)),
1113 def : Pat<(i32 (extload xaddr:$src, i1)),
1115 def : Pat<(i32 (extload iaddr:$src, i8)),
1117 def : Pat<(i32 (extload xaddr:$src, i8)),
1119 def : Pat<(i32 (extload iaddr:$src, i16)),
1121 def : Pat<(i32 (extload xaddr:$src, i16)),
1123 def : Pat<(f64 (extload iaddr:$src, f32)),
1124 (FMRSD (LFS iaddr:$src))>;
1125 def : Pat<(f64 (extload xaddr:$src, f32)),
1126 (FMRSD (LFSX xaddr:$src))>;
1128 def : Pat<(v4i32 (load xoaddr:$src)),
1129 (v4i32 (LVX xoaddr:$src))>;
1130 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
1131 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
1133 // Same as above, but using a temporary. FIXME: implement temporaries :)
1135 def : Pattern<(xor GPRC:$in, imm:$imm),
1136 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
1137 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;